Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	347971801	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347971801	0	0
T1	7284984	207532	0	0
T2	4794552	101049	0	0
T3	1970752	53790	0	0
T4	9021152	294173	0	0
T5	15612632	300068	0	0
T14	23128	633	0	0
T17	19848080	1673987	0	0
T18	43706208	779121	0	0
T19	1139264	28123	0	0
T20	151424	6205	0	0
T21	0	4182	0	0
T22	0	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7284984	7282352	0	0
T2	4794552	4792256	0	0
T3	1970752	1968904	0	0
T4	9021152	9019640	0	0
T5	15612632	15549296	0	0
T14	23128	21952	0	0
T17	19848080	19848024	0	0
T18	43706208	43705032	0	0
T19	1139264	1136968	0	0
T20	151424	149072	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7284984	7282352	0	0
T2	4794552	4792256	0	0
T3	1970752	1968904	0	0
T4	9021152	9019640	0	0
T5	15612632	15549296	0	0
T14	23128	21952	0	0
T17	19848080	19848024	0	0
T18	43706208	43705032	0	0
T19	1139264	1136968	0	0
T20	151424	149072	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7284984	7282352	0	0
T2	4794552	4792256	0	0
T3	1970752	1968904	0	0
T4	9021152	9019640	0	0
T5	15612632	15549296	0	0
T14	23128	21952	0	0
T17	19848080	19848024	0	0
T18	43706208	43705032	0	0
T19	1139264	1136968	0	0
T20	151424	149072	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	129992226	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	129992226	0	0
T1	130089	126182	0	0
T2	85617	45345	0	0
T3	35192	12450	0	0
T4	161092	159039	0	0
T5	278797	123523	0	0
T14	413	246	0	0
T17	354430	19505	0	0
T18	780468	761564	0	0
T19	20344	12147	0	0
T20	2704	2413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	89646316	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	89646316	0	0
T1	130089	40275	0	0
T2	85617	12348	0	0
T3	35192	14445	0	0
T4	161092	67342	0	0
T5	278797	41911	0	0
T14	413	129	0	0
T17	354430	148745	0	0
T18	780468	5389	0	0
T19	20344	5364	0	0
T20	2704	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1481363	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1481363	0	0
T1	130089	40	0	0
T2	85617	2311	0	0
T3	35192	1325	0	0
T4	161092	24	0	0
T5	278797	6877	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	290	0	0
T19	20344	208	0	0
T20	2704	37	0	0
T21	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	4149247	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	4149247	0	0
T1	130089	2345	0	0
T2	85617	951	0	0
T3	35192	2049	0	0
T4	161092	2031	0	0
T5	278797	2928	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	73	0	0
T19	20344	144	0	0
T20	2704	37	0	0
T21	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1383599	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1383599	0	0
T1	130089	28	0	0
T2	85617	652	0	0
T3	35192	0	0	0
T4	161092	26	0	0
T5	278797	1346	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	230	0	0
T19	20344	143	0	0
T20	2704	53	0	0
T21	0	90	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3375240	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3375240	0	0
T1	130089	627	0	0
T2	85617	197	0	0
T3	35192	0	0	0
T4	161092	2163	0	0
T5	278797	534	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	51	0	0
T19	20344	154	0	0
T20	2704	53	0	0
T21	0	90	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1472524	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1472524	0	0
T1	130089	17	0	0
T2	85617	2742	0	0
T3	35192	0	0	0
T4	161092	59	0	0
T5	278797	3780	0	0
T14	413	2	0	0
T17	354430	1220	0	0
T18	780468	172	0	0
T19	20344	137	0	0
T20	2704	56	0	0
T21	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3464175	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3464175	0	0
T1	130089	1670	0	0
T2	85617	1144	0	0
T3	35192	0	0	0
T4	161092	4285	0	0
T5	278797	1688	0	0
T14	413	2	0	0
T17	354430	98169	0	0
T18	780468	49	0	0
T19	20344	202	0	0
T20	2704	56	0	0
T21	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1434330	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1434330	0	0
T1	130089	21	0	0
T2	85617	537	0	0
T3	35192	0	0	0
T4	161092	31	0	0
T5	278797	5013	0	0
T14	413	5	0	0
T17	354430	0	0	0
T18	780468	206	0	0
T19	20344	128	0	0
T20	2704	44	0	0
T21	0	83	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2802491	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2802491	0	0
T1	130089	1005	0	0
T2	85617	186	0	0
T3	35192	0	0	0
T4	161092	3113	0	0
T5	278797	2202	0	0
T14	413	5	0	0
T17	354430	0	0	0
T18	780468	60	0	0
T19	20344	152	0	0
T20	2704	44	0	0
T21	0	83	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1466335	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1466335	0	0
T1	130089	32	0	0
T2	85617	458	0	0
T3	35192	0	0	0
T4	161092	30	0	0
T5	278797	1662	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	237	0	0
T19	20344	213	0	0
T20	2704	39	0	0
T21	0	83	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3090642	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3090642	0	0
T1	130089	1378	0	0
T2	85617	212	0	0
T3	35192	0	0	0
T4	161092	1321	0	0
T5	278797	576	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	63	0	0
T19	20344	200	0	0
T20	2704	39	0	0
T21	0	83	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1456451	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1456451	0	0
T1	130089	48	0	0
T2	85617	465	0	0
T3	35192	0	0	0
T4	161092	8	0	0
T5	278797	1363	0	0
T14	413	5	0	0
T17	354430	1210	0	0
T18	780468	227	0	0
T19	20344	94	0	0
T20	2704	42	0	0
T21	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3159847	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3159847	0	0
T1	130089	735	0	0
T2	85617	192	0	0
T3	35192	0	0	0
T4	161092	434	0	0
T5	278797	689	0	0
T14	413	5	0	0
T17	354430	92375	0	0
T18	780468	56	0	0
T19	20344	151	0	0
T20	2704	42	0	0
T21	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1460365	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1460365	0	0
T1	130089	24	0	0
T2	85617	549	0	0
T3	35192	0	0	0
T4	161092	40	0	0
T5	278797	5879	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	228	0	0
T19	20344	225	0	0
T20	2704	48	0	0
T21	0	83	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3365507	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3365507	0	0
T1	130089	936	0	0
T2	85617	164	0	0
T3	35192	0	0	0
T4	161092	4916	0	0
T5	278797	2517	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	531	0	0
T19	20344	246	0	0
T20	2704	48	0	0
T21	0	83	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1480093	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1480093	0	0
T1	130089	26	0	0
T2	85617	4451	0	0
T3	35192	0	0	0
T4	161092	36	0	0
T5	278797	2680	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	210	0	0
T19	20344	234	0	0
T20	2704	50	0	0
T21	0	92	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3618087	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3618087	0	0
T1	130089	515	0	0
T2	85617	1929	0	0
T3	35192	0	0	0
T4	161092	2244	0	0
T5	278797	1597	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	444	0	0
T19	20344	233	0	0
T20	2704	50	0	0
T21	0	92	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1448240	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1448240	0	0
T1	130089	32	0	0
T2	85617	470	0	0
T3	35192	0	0	0
T4	161092	18	0	0
T5	278797	3078	0	0
T14	413	1	0	0
T17	354430	1203	0	0
T18	780468	248	0	0
T19	20344	249	0	0
T20	2704	42	0	0
T21	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3394044	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3394044	0	0
T1	130089	2261	0	0
T2	85617	239	0	0
T3	35192	0	0	0
T4	161092	1185	0	0
T5	278797	1406	0	0
T14	413	1	0	0
T17	354430	88453	0	0
T18	780468	55	0	0
T19	20344	243	0	0
T20	2704	42	0	0
T21	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1478021	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1478021	0	0
T1	130089	28	0	0
T2	85617	519	0	0
T3	35192	0	0	0
T4	161092	26	0	0
T5	278797	1609	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	237	0	0
T19	20344	267	0	0
T20	2704	57	0	0
T21	0	88	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2566253	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2566253	0	0
T1	130089	1667	0	0
T2	85617	261	0	0
T3	35192	0	0	0
T4	161092	3288	0	0
T5	278797	618	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	49	0	0
T19	20344	221	0	0
T20	2704	57	0	0
T21	0	88	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1459729	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1459729	0	0
T1	130089	66	0	0
T2	85617	622	0	0
T3	35192	0	0	0
T4	161092	23	0	0
T5	278797	1452	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	200	0	0
T19	20344	167	0	0
T20	2704	52	0	0
T21	0	85	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3852796	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3852796	0	0
T1	130089	2680	0	0
T2	85617	191	0	0
T3	35192	0	0	0
T4	161092	871	0	0
T5	278797	535	0	0
T14	413	7	0	0
T17	354430	0	0	0
T18	780468	52	0	0
T19	20344	165	0	0
T20	2704	52	0	0
T21	0	85	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1406272	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1406272	0	0
T1	130089	57	0	0
T2	85617	312	0	0
T3	35192	0	0	0
T4	161092	29	0	0
T5	278797	3374	0	0
T14	413	4	0	0
T17	354430	2013	0	0
T18	780468	340	0	0
T19	20344	153	0	0
T20	2704	47	0	0
T21	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2941336	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2941336	0	0
T1	130089	1926	0	0
T2	85617	185	0	0
T3	35192	0	0	0
T4	161092	2250	0	0
T5	278797	1507	0	0
T14	413	4	0	0
T17	354430	162468	0	0
T18	780468	79	0	0
T19	20344	199	0	0
T20	2704	47	0	0
T21	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1477403	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1477403	0	0
T1	130089	40	0	0
T2	85617	498	0	0
T3	35192	0	0	0
T4	161092	6	0	0
T5	278797	3468	0	0
T14	413	3	0	0
T17	354430	2914	0	0
T18	780468	302	0	0
T19	20344	228	0	0
T20	2704	39	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3935635	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3935635	0	0
T1	130089	2657	0	0
T2	85617	133	0	0
T3	35192	0	0	0
T4	161092	956	0	0
T5	278797	1528	0	0
T14	413	3	0	0
T17	354430	228434	0	0
T18	780468	329	0	0
T19	20344	241	0	0
T20	2704	39	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1464464	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1464464	0	0
T1	130089	49	0	0
T2	85617	506	0	0
T3	35192	0	0	0
T4	161092	26	0	0
T5	278797	9696	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	262	0	0
T19	20344	252	0	0
T20	2704	35	0	0
T21	0	79	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3568304	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3568304	0	0
T1	130089	3979	0	0
T2	85617	228	0	0
T3	35192	0	0	0
T4	161092	3828	0	0
T5	278797	3818	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	54	0	0
T19	20344	211	0	0
T20	2704	35	0	0
T21	0	79	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1451035	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1451035	0	0
T1	130089	7	0	0
T2	85617	567	0	0
T3	35192	0	0	0
T4	161092	36	0	0
T5	278797	3116	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	289	0	0
T19	20344	172	0	0
T20	2704	52	0	0
T21	0	71	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3412317	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3412317	0	0
T1	130089	33	0	0
T2	85617	221	0	0
T3	35192	0	0	0
T4	161092	3032	0	0
T5	278797	1356	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	75	0	0
T19	20344	248	0	0
T20	2704	52	0	0
T21	0	71	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1479296	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1479296	0	0
T1	130089	18	0	0
T2	85617	2169	0	0
T3	35192	3609	0	0
T4	161092	43	0	0
T5	278797	2954	0	0
T14	413	4	0	0
T17	354430	3573	0	0
T18	780468	244	0	0
T19	20344	179	0	0
T20	2704	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2977269	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2977269	0	0
T1	130089	2472	0	0
T2	85617	944	0	0
T3	35192	3665	0	0
T4	161092	3568	0	0
T5	278797	1737	0	0
T14	413	4	0	0
T17	354430	284060	0	0
T18	780468	237	0	0
T19	20344	158	0	0
T20	2704	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1452632	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1452632	0	0
T1	130089	13	0	0
T2	85617	2361	0	0
T3	35192	1760	0	0
T4	161092	29	0	0
T5	278797	1311	0	0
T14	413	5	0	0
T17	354430	1195	0	0
T18	780468	184	0	0
T19	20344	193	0	0
T20	2704	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3921307	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3921307	0	0
T1	130089	1585	0	0
T2	85617	1026	0	0
T3	35192	1757	0	0
T4	161092	3613	0	0
T5	278797	497	0	0
T14	413	5	0	0
T17	354430	98802	0	0
T18	780468	51	0	0
T19	20344	147	0	0
T20	2704	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1481800	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1481800	0	0
T1	130089	15	0	0
T2	85617	450	0	0
T3	35192	0	0	0
T4	161092	13	0	0
T5	278797	5960	0	0
T14	413	6	0	0
T17	354430	1102	0	0
T18	780468	270	0	0
T19	20344	248	0	0
T20	2704	47	0	0
T21	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2906629	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2906629	0	0
T1	130089	1406	0	0
T2	85617	164	0	0
T3	35192	0	0	0
T4	161092	1710	0	0
T5	278797	2757	0	0
T14	413	6	0	0
T17	354430	81473	0	0
T18	780468	62	0	0
T19	20344	190	0	0
T20	2704	47	0	0
T21	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1553220	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1553220	0	0
T1	130089	11	0	0
T2	85617	432	0	0
T3	35192	3167	0	0
T4	161092	18	0	0
T5	278797	5223	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	236	0	0
T19	20344	160	0	0
T20	2704	47	0	0
T21	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3572336	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3572336	0	0
T1	130089	500	0	0
T2	85617	186	0	0
T3	35192	4345	0	0
T4	161092	2357	0	0
T5	278797	2496	0	0
T14	413	3	0	0
T17	354430	0	0	0
T18	780468	685	0	0
T19	20344	152	0	0
T20	2704	47	0	0
T21	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1486079	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1486079	0	0
T1	130089	17	0	0
T2	85617	4571	0	0
T3	35192	0	0	0
T4	161092	36	0	0
T5	278797	1615	0	0
T14	413	10	0	0
T17	354430	0	0	0
T18	780468	206	0	0
T19	20344	207	0	0
T20	2704	47	0	0
T21	0	74	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3751249	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3751249	0	0
T1	130089	729	0	0
T2	85617	1666	0	0
T3	35192	0	0	0
T4	161092	2966	0	0
T5	278797	733	0	0
T14	413	10	0	0
T17	354430	0	0	0
T18	780468	559	0	0
T19	20344	199	0	0
T20	2704	47	0	0
T21	0	74	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1461776	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1461776	0	0
T1	130089	43	0	0
T2	85617	382	0	0
T3	35192	0	0	0
T4	161092	25	0	0
T5	278797	2334	0	0
T14	413	4	0	0
T17	354430	2267	0	0
T18	780468	281	0	0
T19	20344	169	0	0
T20	2704	58	0	0
T21	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2726548	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2726548	0	0
T1	130089	201	0	0
T2	85617	120	0	0
T3	35192	0	0	0
T4	161092	2479	0	0
T5	278797	1024	0	0
T14	413	4	0	0
T17	354430	173260	0	0
T18	780468	60	0	0
T19	20344	242	0	0
T20	2704	58	0	0
T21	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1477542	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1477542	0	0
T1	130089	44	0	0
T2	85617	398	0	0
T3	35192	0	0	0
T4	161092	39	0	0
T5	278797	1712	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	247	0	0
T19	20344	202	0	0
T20	2704	42	0	0
T21	0	88	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3097670	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3097670	0	0
T1	130089	1831	0	0
T2	85617	116	0	0
T3	35192	0	0	0
T4	161092	3044	0	0
T5	278797	788	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	52	0	0
T19	20344	188	0	0
T20	2704	42	0	0
T21	0	88	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1450712	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1450712	0	0
T1	130089	33	0	0
T2	85617	605	0	0
T3	35192	2589	0	0
T4	161092	24	0	0
T5	278797	1627	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	334	0	0
T19	20344	201	0	0
T20	2704	63	0	0
T21	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3194873	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3194873	0	0
T1	130089	716	0	0
T2	85617	257	0	0
T3	35192	2629	0	0
T4	161092	3764	0	0
T5	278797	805	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	228	0	0
T19	20344	187	0	0
T20	2704	63	0	0
T21	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1494086	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1494086	0	0
T1	130089	5	0	0
T2	85617	506	0	0
T3	35192	0	0	0
T4	161092	34	0	0
T5	278797	6176	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	282	0	0
T19	20344	190	0	0
T20	2704	43	0	0
T21	0	95	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3193221	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3193221	0	0
T1	130089	663	0	0
T2	85617	174	0	0
T3	35192	0	0	0
T4	161092	2607	0	0
T5	278797	2740	0	0
T14	413	6	0	0
T17	354430	0	0	0
T18	780468	62	0	0
T19	20344	190	0	0
T20	2704	43	0	0
T21	0	95	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1469293	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1469293	0	0
T1	130089	21	0	0
T2	85617	2362	0	0
T3	35192	0	0	0
T4	161092	23	0	0
T5	278797	5197	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	307	0	0
T19	20344	272	0	0
T20	2704	46	0	0
T21	0	79	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2881994	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2881994	0	0
T1	130089	1632	0	0
T2	85617	958	0	0
T3	35192	0	0	0
T4	161092	1089	0	0
T5	278797	2186	0	0
T14	413	4	0	0
T17	354430	0	0	0
T18	780468	1085	0	0
T19	20344	330	0	0
T20	2704	46	0	0
T21	0	79	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1466239	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1466239	0	0
T1	130089	34	0	0
T2	85617	578	0	0
T3	35192	0	0	0
T4	161092	33	0	0
T5	278797	1251	0	0
T14	413	7	0	0
T17	354430	1176	0	0
T18	780468	243	0	0
T19	20344	210	0	0
T20	2704	38	0	0
T21	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	2594298	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	2594298	0	0
T1	130089	2806	0	0
T2	85617	148	0	0
T3	35192	0	0	0
T4	161092	1599	0	0
T5	278797	572	0	0
T14	413	7	0	0
T17	354430	92012	0	0
T18	780468	223	0	0
T19	20344	216	0	0
T20	2704	38	0	0
T21	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	1465910	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	1465910	0	0
T1	130089	31	0	0
T2	85617	536	0	0
T3	35192	0	0	0
T4	161092	37	0	0
T5	278797	3488	0	0
T14	413	5	0	0
T17	354430	1025	0	0
T18	780468	267	0	0
T19	20344	147	0	0
T20	2704	46	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307871406	3261135	0	0
DepthKnown_A	307871406	307750687	0	0
RvalidKnown_A	307871406	307750687	0	0
WreadyKnown_A	307871406	307750687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	3261135	0	0
T1	130089	1320	0	0
T2	85617	155	0	0
T3	35192	0	0	0
T4	161092	2307	0	0
T5	278797	1559	0	0
T14	413	5	0	0
T17	354430	87333	0	0
T18	780468	65	0	0
T19	20344	155	0	0
T20	2704	46	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307871406	307750687	0	0
T1	130089	130042	0	0
T2	85617	85576	0	0
T3	35192	35159	0	0
T4	161092	161065	0	0
T5	278797	277666	0	0
T14	413	392	0	0
T17	354430	354429	0	0
T18	780468	780447	0	0
T19	20344	20303	0	0
T20	2704	2662	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0