Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1611497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253159

1

T1

18

T2

11

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	631454	1			T1	35		T2	52		T3	2
values[0x0]	602191	1			T1	36		T2	39		T3	1
values[0x1]	631011	1			T1	44		T2	53		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615631

1

T1

45

T2

37

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7155	1			T4	6		T12	4		T13	1
valid_sources[0x01]	7510	1			T4	8		T12	3		T13	1
valid_sources[0x02]	6605	1			T2	1		T4	8		T12	4
valid_sources[0x03]	7011	1			T2	1		T12	4		T14	6
valid_sources[0x04]	6846	1			T4	2		T12	4		T26	1
valid_sources[0x05]	6951	1			T4	1		T12	4		T40	1
valid_sources[0x06]	7259	1			T4	10		T15	1		T12	4
valid_sources[0x07]	7152	1			T12	4		T26	2		T20	5
valid_sources[0x08]	6859	1			T12	4		T26	1		T20	16
valid_sources[0x09]	6491	1			T2	1		T4	1		T12	4
valid_sources[0x0a]	6579	1			T2	1		T12	4		T13	2
valid_sources[0x0b]	6693	1			T3	3		T4	11		T15	14
valid_sources[0x0c]	7731	1			T4	5		T15	25		T12	5
valid_sources[0x0d]	7018	1			T4	10		T12	4		T16	3
valid_sources[0x0e]	7972	1			T1	1		T12	3		T25	1
valid_sources[0x0f]	7631	1			T15	14		T12	4		T14	2
valid_sources[0x10]	6573	1			T1	1		T3	4		T4	1
valid_sources[0x11]	7358	1			T4	1		T12	4		T20	17
valid_sources[0x12]	6703	1			T12	4		T20	7		T21	27
valid_sources[0x13]	6393	1			T2	4		T4	6		T12	6
valid_sources[0x14]	7719	1			T12	3		T26	1		T20	9
valid_sources[0x15]	6759	1			T1	1		T2	1		T4	2
valid_sources[0x16]	7794	1			T2	3		T12	5		T14	51
valid_sources[0x17]	7173	1			T1	1		T2	2		T4	4
valid_sources[0x18]	8275	1			T4	3		T12	4		T14	24
valid_sources[0x19]	6993	1			T4	7		T12	4		T14	2
valid_sources[0x1a]	7436	1			T4	2		T12	4		T13	1
valid_sources[0x1b]	6809	1			T12	4		T26	1		T40	1
valid_sources[0x1c]	6437	1			T2	1		T12	4		T25	1
valid_sources[0x1d]	7244	1			T15	4		T12	4		T40	1
valid_sources[0x1e]	7604	1			T2	1		T4	1		T12	4
valid_sources[0x1f]	7386	1			T4	6		T12	4		T14	20
valid_sources[0x20]	6936	1			T4	4		T12	5		T14	5
valid_sources[0x21]	7279	1			T1	1		T4	6		T12	4
valid_sources[0x22]	7720	1			T4	4		T12	4		T25	1
valid_sources[0x23]	10217	1			T4	1		T15	58		T12	4
valid_sources[0x24]	7879	1			T1	3		T15	2		T12	5
valid_sources[0x25]	6867	1			T12	4		T14	4		T20	3
valid_sources[0x26]	8466	1			T1	3		T4	11		T12	5
valid_sources[0x27]	7837	1			T1	1		T2	1		T12	6
valid_sources[0x28]	8627	1			T2	3		T12	4		T13	1
valid_sources[0x29]	7086	1			T1	1		T2	1		T12	4
valid_sources[0x2a]	7454	1			T2	2		T12	4		T18	93
valid_sources[0x2b]	7647	1			T12	4		T19	246		T25	1
valid_sources[0x2c]	8222	1			T12	4		T20	5		T21	22
valid_sources[0x2d]	7160	1			T15	2		T12	4		T14	42
valid_sources[0x2e]	8221	1			T12	3		T20	4		T21	52
valid_sources[0x2f]	6936	1			T4	4		T12	5		T25	1
valid_sources[0x30]	6540	1			T1	2		T12	4		T25	1
valid_sources[0x31]	7350	1			T4	1		T12	5		T18	67
valid_sources[0x32]	6993	1			T4	2		T12	4		T13	1
valid_sources[0x33]	9359	1			T2	2		T4	5		T12	3
valid_sources[0x34]	6962	1			T12	4		T14	207		T20	11
valid_sources[0x35]	7250	1			T12	5		T40	2		T20	8
valid_sources[0x36]	7750	1			T2	1		T12	4		T13	1
valid_sources[0x37]	7025	1			T4	1		T12	4		T18	187
valid_sources[0x38]	6604	1			T1	2		T2	4		T15	58
valid_sources[0x39]	8101	1			T1	6		T12	5		T26	2
valid_sources[0x3a]	6787	1			T4	5		T15	18		T12	4
valid_sources[0x3b]	8638	1			T4	6		T12	3		T20	3
valid_sources[0x3c]	8730	1			T12	4		T14	9		T20	4
valid_sources[0x3d]	7391	1			T1	1		T2	1		T4	4
valid_sources[0x3e]	7229	1			T1	1		T2	1		T4	3
valid_sources[0x3f]	6484	1			T1	1		T12	6		T14	4
valid_sources[0x40]	7133	1			T1	1		T4	4		T12	4
valid_sources[0x41]	7445	1			T1	1		T12	5		T26	1
valid_sources[0x42]	6846	1			T12	4		T18	59		T40	2
valid_sources[0x43]	6908	1			T2	2		T12	4		T25	2
valid_sources[0x44]	6816	1			T2	1		T4	10		T12	3
valid_sources[0x45]	7683	1			T2	1		T4	1		T12	4
valid_sources[0x46]	6618	1			T4	12		T12	4		T20	7
valid_sources[0x47]	7602	1			T1	2		T12	4		T17	74
valid_sources[0x48]	8108	1			T4	15		T15	75		T12	3
valid_sources[0x49]	6644	1			T4	8		T12	5		T20	3
valid_sources[0x4a]	6584	1			T12	4		T13	1		T20	6
valid_sources[0x4b]	7524	1			T1	2		T2	3		T12	4
valid_sources[0x4c]	8898	1			T12	4		T14	12		T21	11
valid_sources[0x4d]	6876	1			T4	1		T15	10		T12	3
valid_sources[0x4e]	7188	1			T12	4		T20	10		T21	28
valid_sources[0x4f]	7166	1			T4	4		T12	4		T14	77
valid_sources[0x50]	8223	1			T4	2		T12	4		T25	1
valid_sources[0x51]	7343	1			T4	1		T12	4		T21	2
valid_sources[0x52]	6943	1			T2	5		T4	1		T12	5
valid_sources[0x53]	6955	1			T1	2		T4	8		T12	4
valid_sources[0x54]	7244	1			T1	2		T4	5		T12	3
valid_sources[0x55]	7965	1			T4	5		T12	4		T19	88
valid_sources[0x56]	6945	1			T1	1		T2	1		T12	4
valid_sources[0x57]	6979	1			T1	1		T4	3		T12	4
valid_sources[0x58]	6638	1			T4	4		T12	5		T13	1
valid_sources[0x59]	6998	1			T4	12		T12	5		T14	6
valid_sources[0x5a]	7165	1			T4	4		T12	4		T14	59
valid_sources[0x5b]	6983	1			T2	1		T4	2		T12	3
valid_sources[0x5c]	8508	1			T12	5		T14	84		T18	115
valid_sources[0x5d]	6993	1			T2	2		T15	8		T12	4
valid_sources[0x5e]	6670	1			T2	3		T12	4		T14	10
valid_sources[0x5f]	6951	1			T2	1		T4	2		T12	4
valid_sources[0x60]	7258	1			T15	61		T12	4		T20	3
valid_sources[0x61]	7229	1			T12	4		T40	4		T20	15
valid_sources[0x62]	7257	1			T1	1		T2	2		T12	5
valid_sources[0x63]	6694	1			T2	1		T4	9		T12	4
valid_sources[0x64]	6711	1			T2	2		T4	5		T12	4
valid_sources[0x65]	6719	1			T1	1		T4	4		T12	5
valid_sources[0x66]	6784	1			T12	4		T20	4		T21	1
valid_sources[0x67]	6840	1			T1	2		T2	1		T4	4
valid_sources[0x68]	6485	1			T12	6		T26	2		T40	1
valid_sources[0x69]	8352	1			T12	3		T14	13		T26	1
valid_sources[0x6a]	6703	1			T12	4		T26	1		T40	2
valid_sources[0x6b]	6500	1			T12	4		T13	1		T40	1
valid_sources[0x6c]	6998	1			T1	2		T4	3		T12	4
valid_sources[0x6d]	7394	1			T1	2		T2	3		T4	1
valid_sources[0x6e]	7387	1			T12	4		T26	1		T20	6
valid_sources[0x6f]	7036	1			T2	1		T4	1		T15	65
valid_sources[0x70]	7748	1			T2	1		T4	15		T12	4
valid_sources[0x71]	7181	1			T1	1		T4	3		T12	5
valid_sources[0x72]	6861	1			T1	1		T2	1		T4	15
valid_sources[0x73]	6882	1			T4	2		T12	5		T40	1
valid_sources[0x74]	8344	1			T4	12		T12	4		T40	1
valid_sources[0x75]	7496	1			T2	2		T4	9		T12	4
valid_sources[0x76]	5928	1			T12	3		T20	14		T21	32
valid_sources[0x77]	7948	1			T4	5		T12	3		T16	30
valid_sources[0x78]	7657	1			T4	2		T12	4		T40	1
valid_sources[0x79]	7557	1			T1	1		T2	4		T4	2
valid_sources[0x7a]	6659	1			T1	1		T4	4		T12	5
valid_sources[0x7b]	6374	1			T1	2		T12	4		T25	1
valid_sources[0x7c]	7018	1			T12	5		T26	2		T40	1
valid_sources[0x7d]	6577	1			T2	1		T4	13		T12	5
valid_sources[0x7e]	7066	1			T4	4		T15	69		T12	4
valid_sources[0x7f]	6716	1			T1	5		T4	1		T12	5
valid_sources[0x80]	7473	1			T2	2		T4	1		T12	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26558

1

T4

6

T15

13

T12

13

values[0x0]

all_enables

biggest_size

200144

1

T1

17

T2

10

T3

1

values[0x1]

all_enables

biggest_size

26457

1

T1

1

T2

1

T4

7