Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335088940	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335088940	0	0
T1	6432858	127649	0	0
T2	7784224	150178	0	0
T3	18984	460	0	0
T4	44381624	871479	0	0
T12	50192072	759920	0	0
T13	66640	1904	0	0
T14	2320808	47871	0	0
T15	1303400	24785	0	0
T16	42728	530	0	0
T17	44856	730	0	0
T18	5092	1890	0	0
T19	0	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671112	6670216	0	0
T2	7784224	7779744	0	0
T3	18984	18200	0	0
T4	44381624	44377760	0	0
T12	50192072	50189328	0	0
T13	66640	64008	0	0
T14	2320808	2317224	0	0
T15	1303400	1300040	0	0
T16	42728	38472	0	0
T17	44856	40152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671112	6670216	0	0
T2	7784224	7779744	0	0
T3	18984	18200	0	0
T4	44381624	44377760	0	0
T12	50192072	50189328	0	0
T13	66640	64008	0	0
T14	2320808	2317224	0	0
T15	1303400	1300040	0	0
T16	42728	38472	0	0
T17	44856	40152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671112	6670216	0	0
T2	7784224	7779744	0	0
T3	18984	18200	0	0
T4	44381624	44377760	0	0
T12	50192072	50189328	0	0
T13	66640	64008	0	0
T14	2320808	2317224	0	0
T15	1303400	1300040	0	0
T16	42728	38472	0	0
T17	44856	40152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	124725936	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	124725936	0	0
T1	119127	56851	0	0
T2	139004	70349	0	0
T3	339	214	0	0
T4	792529	398694	0	0
T12	896287	4833	0	0
T13	1190	875	0	0
T14	41443	18418	0	0
T15	23275	11025	0	0
T16	763	206	0	0
T17	801	286	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	85580322	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	85580322	0	0
T1	119127	15138	0	0
T2	139004	17491	0	0
T3	339	128	0	0
T4	792529	101669	0	0
T12	896287	375127	0	0
T13	1190	521	0	0
T14	41443	15759	0	0
T15	23275	3096	0	0
T16	763	108	0	0
T17	801	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1472825	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1472825	0	0
T1	119127	2508	0	0
T2	139004	1428	0	0
T3	339	3	0	0
T4	792529	5336	0	0
T12	896287	0	0	0
T13	1190	12	0	0
T14	41443	333	0	0
T15	23275	350	0	0
T16	763	3	0	0
T17	801	6	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3665570	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3665570	0	0
T1	119127	335	0	0
T2	139004	616	0	0
T3	339	3	0	0
T4	792529	1837	0	0
T12	896287	0	0	0
T13	1190	12	0	0
T14	41443	260	0	0
T15	23275	103	0	0
T16	763	3	0	0
T17	801	6	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1470681	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1470681	0	0
T1	119127	1368	0	0
T2	139004	1482	0	0
T3	339	5	0	0
T4	792529	10498	0	0
T12	896287	0	0	0
T13	1190	3	0	0
T14	41443	244	0	0
T15	23275	195	0	0
T16	763	4	0	0
T17	801	3	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3484418	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3484418	0	0
T1	119127	289	0	0
T2	139004	816	0	0
T3	339	5	0	0
T4	792529	4826	0	0
T12	896287	0	0	0
T13	1190	3	0	0
T14	41443	167	0	0
T15	23275	81	0	0
T16	763	4	0	0
T17	801	3	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1480744	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1480744	0	0
T1	119127	980	0	0
T2	139004	3042	0	0
T3	339	1	0	0
T4	792529	9817	0	0
T12	896287	0	0	0
T13	1190	15	0	0
T14	41443	178	0	0
T15	23275	294	0	0
T16	763	2	0	0
T17	801	8	0	0
T18	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2698507	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2698507	0	0
T1	119127	427	0	0
T2	139004	1523	0	0
T3	339	1	0	0
T4	792529	3313	0	0
T12	896287	0	0	0
T13	1190	15	0	0
T14	41443	170	0	0
T15	23275	173	0	0
T16	763	2	0	0
T17	801	8	0	0
T18	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1489933	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1489933	0	0
T1	119127	901	0	0
T2	139004	519	0	0
T3	339	3	0	0
T4	792529	10050	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	267	0	0
T15	23275	227	0	0
T16	763	3	0	0
T17	801	11	0	0
T18	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2939757	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2939757	0	0
T1	119127	631	0	0
T2	139004	713	0	0
T3	339	3	0	0
T4	792529	3035	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	213	0	0
T15	23275	70	0	0
T16	763	3	0	0
T17	801	11	0	0
T18	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1473882	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1473882	0	0
T1	119127	1103	0	0
T2	139004	2512	0	0
T3	339	3	0	0
T4	792529	7425	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	257	0	0
T15	23275	231	0	0
T16	763	3	0	0
T17	801	3	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2871874	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2871874	0	0
T1	119127	449	0	0
T2	139004	1026	0	0
T3	339	3	0	0
T4	792529	3405	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	198	0	0
T15	23275	95	0	0
T16	763	3	0	0
T17	801	3	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1481909	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1481909	0	0
T1	119127	2162	0	0
T2	139004	1929	0	0
T3	339	0	0	0
T4	792529	9441	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	280	0	0
T15	23275	252	0	0
T16	763	4	0	0
T17	801	6	0	0
T18	0	47	0	0
T19	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3317043	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3317043	0	0
T1	119127	1293	0	0
T2	139004	519	0	0
T3	339	0	0	0
T4	792529	3827	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	222	0	0
T15	23275	111	0	0
T16	763	4	0	0
T17	801	6	0	0
T18	0	47	0	0
T19	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1495810	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1495810	0	0
T1	119127	2531	0	0
T2	139004	489	0	0
T3	339	1	0	0
T4	792529	11968	0	0
T12	896287	0	0	0
T13	1190	11	0	0
T14	41443	249	0	0
T15	23275	168	0	0
T16	763	0	0	0
T17	801	7	0	0
T18	0	31	0	0
T19	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3852701	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3852701	0	0
T1	119127	1853	0	0
T2	139004	20	0	0
T3	339	1	0	0
T4	792529	5084	0	0
T12	896287	0	0	0
T13	1190	11	0	0
T14	41443	307	0	0
T15	23275	71	0	0
T16	763	0	0	0
T17	801	7	0	0
T18	0	31	0	0
T19	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1507911	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1507911	0	0
T1	119127	999	0	0
T2	139004	441	0	0
T3	339	1	0	0
T4	792529	9791	0	0
T12	896287	0	0	0
T13	1190	12	0	0
T14	41443	306	0	0
T15	23275	303	0	0
T16	763	2	0	0
T17	801	5	0	0
T18	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2544607	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2544607	0	0
T1	119127	15	0	0
T2	139004	399	0	0
T3	339	1	0	0
T4	792529	2517	0	0
T12	896287	0	0	0
T13	1190	12	0	0
T14	41443	201	0	0
T15	23275	174	0	0
T16	763	2	0	0
T17	801	5	0	0
T18	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1434522	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1434522	0	0
T1	119127	1299	0	0
T2	139004	925	0	0
T3	339	3	0	0
T4	792529	11150	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	262	0	0
T15	23275	247	0	0
T16	763	2	0	0
T17	801	6	0	0
T18	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3093318	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3093318	0	0
T1	119127	163	0	0
T2	139004	313	0	0
T3	339	3	0	0
T4	792529	4642	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	233	0	0
T15	23275	116	0	0
T16	763	2	0	0
T17	801	6	0	0
T18	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1440486	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1440486	0	0
T1	119127	1383	0	0
T2	139004	1259	0	0
T3	339	0	0	0
T4	792529	12228	0	0
T12	896287	1293	0	0
T13	1190	9	0	0
T14	41443	226	0	0
T15	23275	297	0	0
T16	763	6	0	0
T17	801	5	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2479982	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2479982	0	0
T1	119127	433	0	0
T2	139004	642	0	0
T3	339	0	0	0
T4	792529	3476	0	0
T12	896287	100801	0	0
T13	1190	9	0	0
T14	41443	152	0	0
T15	23275	143	0	0
T16	763	6	0	0
T17	801	5	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1491166	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1491166	0	0
T1	119127	3369	0	0
T2	139004	1101	0	0
T3	339	3	0	0
T4	792529	8907	0	0
T12	896287	1020	0	0
T13	1190	10	0	0
T14	41443	332	0	0
T15	23275	392	0	0
T16	763	4	0	0
T17	801	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3627567	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3627567	0	0
T1	119127	971	0	0
T2	139004	442	0	0
T3	339	3	0	0
T4	792529	3442	0	0
T12	896287	80564	0	0
T13	1190	10	0	0
T14	41443	286	0	0
T15	23275	125	0	0
T16	763	4	0	0
T17	801	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1500083	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1500083	0	0
T1	119127	2413	0	0
T2	139004	2090	0	0
T3	339	2	0	0
T4	792529	13095	0	0
T12	896287	1334	0	0
T13	1190	9	0	0
T14	41443	328	0	0
T15	23275	211	0	0
T16	763	4	0	0
T17	801	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2928566	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2928566	0	0
T1	119127	451	0	0
T2	139004	1368	0	0
T3	339	2	0	0
T4	792529	5002	0	0
T12	896287	103694	0	0
T13	1190	9	0	0
T14	41443	351	0	0
T15	23275	154	0	0
T16	763	4	0	0
T17	801	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1501824	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1501824	0	0
T1	119127	1679	0	0
T2	139004	1116	0	0
T3	339	5	0	0
T4	792529	11600	0	0
T12	896287	0	0	0
T13	1190	9	0	0
T14	41443	383	0	0
T15	23275	331	0	0
T16	763	4	0	0
T17	801	1	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2483182	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2483182	0	0
T1	119127	903	0	0
T2	139004	107	0	0
T3	339	5	0	0
T4	792529	3384	0	0
T12	896287	0	0	0
T13	1190	9	0	0
T14	41443	326	0	0
T15	23275	135	0	0
T16	763	4	0	0
T17	801	1	0	0
T18	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1429781	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1429781	0	0
T1	119127	2194	0	0
T2	139004	1850	0	0
T3	339	1	0	0
T4	792529	6899	0	0
T12	896287	0	0	0
T13	1190	14	0	0
T14	41443	272	0	0
T15	23275	364	0	0
T16	763	4	0	0
T17	801	4	0	0
T18	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2735635	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2735635	0	0
T1	119127	973	0	0
T2	139004	191	0	0
T3	339	1	0	0
T4	792529	4799	0	0
T12	896287	0	0	0
T13	1190	14	0	0
T14	41443	326	0	0
T15	23275	117	0	0
T16	763	4	0	0
T17	801	4	0	0
T18	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1505936	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1505936	0	0
T1	119127	2636	0	0
T2	139004	2678	0	0
T3	339	1	0	0
T4	792529	11806	0	0
T12	896287	0	0	0
T13	1190	10	0	0
T14	41443	289	0	0
T15	23275	225	0	0
T16	763	6	0	0
T17	801	6	0	0
T18	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3413222	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3413222	0	0
T1	119127	454	0	0
T2	139004	785	0	0
T3	339	1	0	0
T4	792529	4870	0	0
T12	896287	0	0	0
T13	1190	10	0	0
T14	41443	283	0	0
T15	23275	100	0	0
T16	763	6	0	0
T17	801	6	0	0
T18	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1532136	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1532136	0	0
T1	119127	1443	0	0
T2	139004	1828	0	0
T3	339	2	0	0
T4	792529	12372	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	223	0	0
T15	23275	260	0	0
T16	763	2	0	0
T17	801	8	0	0
T18	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3266749	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3266749	0	0
T1	119127	453	0	0
T2	139004	1174	0	0
T3	339	2	0	0
T4	792529	4622	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	254	0	0
T15	23275	102	0	0
T16	763	2	0	0
T17	801	8	0	0
T18	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1502497	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1502497	0	0
T2	139004	2224	0	0
T3	339	1	0	0
T4	792529	10840	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	301	0	0
T15	23275	259	0	0
T16	763	8	0	0
T17	801	4	0	0
T18	2546	41	0	0
T19	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2555251	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2555251	0	0
T2	139004	193	0	0
T3	339	1	0	0
T4	792529	3528	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	296	0	0
T15	23275	98	0	0
T16	763	8	0	0
T17	801	4	0	0
T18	2546	41	0	0
T19	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1527608	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1527608	0	0
T1	119127	870	0	0
T2	139004	153	0	0
T3	339	6	0	0
T4	792529	10116	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	222	0	0
T15	23275	419	0	0
T16	763	4	0	0
T17	801	7	0	0
T18	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	4086208	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	4086208	0	0
T1	119127	126	0	0
T2	139004	315	0	0
T3	339	6	0	0
T4	792529	4325	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	252	0	0
T15	23275	136	0	0
T16	763	4	0	0
T17	801	7	0	0
T18	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1499450	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1499450	0	0
T1	119127	1897	0	0
T2	139004	727	0	0
T3	339	3	0	0
T4	792529	8386	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	258	0	0
T15	23275	351	0	0
T16	763	5	0	0
T17	801	6	0	0
T18	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2710974	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2710974	0	0
T1	119127	749	0	0
T2	139004	569	0	0
T3	339	3	0	0
T4	792529	3619	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	175	0	0
T15	23275	142	0	0
T16	763	5	0	0
T17	801	6	0	0
T18	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1474285	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1474285	0	0
T1	119127	909	0	0
T2	139004	1694	0	0
T3	339	2	0	0
T4	792529	10478	0	0
T12	896287	1186	0	0
T13	1190	6	0	0
T14	41443	252	0	0
T15	23275	179	0	0
T16	763	5	0	0
T17	801	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2840013	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2840013	0	0
T1	119127	522	0	0
T2	139004	1349	0	0
T3	339	2	0	0
T4	792529	3679	0	0
T12	896287	90068	0	0
T13	1190	6	0	0
T14	41443	292	0	0
T15	23275	76	0	0
T16	763	5	0	0
T17	801	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1493242	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1493242	0	0
T1	119127	1083	0	0
T2	139004	1580	0	0
T3	339	1	0	0
T4	792529	11787	0	0
T12	896287	0	0	0
T13	1190	11	0	0
T14	41443	286	0	0
T15	23275	303	0	0
T16	763	3	0	0
T17	801	1	0	0
T18	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3890937	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3890937	0	0
T1	119127	113	0	0
T2	139004	840	0	0
T3	339	1	0	0
T4	792529	3110	0	0
T12	896287	0	0	0
T13	1190	11	0	0
T14	41443	305	0	0
T15	23275	109	0	0
T16	763	3	0	0
T17	801	1	0	0
T18	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1465862	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1465862	0	0
T1	119127	879	0	0
T2	139004	4904	0	0
T3	339	5	0	0
T4	792529	10579	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	360	0	0
T15	23275	254	0	0
T16	763	5	0	0
T17	801	7	0	0
T18	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2555193	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2555193	0	0
T1	119127	919	0	0
T2	139004	1095	0	0
T3	339	5	0	0
T4	792529	3637	0	0
T12	896287	0	0	0
T13	1190	13	0	0
T14	41443	215	0	0
T15	23275	108	0	0
T16	763	5	0	0
T17	801	7	0	0
T18	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1474787	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1474787	0	0
T1	119127	740	0	0
T2	139004	1173	0	0
T3	339	1	0	0
T4	792529	10249	0	0
T12	896287	0	0	0
T13	1190	7	0	0
T14	41443	257	0	0
T15	23275	288	0	0
T16	763	5	0	0
T17	801	7	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3318697	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3318697	0	0
T1	119127	653	0	0
T2	139004	448	0	0
T3	339	1	0	0
T4	792529	4435	0	0
T12	896287	0	0	0
T13	1190	7	0	0
T14	41443	254	0	0
T15	23275	83	0	0
T16	763	5	0	0
T17	801	7	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1493979	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1493979	0	0
T1	119127	1212	0	0
T2	139004	879	0	0
T3	339	0	0	0
T4	792529	12887	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	255	0	0
T15	23275	260	0	0
T16	763	4	0	0
T17	801	4	0	0
T18	0	51	0	0
T19	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3365702	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3365702	0	0
T1	119127	69	0	0
T2	139004	2	0	0
T3	339	0	0	0
T4	792529	5473	0	0
T12	896287	0	0	0
T13	1190	8	0	0
T14	41443	259	0	0
T15	23275	144	0	0
T16	763	4	0	0
T17	801	4	0	0
T18	0	51	0	0
T19	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1450670	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1450670	0	0
T1	119127	1159	0	0
T2	139004	2192	0	0
T3	339	3	0	0
T4	792529	6078	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	148	0	0
T15	23275	275	0	0
T16	763	4	0	0
T17	801	2	0	0
T18	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	2803628	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	2803628	0	0
T1	119127	479	0	0
T2	139004	300	0	0
T3	339	3	0	0
T4	792529	2852	0	0
T12	896287	0	0	0
T13	1190	6	0	0
T14	41443	147	0	0
T15	23275	107	0	0
T16	763	4	0	0
T17	801	2	0	0
T18	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1460821	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1460821	0	0
T1	119127	732	0	0
T2	139004	2156	0	0
T3	339	2	0	0
T4	792529	6769	0	0
T12	896287	0	0	0
T13	1190	9	0	0
T14	41443	164	0	0
T15	23275	294	0	0
T16	763	6	0	0
T17	801	7	0	0
T18	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3582710	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3582710	0	0
T1	119127	709	0	0
T2	139004	1345	0	0
T3	339	2	0	0
T4	792529	1793	0	0
T12	896287	0	0	0
T13	1190	9	0	0
T14	41443	202	0	0
T15	23275	131	0	0
T16	763	6	0	0
T17	801	7	0	0
T18	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	1499592	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	1499592	0	0
T1	119127	2073	0	0
T2	139004	2476	0	0
T3	339	1	0	0
T4	792529	8895	0	0
T12	896287	0	0	0
T13	1190	7	0	0
T14	41443	214	0	0
T15	23275	339	0	0
T16	763	6	0	0
T17	801	6	0	0
T18	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302701540	3618249	0	0
DepthKnown_A	302701540	302589779	0	0
RvalidKnown_A	302701540	302589779	0	0
WreadyKnown_A	302701540	302589779	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	3618249	0	0
T1	119127	706	0	0
T2	139004	381	0	0
T3	339	1	0	0
T4	792529	3137	0	0
T12	896287	0	0	0
T13	1190	7	0	0
T14	41443	202	0	0
T15	23275	92	0	0
T16	763	6	0	0
T17	801	6	0	0
T18	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302701540	302589779	0	0
T1	119127	119111	0	0
T2	139004	138924	0	0
T3	339	325	0	0
T4	792529	792460	0	0
T12	896287	896238	0	0
T13	1190	1143	0	0
T14	41443	41379	0	0
T15	23275	23215	0	0
T16	763	687	0	0
T17	801	717	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0