Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1780735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

281118

1

T1

1027

T2

385

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	695623	1			T1	2500		T2	936		T3	40
values[0x0]	669523	1			T1	2539		T2	907		T3	38
values[0x1]	696707	1			T1	2562		T2	994		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1380917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

680936

1

T1

2498

T2

916

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9239	1			T1	25		T2	11		T3	1
valid_sources[0x01]	7011	1			T1	8		T2	7		T3	2
valid_sources[0x02]	7371	1			T1	38		T2	11		T4	8
valid_sources[0x03]	7680	1			T1	2		T2	7		T3	6
valid_sources[0x04]	7836	1			T1	23		T2	11		T4	8
valid_sources[0x05]	8226	1			T1	68		T2	23		T4	7
valid_sources[0x06]	9111	1			T1	13		T2	11		T4	7
valid_sources[0x07]	8132	1			T1	35		T2	9		T4	7
valid_sources[0x08]	7801	1			T1	10		T2	29		T4	2
valid_sources[0x09]	8486	1			T1	156		T2	20		T3	3
valid_sources[0x0a]	7507	1			T1	28		T2	13		T3	2
valid_sources[0x0b]	8284	1			T1	4		T2	7		T3	2
valid_sources[0x0c]	9243	1			T1	55		T2	6		T3	1
valid_sources[0x0d]	7439	1			T1	58		T2	14		T4	9
valid_sources[0x0e]	8511	1			T1	32		T2	8		T3	2
valid_sources[0x0f]	7619	1			T1	51		T2	3		T4	10
valid_sources[0x10]	7721	1			T1	48		T2	10		T4	18
valid_sources[0x11]	8686	1			T1	25		T2	9		T4	4
valid_sources[0x12]	8106	1			T1	13		T2	8		T3	3
valid_sources[0x13]	8397	1			T1	48		T2	10		T4	4
valid_sources[0x14]	7958	1			T1	21		T2	12		T4	13
valid_sources[0x15]	7882	1			T1	49		T2	8		T4	12
valid_sources[0x16]	8642	1			T1	82		T2	11		T4	8
valid_sources[0x17]	7871	1			T1	56		T2	12		T4	10
valid_sources[0x18]	7327	1			T1	16		T2	8		T4	9
valid_sources[0x19]	8146	1			T1	3		T2	6		T4	4
valid_sources[0x1a]	7448	1			T1	23		T2	13		T4	7
valid_sources[0x1b]	7926	1			T2	4		T3	1		T4	10
valid_sources[0x1c]	8191	1			T1	10		T2	4		T4	10
valid_sources[0x1d]	7610	1			T1	26		T2	10		T4	16
valid_sources[0x1e]	7743	1			T1	34		T2	9		T4	12
valid_sources[0x1f]	7817	1			T1	52		T2	5		T4	7
valid_sources[0x20]	7792	1			T1	15		T2	6		T4	6
valid_sources[0x21]	8212	1			T1	3		T2	9		T3	1
valid_sources[0x22]	8011	1			T1	2		T2	6		T4	9
valid_sources[0x23]	8026	1			T1	1		T2	6		T4	12
valid_sources[0x24]	7845	1			T1	39		T2	15		T4	7
valid_sources[0x25]	8117	1			T1	14		T2	12		T4	3
valid_sources[0x26]	7722	1			T1	33		T2	8		T4	6
valid_sources[0x27]	7424	1			T1	105		T2	16		T4	7
valid_sources[0x28]	8068	1			T1	91		T2	10		T4	5
valid_sources[0x29]	8367	1			T1	5		T2	17		T4	6
valid_sources[0x2a]	7916	1			T1	26		T2	19		T4	6
valid_sources[0x2b]	7987	1			T1	13		T2	9		T4	10
valid_sources[0x2c]	9017	1			T1	30		T2	7		T3	2
valid_sources[0x2d]	8145	1			T1	31		T2	3		T4	15
valid_sources[0x2e]	8208	1			T1	33		T2	12		T3	2
valid_sources[0x2f]	8872	1			T1	37		T2	9		T4	10
valid_sources[0x30]	7268	1			T1	1		T2	20		T4	9
valid_sources[0x31]	8214	1			T1	54		T2	19		T3	1
valid_sources[0x32]	7856	1			T1	50		T2	5		T4	9
valid_sources[0x33]	9308	1			T1	87		T2	18		T4	7
valid_sources[0x34]	7879	1			T1	20		T2	15		T4	3
valid_sources[0x35]	8232	1			T1	5		T2	8		T3	3
valid_sources[0x36]	7657	1			T1	32		T2	20		T3	1
valid_sources[0x37]	8647	1			T1	19		T2	12		T3	1
valid_sources[0x38]	8184	1			T1	28		T2	4		T4	3
valid_sources[0x39]	8325	1			T1	11		T2	7		T4	3
valid_sources[0x3a]	9782	1			T1	8		T2	2		T4	5
valid_sources[0x3b]	8066	1			T1	17		T2	22		T4	4
valid_sources[0x3c]	7461	1			T1	55		T2	27		T4	3
valid_sources[0x3d]	7811	1			T1	198		T2	10		T4	5
valid_sources[0x3e]	7904	1			T1	2		T2	6		T4	11
valid_sources[0x3f]	8577	1			T1	9		T2	10		T4	10
valid_sources[0x40]	7424	1			T1	46		T2	3		T4	7
valid_sources[0x41]	7620	1			T1	38		T2	7		T4	6
valid_sources[0x42]	7749	1			T1	37		T2	4		T4	9
valid_sources[0x43]	7871	1			T1	11		T2	5		T4	5
valid_sources[0x44]	7910	1			T1	33		T2	18		T4	13
valid_sources[0x45]	7674	1			T1	23		T2	11		T4	7
valid_sources[0x46]	9722	1			T1	5		T2	3		T3	2
valid_sources[0x47]	8121	1			T1	25		T2	7		T4	3
valid_sources[0x48]	9004	1			T1	64		T2	6		T4	7
valid_sources[0x49]	7893	1			T1	29		T2	10		T4	11
valid_sources[0x4a]	7918	1			T1	32		T2	18		T4	10
valid_sources[0x4b]	9454	1			T1	19		T2	5		T4	2
valid_sources[0x4c]	7835	1			T1	46		T2	11		T3	2
valid_sources[0x4d]	8036	1			T1	67		T2	12		T3	2
valid_sources[0x4e]	8096	1			T1	1		T2	4		T4	13
valid_sources[0x4f]	8262	1			T1	19		T2	7		T3	2
valid_sources[0x50]	8243	1			T1	98		T2	28		T4	7
valid_sources[0x51]	7594	1			T1	10		T2	15		T4	3
valid_sources[0x52]	9772	1			T1	86		T2	27		T4	7
valid_sources[0x53]	7748	1			T1	32		T2	1		T4	7
valid_sources[0x54]	7359	1			T1	11		T2	6		T4	14
valid_sources[0x55]	7686	1			T1	2		T2	3		T4	7
valid_sources[0x56]	8472	1			T1	9		T2	11		T4	9
valid_sources[0x57]	8276	1			T1	7		T2	16		T4	13
valid_sources[0x58]	8111	1			T1	32		T2	11		T3	4
valid_sources[0x59]	7802	1			T1	26		T2	9		T4	10
valid_sources[0x5a]	7695	1			T1	40		T2	19		T4	14
valid_sources[0x5b]	7576	1			T1	55		T2	4		T4	8
valid_sources[0x5c]	8330	1			T1	27		T2	7		T4	3
valid_sources[0x5d]	7992	1			T1	22		T2	16		T4	10
valid_sources[0x5e]	7959	1			T2	14		T3	1		T4	7
valid_sources[0x5f]	8287	1			T1	62		T2	20		T4	12
valid_sources[0x60]	7125	1			T1	3		T2	4		T3	2
valid_sources[0x61]	8760	1			T1	27		T2	12		T4	14
valid_sources[0x62]	7890	1			T1	41		T2	3		T3	3
valid_sources[0x63]	7809	1			T1	18		T2	8		T4	1
valid_sources[0x64]	8551	1			T1	34		T2	3		T4	12
valid_sources[0x65]	8598	1			T1	57		T2	13		T4	6
valid_sources[0x66]	7703	1			T1	9		T2	8		T4	8
valid_sources[0x67]	8681	1			T1	33		T2	11		T3	1
valid_sources[0x68]	9623	1			T1	24		T2	10		T4	7
valid_sources[0x69]	7785	1			T1	30		T2	9		T3	1
valid_sources[0x6a]	7565	1			T1	26		T2	10		T4	9
valid_sources[0x6b]	8030	1			T1	16		T2	24		T4	7
valid_sources[0x6c]	7370	1			T2	13		T3	1		T4	16
valid_sources[0x6d]	7858	1			T1	24		T2	9		T4	4
valid_sources[0x6e]	8186	1			T1	43		T2	6		T4	13
valid_sources[0x6f]	8328	1			T1	7		T2	18		T3	3
valid_sources[0x70]	8684	1			T1	34		T2	10		T4	6
valid_sources[0x71]	7982	1			T1	13		T2	15		T4	4
valid_sources[0x72]	8167	1			T1	62		T2	11		T4	9
valid_sources[0x73]	7669	1			T1	15		T2	13		T3	3
valid_sources[0x74]	8629	1			T1	3		T2	17		T4	6
valid_sources[0x75]	7592	1			T1	17		T2	13		T3	1
valid_sources[0x76]	7489	1			T1	1		T2	8		T4	11
valid_sources[0x77]	8730	1			T1	65		T2	14		T4	4
valid_sources[0x78]	8355	1			T1	21		T2	11		T4	10
valid_sources[0x79]	8043	1			T1	48		T2	23		T4	12
valid_sources[0x7a]	7995	1			T1	31		T2	7		T4	4
valid_sources[0x7b]	9165	1			T1	8		T2	5		T4	4
valid_sources[0x7c]	8446	1			T1	15		T2	27		T4	5
valid_sources[0x7d]	8616	1			T1	15		T2	15		T4	8
valid_sources[0x7e]	7073	1			T1	19		T2	2		T4	3
valid_sources[0x7f]	7651	1			T1	39		T2	25		T4	4
valid_sources[0x80]	7974	1			T1	1		T2	6		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29302

1

T1

101

T2

34

T3

4

values[0x0]

all_enables

biggest_size

222275

1

T1

818

T2

307

T3

13

values[0x1]

all_enables

biggest_size

29541

1

T1

108

T2

44

T3

1