Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	379199048	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	379199048	0	0
T1	9247560	191455	0	0
T2	317800	13912	0	0
T3	36176	566	0	0
T4	1978592	28751	0	0
T5	1649592	34208	0	0
T11	11009208	186267	0	0
T12	42672	774	0	0
T14	2126152	54696	0	0
T15	274008	10059	0	0
T16	162344	9816	0	0
T17	0	21784	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9247560	9241960	0	0
T2	317800	315672	0	0
T3	36176	32872	0	0
T4	1978592	1977024	0	0
T5	1649592	1648080	0	0
T11	11009208	11006800	0	0
T12	42672	39032	0	0
T14	2126152	2123800	0	0
T15	274008	271936	0	0
T16	162344	158704	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9247560	9241960	0	0
T2	317800	315672	0	0
T3	36176	32872	0	0
T4	1978592	1977024	0	0
T5	1649592	1648080	0	0
T11	11009208	11006800	0	0
T12	42672	39032	0	0
T14	2126152	2123800	0	0
T15	274008	271936	0	0
T16	162344	158704	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9247560	9241960	0	0
T2	317800	315672	0	0
T3	36176	32872	0	0
T4	1978592	1977024	0	0
T5	1649592	1648080	0	0
T11	11009208	11006800	0	0
T12	42672	39032	0	0
T14	2126152	2123800	0	0
T15	274008	271936	0	0
T16	162344	158704	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	135388176	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	135388176	0	0
T1	165135	81861	0	0
T2	5675	5407	0	0
T3	646	221	0	0
T4	35332	13446	0	0
T5	29457	13092	0	0
T11	196593	82259	0	0
T12	762	300	0	0
T14	37967	23330	0	0
T15	4893	4611	0	0
T16	2899	2454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	99875984	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	99875984	0	0
T1	165135	25219	0	0
T2	5675	2837	0	0
T3	646	115	0	0
T4	35332	4254	0	0
T5	29457	11033	0	0
T11	196593	22360	0	0
T12	762	158	0	0
T14	37967	10565	0	0
T15	4893	2704	0	0
T16	2899	2454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1647061	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1647061	0	0
T1	165135	1372	0	0
T2	5675	109	0	0
T3	646	3	0	0
T4	35332	323	0	0
T5	29457	204	0	0
T11	196593	1634	0	0
T12	762	2	0	0
T14	37967	319	0	0
T15	4893	39	0	0
T16	2899	0	0	0
T17	0	895	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	2939310	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	2939310	0	0
T1	165135	645	0	0
T2	5675	109	0	0
T3	646	3	0	0
T4	35332	109	0	0
T5	29457	176	0	0
T11	196593	2052	0	0
T12	762	2	0	0
T14	37967	397	0	0
T15	4893	39	0	0
T16	2899	0	0	0
T17	0	318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1646675	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1646675	0	0
T1	165135	1704	0	0
T2	5675	92	0	0
T3	646	5	0	0
T4	35332	273	0	0
T5	29457	124	0	0
T11	196593	6155	0	0
T12	762	7	0	0
T14	37967	312	0	0
T15	4893	55	0	0
T16	2899	0	0	0
T17	0	769	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3605131	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3605131	0	0
T1	165135	703	0	0
T2	5675	92	0	0
T3	646	5	0	0
T4	35332	128	0	0
T5	29457	163	0	0
T11	196593	1977	0	0
T12	762	7	0	0
T14	37967	268	0	0
T15	4893	55	0	0
T16	2899	0	0	0
T17	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1676047	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1676047	0	0
T1	165135	1453	0	0
T2	5675	110	0	0
T3	646	4	0	0
T4	35332	246	0	0
T5	29457	236	0	0
T11	196593	1503	0	0
T12	762	9	0	0
T14	37967	406	0	0
T15	4893	50	0	0
T16	2899	0	0	0
T17	0	656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3602346	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3602346	0	0
T1	165135	624	0	0
T2	5675	110	0	0
T3	646	4	0	0
T4	35332	120	0	0
T5	29457	309	0	0
T11	196593	1132	0	0
T12	762	9	0	0
T14	37967	394	0	0
T15	4893	50	0	0
T16	2899	0	0	0
T17	0	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1684819	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1684819	0	0
T1	165135	5278	0	0
T2	5675	102	0	0
T3	646	3	0	0
T4	35332	176	0	0
T5	29457	209	0	0
T11	196593	1172	0	0
T12	762	2	0	0
T14	37967	369	0	0
T15	4893	57	0	0
T16	2899	0	0	0
T17	0	735	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3841688	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3841688	0	0
T1	165135	2400	0	0
T2	5675	102	0	0
T3	646	3	0	0
T4	35332	105	0	0
T5	29457	207	0	0
T11	196593	389	0	0
T12	762	2	0	0
T14	37967	344	0	0
T15	4893	57	0	0
T16	2899	0	0	0
T17	0	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1657667	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1657667	0	0
T1	165135	3358	0	0
T2	5675	85	0	0
T3	646	8	0	0
T4	35332	268	0	0
T5	29457	249	0	0
T11	196593	3913	0	0
T12	762	2	0	0
T14	37967	331	0	0
T15	4893	49	0	0
T16	2899	248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3728329	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3728329	0	0
T1	165135	1461	0	0
T2	5675	85	0	0
T3	646	8	0	0
T4	35332	103	0	0
T5	29457	162	0	0
T11	196593	1766	0	0
T12	762	2	0	0
T14	37967	373	0	0
T15	4893	49	0	0
T16	2899	248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1693177	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1693177	0	0
T1	165135	1360	0	0
T2	5675	117	0	0
T3	646	3	0	0
T4	35332	254	0	0
T5	29457	236	0	0
T11	196593	2591	0	0
T12	762	5	0	0
T14	37967	366	0	0
T15	4893	54	0	0
T16	2899	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3581885	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3581885	0	0
T1	165135	541	0	0
T2	5675	117	0	0
T3	646	3	0	0
T4	35332	111	0	0
T5	29457	239	0	0
T11	196593	382	0	0
T12	762	5	0	0
T14	37967	487	0	0
T15	4893	54	0	0
T16	2899	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1682686	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1682686	0	0
T1	165135	1428	0	0
T2	5675	97	0	0
T3	646	5	0	0
T4	35332	175	0	0
T5	29457	246	0	0
T11	196593	944	0	0
T12	762	9	0	0
T14	37967	354	0	0
T15	4893	68	0	0
T16	2899	0	0	0
T17	0	853	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3869430	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3869430	0	0
T1	165135	660	0	0
T2	5675	97	0	0
T3	646	5	0	0
T4	35332	79	0	0
T5	29457	212	0	0
T11	196593	1169	0	0
T12	762	9	0	0
T14	37967	339	0	0
T15	4893	68	0	0
T16	2899	0	0	0
T17	0	385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1743089	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1743089	0	0
T1	165135	3383	0	0
T2	5675	118	0	0
T3	646	5	0	0
T4	35332	278	0	0
T5	29457	102	0	0
T11	196593	1098	0	0
T12	762	8	0	0
T14	37967	325	0	0
T15	4893	39	0	0
T16	2899	221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3712613	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3712613	0	0
T1	165135	1433	0	0
T2	5675	118	0	0
T3	646	5	0	0
T4	35332	115	0	0
T5	29457	101	0	0
T11	196593	670	0	0
T12	762	8	0	0
T14	37967	368	0	0
T15	4893	39	0	0
T16	2899	221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1656137	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1656137	0	0
T1	165135	1332	0	0
T2	5675	99	0	0
T3	646	9	0	0
T4	35332	392	0	0
T5	29457	284	0	0
T11	196593	1295	0	0
T12	762	7	0	0
T14	37967	398	0	0
T15	4893	51	0	0
T16	2899	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	4177013	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	4177013	0	0
T1	165135	490	0	0
T2	5675	99	0	0
T3	646	9	0	0
T4	35332	166	0	0
T5	29457	305	0	0
T11	196593	26	0	0
T12	762	7	0	0
T14	37967	506	0	0
T15	4893	51	0	0
T16	2899	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1698095	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1698095	0	0
T1	165135	2806	0	0
T2	5675	103	0	0
T3	646	3	0	0
T4	35332	320	0	0
T5	29457	163	0	0
T11	196593	3724	0	0
T12	762	9	0	0
T14	37967	413	0	0
T15	4893	48	0	0
T16	2899	0	0	0
T17	0	895	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3834022	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3834022	0	0
T1	165135	1522	0	0
T2	5675	103	0	0
T3	646	3	0	0
T4	35332	115	0	0
T5	29457	161	0	0
T11	196593	756	0	0
T12	762	9	0	0
T14	37967	386	0	0
T15	4893	48	0	0
T16	2899	0	0	0
T17	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1616600	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1616600	0	0
T1	165135	1465	0	0
T2	5675	119	0	0
T3	646	2	0	0
T4	35332	262	0	0
T5	29457	159	0	0
T11	196593	1913	0	0
T12	762	7	0	0
T14	37967	309	0	0
T15	4893	54	0	0
T16	2899	0	0	0
T17	0	1021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3605478	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3605478	0	0
T1	165135	515	0	0
T2	5675	119	0	0
T3	646	2	0	0
T4	35332	124	0	0
T5	29457	156	0	0
T11	196593	1182	0	0
T12	762	7	0	0
T14	37967	309	0	0
T15	4893	54	0	0
T16	2899	0	0	0
T17	0	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1674567	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1674567	0	0
T1	165135	3462	0	0
T2	5675	99	0	0
T3	646	2	0	0
T4	35332	276	0	0
T5	29457	182	0	0
T11	196593	3671	0	0
T12	762	10	0	0
T14	37967	546	0	0
T15	4893	53	0	0
T16	2899	251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	4709093	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	4709093	0	0
T1	165135	1379	0	0
T2	5675	99	0	0
T3	646	2	0	0
T4	35332	102	0	0
T5	29457	129	0	0
T11	196593	1491	0	0
T12	762	10	0	0
T14	37967	499	0	0
T15	4893	53	0	0
T16	2899	251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1629502	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1629502	0	0
T1	165135	1486	0	0
T2	5675	94	0	0
T3	646	3	0	0
T4	35332	183	0	0
T5	29457	260	0	0
T11	196593	1269	0	0
T12	762	10	0	0
T14	37967	303	0	0
T15	4893	52	0	0
T16	2899	0	0	0
T17	0	911	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3820660	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3820660	0	0
T1	165135	584	0	0
T2	5675	94	0	0
T3	646	3	0	0
T4	35332	81	0	0
T5	29457	200	0	0
T11	196593	340	0	0
T12	762	10	0	0
T14	37967	352	0	0
T15	4893	52	0	0
T16	2899	0	0	0
T17	0	395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1625135	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1625135	0	0
T1	165135	3617	0	0
T2	5675	102	0	0
T3	646	4	0	0
T4	35332	275	0	0
T5	29457	56	0	0
T11	196593	3694	0	0
T12	762	8	0	0
T14	37967	416	0	0
T15	4893	61	0	0
T16	2899	0	0	0
T17	0	810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3025444	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3025444	0	0
T1	165135	1646	0	0
T2	5675	102	0	0
T3	646	4	0	0
T4	35332	83	0	0
T5	29457	87	0	0
T11	196593	501	0	0
T12	762	8	0	0
T14	37967	420	0	0
T15	4893	61	0	0
T16	2899	0	0	0
T17	0	354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1630194	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1630194	0	0
T1	165135	1178	0	0
T2	5675	110	0	0
T3	646	3	0	0
T4	35332	386	0	0
T5	29457	128	0	0
T11	196593	1567	0	0
T12	762	3	0	0
T14	37967	319	0	0
T15	4893	53	0	0
T16	2899	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3493013	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3493013	0	0
T1	165135	567	0	0
T2	5675	110	0	0
T3	646	3	0	0
T4	35332	178	0	0
T5	29457	205	0	0
T11	196593	943	0	0
T12	762	3	0	0
T14	37967	338	0	0
T15	4893	53	0	0
T16	2899	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1636461	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1636461	0	0
T1	165135	3453	0	0
T2	5675	112	0	0
T3	646	1	0	0
T4	35332	215	0	0
T5	29457	175	0	0
T11	196593	2611	0	0
T12	762	5	0	0
T14	37967	386	0	0
T15	4893	39	0	0
T16	2899	0	0	0
T17	0	886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3431604	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3431604	0	0
T1	165135	1388	0	0
T2	5675	112	0	0
T3	646	1	0	0
T4	35332	70	0	0
T5	29457	184	0	0
T11	196593	951	0	0
T12	762	5	0	0
T14	37967	347	0	0
T15	4893	39	0	0
T16	2899	0	0	0
T17	0	329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1658594	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1658594	0	0
T1	165135	1623	0	0
T2	5675	108	0	0
T3	646	0	0	0
T4	35332	255	0	0
T5	29457	134	0	0
T11	196593	1076	0	0
T12	762	5	0	0
T14	37967	406	0	0
T15	4893	48	0	0
T16	2899	270	0	0
T17	0	767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3330579	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3330579	0	0
T1	165135	691	0	0
T2	5675	108	0	0
T3	646	0	0	0
T4	35332	113	0	0
T5	29457	142	0	0
T11	196593	388	0	0
T12	762	5	0	0
T14	37967	376	0	0
T15	4893	48	0	0
T16	2899	270	0	0
T17	0	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1649941	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1649941	0	0
T1	165135	1617	0	0
T2	5675	113	0	0
T3	646	1	0	0
T4	35332	306	0	0
T5	29457	229	0	0
T11	196593	2543	0	0
T12	762	2	0	0
T14	37967	418	0	0
T15	4893	43	0	0
T16	2899	247	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3471391	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3471391	0	0
T1	165135	567	0	0
T2	5675	113	0	0
T3	646	1	0	0
T4	35332	100	0	0
T5	29457	279	0	0
T11	196593	675	0	0
T12	762	2	0	0
T14	37967	373	0	0
T15	4893	43	0	0
T16	2899	247	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1695884	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1695884	0	0
T1	165135	1635	0	0
T2	5675	106	0	0
T3	646	5	0	0
T4	35332	308	0	0
T5	29457	247	0	0
T11	196593	1097	0	0
T12	762	5	0	0
T14	37967	530	0	0
T15	4893	49	0	0
T16	2899	0	0	0
T17	0	944	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3440066	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3440066	0	0
T1	165135	742	0	0
T2	5675	106	0	0
T3	646	5	0	0
T4	35332	133	0	0
T5	29457	148	0	0
T11	196593	346	0	0
T12	762	5	0	0
T14	37967	507	0	0
T15	4893	49	0	0
T16	2899	0	0	0
T17	0	400	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1668171	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1668171	0	0
T1	165135	1327	0	0
T2	5675	95	0	0
T3	646	2	0	0
T4	35332	340	0	0
T5	29457	108	0	0
T11	196593	1218	0	0
T12	762	5	0	0
T14	37967	287	0	0
T15	4893	48	0	0
T16	2899	237	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3472347	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3472347	0	0
T1	165135	595	0	0
T2	5675	95	0	0
T3	646	2	0	0
T4	35332	148	0	0
T5	29457	131	0	0
T11	196593	256	0	0
T12	762	5	0	0
T14	37967	332	0	0
T15	4893	48	0	0
T16	2899	237	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1682177	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1682177	0	0
T1	165135	3578	0	0
T2	5675	106	0	0
T3	646	5	0	0
T4	35332	200	0	0
T5	29457	177	0	0
T11	196593	2519	0	0
T12	762	5	0	0
T14	37967	454	0	0
T15	4893	45	0	0
T16	2899	0	0	0
T17	0	689	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3252246	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3252246	0	0
T1	165135	1372	0	0
T2	5675	106	0	0
T3	646	5	0	0
T4	35332	68	0	0
T5	29457	238	0	0
T11	196593	526	0	0
T12	762	5	0	0
T14	37967	465	0	0
T15	4893	45	0	0
T16	2899	0	0	0
T17	0	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1638937	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1638937	0	0
T1	165135	1555	0	0
T2	5675	118	0	0
T3	646	9	0	0
T4	35332	354	0	0
T5	29457	183	0	0
T11	196593	2385	0	0
T12	762	6	0	0
T14	37967	238	0	0
T15	4893	53	0	0
T16	2899	0	0	0
T17	0	756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	4268600	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	4268600	0	0
T1	165135	592	0	0
T2	5675	118	0	0
T3	646	9	0	0
T4	35332	157	0	0
T5	29457	160	0	0
T11	196593	1771	0	0
T12	762	6	0	0
T14	37967	309	0	0
T15	4893	53	0	0
T16	2899	0	0	0
T17	0	304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1696403	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1696403	0	0
T1	165135	1595	0	0
T2	5675	106	0	0
T3	646	9	0	0
T4	35332	321	0	0
T5	29457	215	0	0
T11	196593	2438	0	0
T12	762	4	0	0
T14	37967	439	0	0
T15	4893	48	0	0
T16	2899	0	0	0
T17	0	928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3642566	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3642566	0	0
T1	165135	661	0	0
T2	5675	106	0	0
T3	646	9	0	0
T4	35332	124	0	0
T5	29457	238	0	0
T11	196593	426	0	0
T12	762	4	0	0
T14	37967	318	0	0
T15	4893	48	0	0
T16	2899	0	0	0
T17	0	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1695869	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1695869	0	0
T1	165135	1533	0	0
T2	5675	94	0	0
T3	646	6	0	0
T4	35332	534	0	0
T5	29457	167	0	0
T11	196593	1154	0	0
T12	762	7	0	0
T14	37967	401	0	0
T15	4893	45	0	0
T16	2899	0	0	0
T17	0	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3621151	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3621151	0	0
T1	165135	598	0	0
T2	5675	94	0	0
T3	646	6	0	0
T4	35332	171	0	0
T5	29457	118	0	0
T11	196593	98	0	0
T12	762	7	0	0
T14	37967	377	0	0
T15	4893	45	0	0
T16	2899	0	0	0
T17	0	294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1623450	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1623450	0	0
T1	165135	1432	0	0
T2	5675	101	0	0
T3	646	2	0	0
T4	35332	302	0	0
T5	29457	198	0	0
T11	196593	1352	0	0
T12	762	5	0	0
T14	37967	373	0	0
T15	4893	55	0	0
T16	2899	0	0	0
T17	0	813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3868302	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3868302	0	0
T1	165135	598	0	0
T2	5675	101	0	0
T3	646	2	0	0
T4	35332	89	0	0
T5	29457	231	0	0
T11	196593	1119	0	0
T12	762	5	0	0
T14	37967	335	0	0
T15	4893	55	0	0
T16	2899	0	0	0
T17	0	332	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1656640	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1656640	0	0
T1	165135	1508	0	0
T2	5675	98	0	0
T3	646	10	0	0
T4	35332	262	0	0
T5	29457	217	0	0
T11	196593	2540	0	0
T12	762	4	0	0
T14	37967	420	0	0
T15	4893	41	0	0
T16	2899	0	0	0
T17	0	585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3966427	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3966427	0	0
T1	165135	571	0	0
T2	5675	98	0	0
T3	646	10	0	0
T4	35332	151	0	0
T5	29457	217	0	0
T11	196593	597	0	0
T12	762	4	0	0
T14	37967	573	0	0
T15	4893	41	0	0
T16	2899	0	0	0
T17	0	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	1665542	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	1665542	0	0
T1	165135	3689	0	0
T2	5675	121	0	0
T3	646	3	0	0
T4	35332	387	0	0
T5	29457	156	0	0
T11	196593	2212	0	0
T12	762	7	0	0
T14	37967	398	0	0
T15	4893	75	0	0
T16	2899	0	0	0
T17	0	771	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	346312081	3694634	0	0
DepthKnown_A	346312081	346195881	0	0
RvalidKnown_A	346312081	346195881	0	0
WreadyKnown_A	346312081	346195881	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	3694634	0	0
T1	165135	1603	0	0
T2	5675	121	0	0
T3	646	3	0	0
T4	35332	137	0	0
T5	29457	141	0	0
T11	196593	431	0	0
T12	762	7	0	0
T14	37967	473	0	0
T15	4893	75	0	0
T16	2899	0	0	0
T17	0	347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346312081	346195881	0	0
T1	165135	165035	0	0
T2	5675	5637	0	0
T3	646	587	0	0
T4	35332	35304	0	0
T5	29457	29430	0	0
T11	196593	196550	0	0
T12	762	697	0	0
T14	37967	37925	0	0
T15	4893	4856	0	0
T16	2899	2834	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0