Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1661549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261781

1

T1

217

T2

353

T3

299

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650067	1			T1	536		T2	825		T3	675
values[0x0]	622580	1			T1	501		T2	834		T3	730
values[0x1]	650683	1			T1	516		T2	824		T3	708

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1286566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

636764

1

T1

516

T2

830

T3

686

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8115	1			T1	7		T2	12		T3	7
valid_sources[0x01]	7881	1			T1	6		T3	5		T4	6
valid_sources[0x02]	7802	1			T1	6		T3	13		T14	4
valid_sources[0x03]	8124	1			T1	6		T2	29		T3	7
valid_sources[0x04]	7491	1			T1	7		T3	15		T4	4
valid_sources[0x05]	7143	1			T1	6		T2	2		T3	19
valid_sources[0x06]	6370	1			T1	5		T3	6		T4	2
valid_sources[0x07]	7307	1			T1	6		T2	44		T3	11
valid_sources[0x08]	7369	1			T1	7		T3	6		T4	2
valid_sources[0x09]	6813	1			T1	7		T3	3		T4	1
valid_sources[0x0a]	8370	1			T1	6		T3	5		T4	1
valid_sources[0x0b]	7671	1			T1	6		T3	12		T4	1
valid_sources[0x0c]	7050	1			T1	6		T3	3		T14	3
valid_sources[0x0d]	8024	1			T1	6		T3	8		T4	5
valid_sources[0x0e]	7315	1			T1	6		T3	9		T4	1
valid_sources[0x0f]	7375	1			T1	6		T3	9		T4	1
valid_sources[0x10]	6761	1			T1	6		T2	14		T3	13
valid_sources[0x11]	7144	1			T1	4		T3	6		T14	6
valid_sources[0x12]	6835	1			T1	6		T3	6		T4	3
valid_sources[0x13]	8730	1			T1	6		T2	9		T3	12
valid_sources[0x14]	8380	1			T1	6		T2	74		T3	16
valid_sources[0x15]	6962	1			T1	7		T3	20		T4	1
valid_sources[0x16]	7719	1			T1	6		T3	5		T14	19
valid_sources[0x17]	7524	1			T1	6		T3	1		T4	4
valid_sources[0x18]	7340	1			T1	6		T3	3		T4	2
valid_sources[0x19]	7126	1			T1	6		T3	10		T4	3
valid_sources[0x1a]	8527	1			T1	7		T3	17		T4	2
valid_sources[0x1b]	7829	1			T1	6		T3	7		T14	20
valid_sources[0x1c]	7362	1			T1	8		T3	7		T4	2
valid_sources[0x1d]	8852	1			T1	7		T3	6		T4	3
valid_sources[0x1e]	6688	1			T1	7		T3	4		T14	41
valid_sources[0x1f]	6456	1			T1	5		T2	25		T3	13
valid_sources[0x20]	7543	1			T1	6		T3	14		T4	1
valid_sources[0x21]	7229	1			T1	6		T3	4		T4	2
valid_sources[0x22]	7735	1			T1	6		T3	17		T14	5
valid_sources[0x23]	7219	1			T1	6		T3	5		T4	2
valid_sources[0x24]	8322	1			T1	5		T3	9		T4	1
valid_sources[0x25]	6851	1			T1	7		T3	8		T4	5
valid_sources[0x26]	7687	1			T1	6		T2	9		T3	14
valid_sources[0x27]	7289	1			T1	5		T3	9		T4	1
valid_sources[0x28]	8832	1			T1	6		T3	5		T14	27
valid_sources[0x29]	7084	1			T1	7		T3	13		T4	1
valid_sources[0x2a]	8933	1			T1	6		T3	6		T4	1
valid_sources[0x2b]	7495	1			T1	7		T2	28		T3	5
valid_sources[0x2c]	7639	1			T1	8		T2	81		T3	14
valid_sources[0x2d]	7369	1			T1	6		T3	9		T4	2
valid_sources[0x2e]	7193	1			T1	6		T3	9		T4	2
valid_sources[0x2f]	6750	1			T1	7		T2	7		T3	2
valid_sources[0x30]	7262	1			T1	6		T3	4		T14	2
valid_sources[0x31]	9134	1			T1	6		T3	6		T4	2
valid_sources[0x32]	9195	1			T1	6		T2	62		T3	4
valid_sources[0x33]	6783	1			T1	7		T3	2		T14	7
valid_sources[0x34]	7505	1			T1	5		T3	3		T14	14
valid_sources[0x35]	7464	1			T1	6		T2	44		T3	3
valid_sources[0x36]	8294	1			T1	7		T3	4		T14	4
valid_sources[0x37]	7390	1			T1	5		T3	8		T4	2
valid_sources[0x38]	8075	1			T1	5		T3	8		T4	2
valid_sources[0x39]	7263	1			T1	6		T3	17		T4	1
valid_sources[0x3a]	7288	1			T1	6		T2	25		T3	4
valid_sources[0x3b]	7500	1			T1	6		T2	39		T3	4
valid_sources[0x3c]	8541	1			T1	6		T3	11		T4	3
valid_sources[0x3d]	7206	1			T1	6		T3	1		T4	3
valid_sources[0x3e]	6879	1			T1	6		T3	14		T4	1
valid_sources[0x3f]	7271	1			T1	6		T3	18		T4	2
valid_sources[0x40]	7161	1			T1	6		T3	10		T14	9
valid_sources[0x41]	7311	1			T1	7		T3	5		T4	4
valid_sources[0x42]	7038	1			T1	7		T3	13		T4	1
valid_sources[0x43]	6913	1			T1	6		T3	6		T14	57
valid_sources[0x44]	7103	1			T1	6		T3	9		T15	20
valid_sources[0x45]	7766	1			T1	6		T2	6		T3	10
valid_sources[0x46]	6810	1			T1	7		T2	35		T3	5
valid_sources[0x47]	11052	1			T1	7		T3	5		T4	2
valid_sources[0x48]	7296	1			T1	6		T2	2		T3	8
valid_sources[0x49]	7827	1			T1	7		T3	3		T4	4
valid_sources[0x4a]	6931	1			T1	6		T3	8		T4	1
valid_sources[0x4b]	7075	1			T1	6		T3	15		T4	1
valid_sources[0x4c]	6908	1			T1	6		T3	12		T14	32
valid_sources[0x4d]	6829	1			T1	4		T3	9		T4	4
valid_sources[0x4e]	9608	1			T1	5		T3	11		T4	4
valid_sources[0x4f]	7319	1			T1	6		T3	9		T4	5
valid_sources[0x50]	7836	1			T1	6		T2	26		T3	3
valid_sources[0x51]	7789	1			T1	6		T2	87		T3	12
valid_sources[0x52]	6837	1			T1	5		T2	98		T3	7
valid_sources[0x53]	7129	1			T1	6		T3	5		T4	1
valid_sources[0x54]	7623	1			T1	6		T3	18		T4	1
valid_sources[0x55]	8190	1			T1	6		T2	6		T3	9
valid_sources[0x56]	6584	1			T1	4		T3	5		T4	1
valid_sources[0x57]	8081	1			T1	6		T2	137		T3	4
valid_sources[0x58]	6954	1			T1	7		T2	66		T3	16
valid_sources[0x59]	7222	1			T1	6		T3	1		T4	5
valid_sources[0x5a]	7312	1			T1	7		T3	5		T4	2
valid_sources[0x5b]	7475	1			T1	7		T3	7		T4	1
valid_sources[0x5c]	10468	1			T1	5		T2	21		T3	12
valid_sources[0x5d]	7829	1			T1	8		T2	5		T3	7
valid_sources[0x5e]	6609	1			T1	8		T3	6		T4	2
valid_sources[0x5f]	7331	1			T1	8		T2	9		T3	14
valid_sources[0x60]	7087	1			T1	6		T3	2		T14	4
valid_sources[0x61]	6563	1			T1	5		T3	9		T14	3
valid_sources[0x62]	7255	1			T1	6		T3	5		T4	5
valid_sources[0x63]	7400	1			T1	7		T2	13		T3	4
valid_sources[0x64]	8077	1			T1	6		T3	5		T4	3
valid_sources[0x65]	7278	1			T1	6		T2	18		T3	12
valid_sources[0x66]	8383	1			T1	7		T2	71		T3	6
valid_sources[0x67]	7066	1			T1	5		T3	7		T4	1
valid_sources[0x68]	7915	1			T1	5		T3	7		T4	5
valid_sources[0x69]	7071	1			T1	7		T3	3		T4	3
valid_sources[0x6a]	6685	1			T1	6		T3	10		T14	58
valid_sources[0x6b]	8851	1			T1	5		T3	13		T4	3
valid_sources[0x6c]	7075	1			T1	5		T2	33		T3	21
valid_sources[0x6d]	7217	1			T1	6		T2	42		T3	2
valid_sources[0x6e]	7370	1			T1	7		T3	3		T4	1
valid_sources[0x6f]	7582	1			T1	6		T3	11		T4	1
valid_sources[0x70]	7360	1			T1	8		T3	7		T4	2
valid_sources[0x71]	7708	1			T1	6		T3	7		T14	13
valid_sources[0x72]	7589	1			T1	6		T3	15		T4	4
valid_sources[0x73]	7212	1			T1	6		T3	12		T14	8
valid_sources[0x74]	7638	1			T1	9		T2	38		T3	20
valid_sources[0x75]	8223	1			T1	6		T2	17		T3	4
valid_sources[0x76]	6953	1			T1	6		T3	14		T4	1
valid_sources[0x77]	8227	1			T1	5		T2	48		T3	4
valid_sources[0x78]	7932	1			T1	5		T3	2		T4	2
valid_sources[0x79]	8177	1			T1	7		T3	4		T4	6
valid_sources[0x7a]	8379	1			T1	6		T3	7		T14	8
valid_sources[0x7b]	7247	1			T1	6		T3	4		T14	4
valid_sources[0x7c]	6789	1			T1	5		T3	9		T4	2
valid_sources[0x7d]	7202	1			T1	5		T3	11		T4	7
valid_sources[0x7e]	8766	1			T1	6		T3	7		T14	39
valid_sources[0x7f]	7559	1			T1	6		T3	3		T4	1
valid_sources[0x80]	6349	1			T1	6		T3	17		T14	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27364

1

T1

29

T2

37

T3

23

values[0x0]

all_enables

biggest_size

206877

1

T1

170

T2

284

T3

239

values[0x1]

all_enables

biggest_size

27540

1

T1

18

T2

32

T3

37