Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	348229028	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348229028	0	0
T1	2159360	1212902	0	0
T2	282408	12183	0	0
T3	5980408	130733	0	0
T4	15288784	357236	0	0
T7	3554460	63683	0	0
T14	5973240	106018	0	0
T15	16785888	1784483	0	0
T16	1650768	27524	0	0
T17	226968	4088	0	0
T18	36711304	1180439	0	0
T19	742672	16119	0	0
T20	0	9378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8637440	8637048	0	0
T2	282408	280784	0	0
T3	5980408	5980296	0	0
T4	15288784	15266720	0	0
T14	5973240	5968984	0	0
T15	16785888	16785664	0	0
T16	1650768	1574552	0	0
T17	226968	226016	0	0
T18	36711304	36710408	0	0
T19	742672	738248	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8637440	8637048	0	0
T2	282408	280784	0	0
T3	5980408	5980296	0	0
T4	15288784	15266720	0	0
T14	5973240	5968984	0	0
T15	16785888	16785664	0	0
T16	1650768	1574552	0	0
T17	226968	226016	0	0
T18	36711304	36710408	0	0
T19	742672	738248	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8637440	8637048	0	0
T2	282408	280784	0	0
T3	5980408	5980296	0	0
T4	15288784	15266720	0	0
T14	5973240	5968984	0	0
T15	16785888	16785664	0	0
T16	1650768	1574552	0	0
T17	226968	226016	0	0
T18	36711304	36710408	0	0
T19	742672	738248	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	125914031	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	125914031	0	0
T1	154240	6981	0	0
T2	5043	4734	0	0
T3	106793	103725	0	0
T4	273014	108236	0	0
T14	106665	41392	0	0
T15	299748	147224	0	0
T16	29478	11586	0	0
T17	4053	1784	0	0
T18	655559	647093	0	0
T19	13262	6171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	91026989	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	91026989	0	0
T1	154240	599470	0	0
T2	5043	2483	0	0
T3	106793	8947	0	0
T4	273014	84501	0	0
T14	106665	17597	0	0
T15	299748	334719	0	0
T16	29478	3955	0	0
T17	4053	528	0	0
T18	655559	265097	0	0
T19	13262	5172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1478234	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1478234	0	0
T2	5043	78	0	0
T3	106793	383	0	0
T4	273014	824	0	0
T7	84630	939	0	0
T14	106665	857	0	0
T15	299748	30451	0	0
T16	29478	190	0	0
T17	4053	7	0	0
T18	655559	104	0	0
T19	13262	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3092050	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3092050	0	0
T2	5043	78	0	0
T3	106793	88	0	0
T4	273014	933	0	0
T7	84630	939	0	0
T14	106665	571	0	0
T15	299748	8999	0	0
T16	29478	90	0	0
T17	4053	0	0	0
T18	655559	7435	0	0
T19	13262	73	0	0
T20	0	9378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1498315	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1498315	0	0
T2	5043	71	0	0
T3	106793	336	0	0
T4	273014	7098	0	0
T7	84630	1396	0	0
T14	106665	812	0	0
T15	299748	31185	0	0
T16	29478	201	0	0
T17	4053	53	0	0
T18	655559	107	0	0
T19	13262	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	2776080	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	2776080	0	0
T2	5043	71	0	0
T3	106793	77	0	0
T4	273014	8101	0	0
T7	84630	1396	0	0
T14	106665	403	0	0
T15	299748	11373	0	0
T16	29478	134	0	0
T17	4053	21	0	0
T18	655559	9471	0	0
T19	13262	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1550903	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1550903	0	0
T2	5043	99	0	0
T3	106793	349	0	0
T4	273014	2243	0	0
T7	84630	1107	0	0
T14	106665	678	0	0
T15	299748	29753	0	0
T16	29478	535	0	0
T17	4053	60	0	0
T18	655559	132	0	0
T19	13262	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	2857674	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	2857674	0	0
T2	5043	99	0	0
T3	106793	1307	0	0
T4	273014	2327	0	0
T7	84630	1107	0	0
T14	106665	403	0	0
T15	299748	13010	0	0
T16	29478	222	0	0
T17	4053	25	0	0
T18	655559	11191	0	0
T19	13262	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1537857	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1537857	0	0
T2	5043	95	0	0
T3	106793	370	0	0
T4	273014	7592	0	0
T7	84630	1212	0	0
T14	106665	2757	0	0
T15	299748	39893	0	0
T16	29478	253	0	0
T17	4053	37	0	0
T18	655559	135	0	0
T19	13262	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3550429	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3550429	0	0
T2	5043	95	0	0
T3	106793	699	0	0
T4	273014	7499	0	0
T7	84630	1212	0	0
T14	106665	1372	0	0
T15	299748	11862	0	0
T16	29478	104	0	0
T17	4053	14	0	0
T18	655559	12388	0	0
T19	13262	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1537699	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1537699	0	0
T2	5043	93	0	0
T3	106793	287	0	0
T4	273014	831	0	0
T7	84630	1610	0	0
T14	106665	742	0	0
T15	299748	32771	0	0
T16	29478	470	0	0
T17	4053	73	0	0
T18	655559	135	0	0
T19	13262	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3028530	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3028530	0	0
T2	5043	93	0	0
T3	106793	70	0	0
T4	273014	776	0	0
T7	84630	1610	0	0
T14	106665	529	0	0
T15	299748	9442	0	0
T16	29478	230	0	0
T17	4053	26	0	0
T18	655559	9475	0	0
T19	13262	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1502755	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1502755	0	0
T2	5043	95	0	0
T3	106793	374	0	0
T4	273014	1001	0	0
T7	84630	973	0	0
T14	106665	737	0	0
T15	299748	31486	0	0
T16	29478	172	0	0
T17	4053	41	0	0
T18	655559	127	0	0
T19	13262	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	2753583	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	2753583	0	0
T2	5043	95	0	0
T3	106793	105	0	0
T4	273014	1114	0	0
T7	84630	973	0	0
T14	106665	398	0	0
T15	299748	10806	0	0
T16	29478	91	0	0
T17	4053	11	0	0
T18	655559	8327	0	0
T19	13262	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1537145	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1537145	0	0
T2	5043	92	0	0
T3	106793	382	0	0
T4	273014	2870	0	0
T7	84630	2067	0	0
T14	106665	799	0	0
T15	299748	37722	0	0
T16	29478	255	0	0
T17	4053	64	0	0
T18	655559	100	0	0
T19	13262	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3097972	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3097972	0	0
T2	5043	92	0	0
T3	106793	678	0	0
T4	273014	2754	0	0
T7	84630	2067	0	0
T14	106665	537	0	0
T15	299748	10781	0	0
T16	29478	107	0	0
T17	4053	16	0	0
T18	655559	9500	0	0
T19	13262	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1527383	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1527383	0	0
T2	5043	87	0	0
T3	106793	307	0	0
T4	273014	3077	0	0
T7	84630	1876	0	0
T14	106665	737	0	0
T15	299748	44293	0	0
T16	29478	212	0	0
T17	4053	87	0	0
T18	655559	150	0	0
T19	13262	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3249178	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3249178	0	0
T2	5043	87	0	0
T3	106793	82	0	0
T4	273014	2880	0	0
T7	84630	1876	0	0
T14	106665	424	0	0
T15	299748	14871	0	0
T16	29478	57	0	0
T17	4053	24	0	0
T18	655559	10258	0	0
T19	13262	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1533399	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1533399	0	0
T2	5043	92	0	0
T3	106793	349	0	0
T4	273014	3378	0	0
T7	84630	1478	0	0
T14	106665	923	0	0
T15	299748	36211	0	0
T16	29478	225	0	0
T17	4053	11	0	0
T18	655559	102	0	0
T19	13262	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3485839	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3485839	0	0
T2	5043	92	0	0
T3	106793	250	0	0
T4	273014	3309	0	0
T7	84630	1478	0	0
T14	106665	419	0	0
T15	299748	15514	0	0
T16	29478	98	0	0
T17	4053	2	0	0
T18	655559	7497	0	0
T19	13262	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1526107	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1526107	0	0
T1	154240	1005	0	0
T2	5043	74	0	0
T3	106793	333	0	0
T4	273014	4104	0	0
T14	106665	2798	0	0
T15	299748	36486	0	0
T16	29478	170	0	0
T17	4053	77	0	0
T18	655559	147	0	0
T19	13262	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3216303	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3216303	0	0
T1	154240	83866	0	0
T2	5043	74	0	0
T3	106793	88	0	0
T4	273014	5160	0	0
T14	106665	2254	0	0
T15	299748	11976	0	0
T16	29478	64	0	0
T17	4053	42	0	0
T18	655559	13811	0	0
T19	13262	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1534220	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1534220	0	0
T2	5043	116	0	0
T3	106793	318	0	0
T4	273014	3211	0	0
T7	84630	1242	0	0
T14	106665	902	0	0
T15	299748	30558	0	0
T16	29478	251	0	0
T17	4053	31	0	0
T18	655559	163	0	0
T19	13262	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3423777	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3423777	0	0
T2	5043	116	0	0
T3	106793	528	0	0
T4	273014	3436	0	0
T7	84630	1242	0	0
T14	106665	498	0	0
T15	299748	13942	0	0
T16	29478	130	0	0
T17	4053	4	0	0
T18	655559	17191	0	0
T19	13262	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1507721	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1507721	0	0
T2	5043	90	0	0
T3	106793	308	0	0
T4	273014	1235	0	0
T7	84630	917	0	0
T14	106665	838	0	0
T15	299748	34979	0	0
T16	29478	1526	0	0
T17	4053	60	0	0
T18	655559	142	0	0
T19	13262	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3501539	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3501539	0	0
T2	5043	90	0	0
T3	106793	537	0	0
T4	273014	1387	0	0
T7	84630	917	0	0
T14	106665	445	0	0
T15	299748	13408	0	0
T16	29478	648	0	0
T17	4053	38	0	0
T18	655559	12288	0	0
T19	13262	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1556097	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1556097	0	0
T2	5043	97	0	0
T3	106793	325	0	0
T4	273014	6048	0	0
T7	84630	1407	0	0
T14	106665	678	0	0
T15	299748	31761	0	0
T16	29478	190	0	0
T17	4053	28	0	0
T18	655559	104	0	0
T19	13262	125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	2689228	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	2689228	0	0
T2	5043	97	0	0
T3	106793	74	0	0
T4	273014	5732	0	0
T7	84630	1407	0	0
T14	106665	496	0	0
T15	299748	10963	0	0
T16	29478	91	0	0
T17	4053	22	0	0
T18	655559	8280	0	0
T19	13262	123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1505322	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1505322	0	0
T2	5043	99	0	0
T3	106793	404	0	0
T4	273014	3201	0	0
T7	84630	2090	0	0
T14	106665	590	0	0
T15	299748	38046	0	0
T16	29478	181	0	0
T17	4053	31	0	0
T18	655559	101	0	0
T19	13262	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3075982	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3075982	0	0
T2	5043	99	0	0
T3	106793	95	0	0
T4	273014	3103	0	0
T7	84630	2090	0	0
T14	106665	386	0	0
T15	299748	12188	0	0
T16	29478	122	0	0
T17	4053	34	0	0
T18	655559	8558	0	0
T19	13262	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1506413	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1506413	0	0
T2	5043	91	0	0
T3	106793	281	0	0
T4	273014	875	0	0
T7	84630	1744	0	0
T14	106665	644	0	0
T15	299748	34983	0	0
T16	29478	129	0	0
T17	4053	23	0	0
T18	655559	103	0	0
T19	13262	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3457131	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3457131	0	0
T2	5043	91	0	0
T3	106793	492	0	0
T4	273014	862	0	0
T7	84630	1743	0	0
T14	106665	506	0	0
T15	299748	14897	0	0
T16	29478	50	0	0
T17	4053	5	0	0
T18	655559	8420	0	0
T19	13262	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1523549	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1523549	0	0
T2	5043	137	0	0
T3	106793	321	0	0
T4	273014	902	0	0
T7	84630	1718	0	0
T14	106665	2431	0	0
T15	299748	37638	0	0
T16	29478	157	0	0
T17	4053	40	0	0
T18	655559	113	0	0
T19	13262	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3261187	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3261187	0	0
T2	5043	137	0	0
T3	106793	85	0	0
T4	273014	819	0	0
T7	84630	1718	0	0
T14	106665	1663	0	0
T15	299748	11206	0	0
T16	29478	78	0	0
T17	4053	10	0	0
T18	655559	10984	0	0
T19	13262	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1503577	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1503577	0	0
T2	5043	98	0	0
T3	106793	309	0	0
T4	273014	1169	0	0
T7	84630	1173	0	0
T14	106665	666	0	0
T15	299748	32428	0	0
T16	29478	243	0	0
T17	4053	31	0	0
T18	655559	119	0	0
T19	13262	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	2852626	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	2852626	0	0
T2	5043	98	0	0
T3	106793	73	0	0
T4	273014	1092	0	0
T7	84630	1173	0	0
T14	106665	454	0	0
T15	299748	9047	0	0
T16	29478	111	0	0
T17	4053	25	0	0
T18	655559	10699	0	0
T19	13262	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1562733	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1562733	0	0
T1	154240	1199	0	0
T2	5043	94	0	0
T3	106793	323	0	0
T4	273014	1138	0	0
T14	106665	666	0	0
T15	299748	41776	0	0
T16	29478	224	0	0
T17	4053	61	0	0
T18	655559	100	0	0
T19	13262	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	4153291	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	4153291	0	0
T1	154240	107741	0	0
T2	5043	94	0	0
T3	106793	75	0	0
T4	273014	1088	0	0
T14	106665	435	0	0
T15	299748	12168	0	0
T16	29478	137	0	0
T17	4053	13	0	0
T18	655559	8237	0	0
T19	13262	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1497259	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1497259	0	0
T2	5043	83	0	0
T3	106793	319	0	0
T4	273014	2904	0	0
T7	84630	1679	0	0
T14	106665	657	0	0
T15	299748	40236	0	0
T16	29478	450	0	0
T17	4053	51	0	0
T18	655559	104	0	0
T19	13262	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3570072	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3570072	0	0
T2	5043	83	0	0
T3	106793	154	0	0
T4	273014	2819	0	0
T7	84630	1679	0	0
T14	106665	463	0	0
T15	299748	15195	0	0
T16	29478	224	0	0
T17	4053	22	0	0
T18	655559	8903	0	0
T19	13262	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1535576	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1535576	0	0
T1	154240	1268	0	0
T2	5043	97	0	0
T3	106793	332	0	0
T4	273014	2923	0	0
T14	106665	788	0	0
T15	299748	35337	0	0
T16	29478	153	0	0
T17	4053	29	0	0
T18	655559	125	0	0
T19	13262	166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3089967	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3089967	0	0
T1	154240	110470	0	0
T2	5043	97	0	0
T3	106793	1996	0	0
T4	273014	3272	0	0
T14	106665	464	0	0
T15	299748	11480	0	0
T16	29478	92	0	0
T17	4053	11	0	0
T18	655559	8388	0	0
T19	13262	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1571150	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1571150	0	0
T2	5043	82	0	0
T3	106793	321	0	0
T4	273014	4909	0	0
T7	84630	1929	0	0
T14	106665	609	0	0
T15	299748	43570	0	0
T16	29478	330	0	0
T17	4053	28	0	0
T18	655559	173	0	0
T19	13262	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3638922	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3638922	0	0
T2	5043	82	0	0
T3	106793	89	0	0
T4	273014	5023	0	0
T7	84630	1927	0	0
T14	106665	353	0	0
T15	299748	13386	0	0
T16	29478	169	0	0
T17	4053	8	0	0
T18	655559	11755	0	0
T19	13262	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1507706	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1507706	0	0
T1	154240	1252	0	0
T2	5043	86	0	0
T3	106793	310	0	0
T4	273014	2662	0	0
T14	106665	654	0	0
T15	299748	41234	0	0
T16	29478	198	0	0
T17	4053	84	0	0
T18	655559	86	0	0
T19	13262	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	4589897	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	4589897	0	0
T1	154240	116915	0	0
T2	5043	86	0	0
T3	106793	77	0	0
T4	273014	3396	0	0
T14	106665	404	0	0
T15	299748	13514	0	0
T16	29478	68	0	0
T17	4053	12	0	0
T18	655559	6526	0	0
T19	13262	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1528004	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1528004	0	0
T2	5043	87	0	0
T3	106793	304	0	0
T4	273014	3097	0	0
T7	84630	2232	0	0
T14	106665	711	0	0
T15	299748	34151	0	0
T16	29478	535	0	0
T17	4053	42	0	0
T18	655559	142	0	0
T19	13262	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3607623	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3607623	0	0
T2	5043	87	0	0
T3	106793	79	0	0
T4	273014	3011	0	0
T7	84630	2230	0	0
T14	106665	472	0	0
T15	299748	13496	0	0
T16	29478	247	0	0
T17	4053	17	0	0
T18	655559	13445	0	0
T19	13262	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1509299	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1509299	0	0
T1	154240	978	0	0
T2	5043	86	0	0
T3	106793	373	0	0
T4	273014	2764	0	0
T14	106665	573	0	0
T15	299748	34317	0	0
T16	29478	192	0	0
T17	4053	64	0	0
T18	655559	83	0	0
T19	13262	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3696264	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3696264	0	0
T1	154240	78807	0	0
T2	5043	86	0	0
T3	106793	81	0	0
T4	273014	3212	0	0
T14	106665	396	0	0
T15	299748	15002	0	0
T16	29478	117	0	0
T17	4053	56	0	0
T18	655559	9246	0	0
T19	13262	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1518572	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1518572	0	0
T2	5043	85	0	0
T3	106793	345	0	0
T4	273014	3153	0	0
T7	84630	1190	0	0
T14	106665	764	0	0
T15	299748	36802	0	0
T16	29478	319	0	0
T17	4053	41	0	0
T18	655559	115	0	0
T19	13262	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3298273	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3298273	0	0
T2	5043	85	0	0
T3	106793	81	0	0
T4	273014	2862	0	0
T7	84630	1190	0	0
T14	106665	416	0	0
T15	299748	13387	0	0
T16	29478	177	0	0
T17	4053	23	0	0
T18	655559	7443	0	0
T19	13262	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1513979	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1513979	0	0
T2	5043	92	0	0
T3	106793	396	0	0
T4	273014	4635	0	0
T7	84630	1865	0	0
T14	106665	4632	0	0
T15	299748	36787	0	0
T16	29478	178	0	0
T17	4053	69	0	0
T18	655559	49	0	0
T19	13262	135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3260336	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3260336	0	0
T2	5043	92	0	0
T3	106793	904	0	0
T4	273014	4562	0	0
T7	84630	1865	0	0
T14	106665	1916	0	0
T15	299748	10760	0	0
T16	29478	115	0	0
T17	4053	24	0	0
T18	655559	5665	0	0
T19	13262	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	1534749	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	1534749	0	0
T1	154240	1279	0	0
T2	5043	87	0	0
T3	106793	356	0	0
T4	273014	2833	0	0
T14	106665	796	0	0
T15	299748	32967	0	0
T16	29478	175	0	0
T17	4053	25	0	0
T18	655559	91	0	0
T19	13262	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317995668	3868532	0	0
DepthKnown_A	317995668	317879907	0	0
RvalidKnown_A	317995668	317879907	0	0
WreadyKnown_A	317995668	317879907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	3868532	0	0
T1	154240	101671	0	0
T2	5043	87	0	0
T3	106793	82	0	0
T4	273014	3293	0	0
T14	106665	513	0	0
T15	299748	12046	0	0
T16	29478	96	0	0
T17	4053	23	0	0
T18	655559	9716	0	0
T19	13262	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317995668	317879907	0	0
T1	154240	154233	0	0
T2	5043	5014	0	0
T3	106793	106791	0	0
T4	273014	272620	0	0
T14	106665	106589	0	0
T15	299748	299744	0	0
T16	29478	28117	0	0
T17	4053	4036	0	0
T18	655559	655543	0	0
T19	13262	13183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0