Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1725737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

271452

1

T1

197

T2

136

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	674256	1			T1	432		T2	327		T3	78
values[0x0]	646170	1			T1	404		T2	330		T3	17
values[0x1]	676763	1			T1	448		T2	403		T3	86

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1338455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

658734

1

T1

440

T2

357

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7302	1			T1	2		T2	4		T11	9
valid_sources[0x01]	7281	1			T1	4		T2	4		T11	16
valid_sources[0x02]	7788	1			T1	3		T2	4		T11	8
valid_sources[0x03]	8041	1			T1	2		T2	2		T3	2
valid_sources[0x04]	8273	1			T1	7		T2	4		T11	5
valid_sources[0x05]	6994	1			T1	1		T2	1		T11	5
valid_sources[0x06]	8525	1			T1	4		T2	5		T3	1
valid_sources[0x07]	7933	1			T1	4		T2	3		T3	2
valid_sources[0x08]	7957	1			T1	2		T2	5		T3	1
valid_sources[0x09]	7521	1			T1	7		T2	4		T3	4
valid_sources[0x0a]	7099	1			T1	3		T2	3		T3	1
valid_sources[0x0b]	7648	1			T1	10		T2	5		T11	15
valid_sources[0x0c]	7273	1			T1	3		T2	6		T3	1
valid_sources[0x0d]	7293	1			T1	1		T2	5		T11	6
valid_sources[0x0e]	7064	1			T1	3		T2	4		T11	11
valid_sources[0x0f]	7754	1			T1	13		T2	8		T3	2
valid_sources[0x10]	7572	1			T1	5		T2	2		T3	6
valid_sources[0x11]	7713	1			T1	7		T2	7		T3	1
valid_sources[0x12]	6704	1			T1	1		T2	6		T3	1
valid_sources[0x13]	6947	1			T1	5		T2	7		T11	5
valid_sources[0x14]	7589	1			T2	5		T3	1		T11	5
valid_sources[0x15]	7108	1			T1	4		T2	2		T3	2
valid_sources[0x16]	8215	1			T1	18		T2	5		T11	8
valid_sources[0x17]	8990	1			T1	7		T2	6		T3	1
valid_sources[0x18]	7502	1			T1	3		T11	9		T12	2
valid_sources[0x19]	7177	1			T1	5		T2	2		T11	13
valid_sources[0x1a]	7292	1			T1	13		T2	1		T3	1
valid_sources[0x1b]	7919	1			T1	6		T2	3		T3	5
valid_sources[0x1c]	8209	1			T1	3		T2	2		T3	1
valid_sources[0x1d]	6802	1			T1	1		T2	3		T11	16
valid_sources[0x1e]	8662	1			T1	4		T2	1		T11	14
valid_sources[0x1f]	6775	1			T1	2		T2	2		T3	1
valid_sources[0x20]	7826	1			T1	8		T2	8		T3	1
valid_sources[0x21]	7227	1			T1	3		T2	3		T3	1
valid_sources[0x22]	8311	1			T1	10		T2	3		T3	2
valid_sources[0x23]	6776	1			T1	7		T2	1		T11	12
valid_sources[0x24]	7491	1			T1	8		T2	6		T11	14
valid_sources[0x25]	10341	1			T1	6		T2	4		T3	1
valid_sources[0x26]	7204	1			T1	9		T2	3		T11	7
valid_sources[0x27]	9165	1			T1	10		T2	4		T11	8
valid_sources[0x28]	7543	1			T1	1		T2	4		T3	1
valid_sources[0x29]	7690	1			T1	10		T3	1		T11	13
valid_sources[0x2a]	7829	1			T1	4		T11	16		T12	5
valid_sources[0x2b]	8687	1			T1	1		T2	2		T11	13
valid_sources[0x2c]	6760	1			T1	6		T2	3		T3	1
valid_sources[0x2d]	7813	1			T1	12		T2	6		T3	1
valid_sources[0x2e]	7791	1			T1	10		T2	8		T3	2
valid_sources[0x2f]	7266	1			T1	4		T2	4		T11	4
valid_sources[0x30]	8118	1			T1	6		T2	8		T11	14
valid_sources[0x31]	7819	1			T1	7		T3	2		T11	14
valid_sources[0x32]	7503	1			T1	2		T2	1		T3	1
valid_sources[0x33]	7879	1			T1	3		T2	4		T11	9
valid_sources[0x34]	6946	1			T1	2		T2	5		T11	8
valid_sources[0x35]	9038	1			T1	4		T2	6		T11	13
valid_sources[0x36]	7778	1			T1	4		T2	2		T11	16
valid_sources[0x37]	6939	1			T1	7		T2	4		T11	8
valid_sources[0x38]	8188	1			T1	3		T2	7		T11	9
valid_sources[0x39]	7523	1			T1	2		T2	2		T11	15
valid_sources[0x3a]	7532	1			T1	1		T2	3		T11	10
valid_sources[0x3b]	8079	1			T1	7		T2	3		T3	1
valid_sources[0x3c]	9392	1			T1	6		T2	1		T11	10
valid_sources[0x3d]	9215	1			T1	3		T2	3		T11	10
valid_sources[0x3e]	7537	1			T1	2		T2	4		T11	4
valid_sources[0x3f]	7449	1			T1	10		T2	2		T11	17
valid_sources[0x40]	8364	1			T1	4		T2	2		T11	15
valid_sources[0x41]	7403	1			T2	2		T3	1		T11	17
valid_sources[0x42]	6936	1			T1	5		T2	3		T11	12
valid_sources[0x43]	7120	1			T1	5		T2	2		T3	1
valid_sources[0x44]	7413	1			T1	8		T2	3		T11	28
valid_sources[0x45]	7773	1			T1	8		T2	1		T3	1
valid_sources[0x46]	7595	1			T1	1		T2	3		T11	11
valid_sources[0x47]	7666	1			T1	2		T2	6		T11	11
valid_sources[0x48]	8265	1			T1	7		T2	6		T11	6
valid_sources[0x49]	8326	1			T1	12		T2	3		T11	10
valid_sources[0x4a]	7491	1			T1	2		T2	3		T3	1
valid_sources[0x4b]	7456	1			T1	4		T2	7		T11	15
valid_sources[0x4c]	8554	1			T1	7		T2	2		T11	6
valid_sources[0x4d]	9212	1			T1	4		T2	4		T3	1
valid_sources[0x4e]	7769	1			T1	6		T2	6		T11	16
valid_sources[0x4f]	7459	1			T1	1		T2	6		T11	6
valid_sources[0x50]	7796	1			T1	3		T2	5		T11	9
valid_sources[0x51]	8882	1			T1	8		T2	5		T3	1
valid_sources[0x52]	7774	1			T1	8		T2	2		T11	5
valid_sources[0x53]	8653	1			T1	6		T2	5		T11	12
valid_sources[0x54]	7676	1			T1	2		T2	4		T11	8
valid_sources[0x55]	6980	1			T1	5		T2	3		T11	14
valid_sources[0x56]	8443	1			T1	4		T2	4		T3	1
valid_sources[0x57]	7776	1			T1	6		T2	6		T3	1
valid_sources[0x58]	7134	1			T1	1		T2	5		T11	6
valid_sources[0x59]	8116	1			T1	8		T2	2		T11	16
valid_sources[0x5a]	8249	1			T1	6		T2	4		T11	10
valid_sources[0x5b]	8305	1			T1	10		T2	3		T3	1
valid_sources[0x5c]	7761	1			T1	6		T2	9		T11	3
valid_sources[0x5d]	7602	1			T1	1		T2	5		T11	9
valid_sources[0x5e]	8456	1			T1	10		T2	2		T3	2
valid_sources[0x5f]	7834	1			T1	4		T2	2		T3	1
valid_sources[0x60]	7538	1			T1	2		T2	4		T3	3
valid_sources[0x61]	8311	1			T1	7		T2	8		T11	15
valid_sources[0x62]	7910	1			T1	6		T2	4		T11	6
valid_sources[0x63]	8282	1			T1	7		T2	3		T3	4
valid_sources[0x64]	7700	1			T1	12		T2	3		T3	2
valid_sources[0x65]	7155	1			T1	3		T2	7		T11	7
valid_sources[0x66]	9676	1			T1	4		T2	5		T11	13
valid_sources[0x67]	9838	1			T1	2		T2	4		T3	1
valid_sources[0x68]	8320	1			T1	8		T2	7		T11	14
valid_sources[0x69]	7462	1			T1	7		T2	4		T3	1
valid_sources[0x6a]	7950	1			T1	5		T2	3		T11	9
valid_sources[0x6b]	7824	1			T1	1		T2	3		T3	1
valid_sources[0x6c]	7018	1			T1	1		T2	5		T11	8
valid_sources[0x6d]	6695	1			T1	1		T2	6		T11	18
valid_sources[0x6e]	7554	1			T1	4		T2	5		T11	7
valid_sources[0x6f]	7451	1			T1	5		T2	4		T3	2
valid_sources[0x70]	7259	1			T1	2		T2	7		T3	1
valid_sources[0x71]	6590	1			T1	8		T11	8		T12	3
valid_sources[0x72]	7892	1			T1	13		T2	3		T11	4
valid_sources[0x73]	7548	1			T1	1		T2	3		T11	14
valid_sources[0x74]	7274	1			T1	7		T2	2		T3	2
valid_sources[0x75]	6487	1			T1	2		T2	5		T3	1
valid_sources[0x76]	6710	1			T1	9		T2	5		T11	5
valid_sources[0x77]	7436	1			T1	5		T2	4		T11	12
valid_sources[0x78]	8360	1			T1	3		T2	3		T11	13
valid_sources[0x79]	7253	1			T1	7		T2	4		T11	12
valid_sources[0x7a]	7506	1			T1	3		T2	3		T11	11
valid_sources[0x7b]	8853	1			T1	3		T2	1		T3	1
valid_sources[0x7c]	7796	1			T1	6		T2	4		T3	3
valid_sources[0x7d]	7295	1			T1	1		T2	5		T3	1
valid_sources[0x7e]	7324	1			T1	4		T2	6		T11	6
valid_sources[0x7f]	7797	1			T1	14		T2	4		T11	6
valid_sources[0x80]	8372	1			T1	2		T2	2		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28611

1

T1

25

T2

12

T3

8

values[0x0]

all_enables

biggest_size

214115

1

T1

150

T2

111

T3

3

values[0x1]

all_enables

biggest_size

28726

1

T1

22

T2

13

T3

7