Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	330095991	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	330095991	0	0
T1	7385056	1371536	0	0
T2	123032	5196	0	0
T3	6214880	136324	0	0
T11	11903192	1711947	0	0
T12	27004656	566482	0	0
T13	117992	3950	0	0
T14	3812816	67252	0	0
T15	46256	916	0	0
T16	6085968	199461	0	0
T17	1490104	61961	0	0
T18	0	33259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7385056	7384832	0	0
T2	123032	121576	0	0
T3	6214880	6210064	0	0
T11	11903192	11902968	0	0
T12	27004656	26996648	0	0
T13	117992	116144	0	0
T14	3812816	3810520	0	0
T15	46256	42616	0	0
T16	6085968	6085184	0	0
T17	1490104	1424808	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7385056	7384832	0	0
T2	123032	121576	0	0
T3	6214880	6210064	0	0
T11	11903192	11902968	0	0
T12	27004656	26996648	0	0
T13	117992	116144	0	0
T14	3812816	3810520	0	0
T15	46256	42616	0	0
T16	6085968	6085184	0	0
T17	1490104	1424808	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7385056	7384832	0	0
T2	123032	121576	0	0
T3	6214880	6210064	0	0
T11	11903192	11902968	0	0
T12	27004656	26996648	0	0
T13	117992	116144	0	0
T14	3812816	3810520	0	0
T15	46256	42616	0	0
T16	6085968	6085184	0	0
T17	1490104	1424808	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	119229184	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	119229184	0	0
T1	131876	616619	0	0
T2	2197	2018	0	0
T3	110980	57818	0	0
T11	212557	209480	0	0
T12	482226	242815	0	0
T13	2107	1801	0	0
T14	68086	66347	0	0
T15	826	355	0	0
T16	108678	107098	0	0
T17	26609	20853	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	86724974	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	86724974	0	0
T1	131876	165549	0	0
T2	2197	1060	0	0
T3	110980	24298	0	0
T11	212557	745316	0	0
T12	482226	109388	0	0
T13	2107	1063	0	0
T14	68086	179	0	0
T15	826	187	0	0
T16	108678	45912	0	0
T17	26609	14024	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1445923	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1445923	0	0
T1	131876	12907	0	0
T2	2197	48	0	0
T3	110980	1171	0	0
T11	212557	438	0	0
T12	482226	4487	0	0
T13	2107	23	0	0
T14	68086	16	0	0
T15	826	10	0	0
T16	108678	6	0	0
T17	26609	245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3511363	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3511363	0	0
T1	131876	5223	0	0
T2	2197	48	0	0
T3	110980	870	0	0
T11	212557	26281	0	0
T12	482226	3697	0	0
T13	2107	23	0	0
T14	68086	4	0	0
T15	826	10	0	0
T16	108678	203	0	0
T17	26609	245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1448411	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1448411	0	0
T1	131876	8484	0	0
T2	2197	35	0	0
T3	110980	984	0	0
T11	212557	412	0	0
T12	482226	4309	0	0
T13	2107	21	0	0
T14	68086	9	0	0
T15	826	3	0	0
T16	108678	25	0	0
T17	26609	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2906289	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2906289	0	0
T1	131876	3696	0	0
T2	2197	35	0	0
T3	110980	833	0	0
T11	212557	25957	0	0
T12	482226	3566	0	0
T13	2107	21	0	0
T14	68086	3	0	0
T15	826	3	0	0
T16	108678	1153	0	0
T17	26609	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1425415	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1425415	0	0
T1	131876	18215	0	0
T2	2197	29	0	0
T3	110980	1006	0	0
T11	212557	493	0	0
T12	482226	4296	0	0
T13	2107	20	0	0
T14	68086	8	0	0
T15	826	9	0	0
T16	108678	32	0	0
T17	26609	781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3289744	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3289744	0	0
T1	131876	6983	0	0
T2	2197	29	0	0
T3	110980	779	0	0
T11	212557	36144	0	0
T12	482226	3648	0	0
T13	2107	20	0	0
T14	68086	2	0	0
T15	826	9	0	0
T16	108678	2529	0	0
T17	26609	781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1392414	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1392414	0	0
T1	131876	19453	0	0
T2	2197	36	0	0
T3	110980	1155	0	0
T11	212557	416	0	0
T12	482226	4244	0	0
T13	2107	17	0	0
T14	68086	24	0	0
T15	826	4	0	0
T16	108678	18	0	0
T17	26609	462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3341042	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3341042	0	0
T1	131876	9991	0	0
T2	2197	36	0	0
T3	110980	809	0	0
T11	212557	25209	0	0
T12	482226	3202	0	0
T13	2107	17	0	0
T14	68086	6	0	0
T15	826	4	0	0
T16	108678	2332	0	0
T17	26609	462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1430039	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1430039	0	0
T1	131876	19135	0	0
T2	2197	37	0	0
T3	110980	1244	0	0
T11	212557	382	0	0
T12	482226	4815	0	0
T13	2107	24	0	0
T14	68086	15	0	0
T15	826	8	0	0
T16	108678	13	0	0
T17	26609	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3022004	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3022004	0	0
T1	131876	8555	0	0
T2	2197	37	0	0
T3	110980	909	0	0
T11	212557	23895	0	0
T12	482226	3565	0	0
T13	2107	24	0	0
T14	68086	5	0	0
T15	826	8	0	0
T16	108678	1220	0	0
T17	26609	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1374521	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1374521	0	0
T1	131876	15633	0	0
T2	2197	41	0	0
T3	110980	1174	0	0
T11	212557	508	0	0
T12	482226	4101	0	0
T13	2107	17	0	0
T14	68086	27	0	0
T15	826	9	0	0
T16	108678	18	0	0
T17	26609	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3796462	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3796462	0	0
T1	131876	7832	0	0
T2	2197	41	0	0
T3	110980	917	0	0
T11	212557	34657	0	0
T12	482226	3316	0	0
T13	2107	17	0	0
T14	68086	5	0	0
T15	826	9	0	0
T16	108678	926	0	0
T17	26609	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1455110	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1455110	0	0
T1	131876	13725	0	0
T2	2197	44	0	0
T3	110980	1130	0	0
T11	212557	516	0	0
T12	482226	4588	0	0
T13	2107	21	0	0
T14	68086	19	0	0
T15	826	9	0	0
T16	108678	25	0	0
T17	26609	549	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2754920	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2754920	0	0
T1	131876	5983	0	0
T2	2197	44	0	0
T3	110980	889	0	0
T11	212557	28715	0	0
T12	482226	3651	0	0
T13	2107	21	0	0
T14	68086	4	0	0
T15	826	9	0	0
T16	108678	2884	0	0
T17	26609	549	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1447935	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1447935	0	0
T1	131876	15392	0	0
T2	2197	34	0	0
T3	110980	1104	0	0
T11	212557	460	0	0
T12	482226	4693	0	0
T13	2107	19	0	0
T14	68086	39	0	0
T15	826	7	0	0
T16	108678	34	0	0
T17	26609	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3172883	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3172883	0	0
T1	131876	5127	0	0
T2	2197	34	0	0
T3	110980	939	0	0
T11	212557	28196	0	0
T12	482226	3463	0	0
T13	2107	19	0	0
T14	68086	13	0	0
T15	826	7	0	0
T16	108678	1970	0	0
T17	26609	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1362790	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1362790	0	0
T1	131876	17443	0	0
T2	2197	35	0	0
T3	110980	1116	0	0
T11	212557	366	0	0
T12	482226	4052	0	0
T13	2107	15	0	0
T14	68086	32	0	0
T15	826	8	0	0
T16	108678	13	0	0
T17	26609	271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2935990	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2935990	0	0
T1	131876	6711	0	0
T2	2197	35	0	0
T3	110980	905	0	0
T11	212557	23007	0	0
T12	482226	3606	0	0
T13	2107	15	0	0
T14	68086	7	0	0
T15	826	8	0	0
T16	108678	957	0	0
T17	26609	271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1367124	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1367124	0	0
T1	131876	18138	0	0
T2	2197	41	0	0
T3	110980	1089	0	0
T11	212557	411	0	0
T12	482226	3958	0	0
T13	2107	31	0	0
T14	68086	18	0	0
T15	826	5	0	0
T16	108678	11	0	0
T17	26609	563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2752251	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2752251	0	0
T1	131876	3986	0	0
T2	2197	41	0	0
T3	110980	888	0	0
T11	212557	22113	0	0
T12	482226	3434	0	0
T13	2107	31	0	0
T14	68086	3	0	0
T15	826	5	0	0
T16	108678	1649	0	0
T17	26609	563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1407240	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1407240	0	0
T1	131876	9621	0	0
T2	2197	36	0	0
T3	110980	1094	0	0
T11	212557	426	0	0
T12	482226	4262	0	0
T13	2107	24	0	0
T14	68086	1	0	0
T15	826	11	0	0
T16	108678	25	0	0
T17	26609	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2921276	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2921276	0	0
T1	131876	2829	0	0
T2	2197	36	0	0
T3	110980	879	0	0
T11	212557	24491	0	0
T12	482226	3392	0	0
T13	2107	24	0	0
T14	68086	1	0	0
T15	826	11	0	0
T16	108678	1435	0	0
T17	26609	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1403310	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1403310	0	0
T1	131876	16376	0	0
T2	2197	49	0	0
T3	110980	1186	0	0
T11	212557	382	0	0
T12	482226	4338	0	0
T13	2107	21	0	0
T14	68086	33	0	0
T15	826	8	0	0
T16	108678	27	0	0
T17	26609	1094	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3208626	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3208626	0	0
T1	131876	5018	0	0
T2	2197	49	0	0
T3	110980	918	0	0
T11	212557	31130	0	0
T12	482226	3461	0	0
T13	2107	21	0	0
T14	68086	6	0	0
T15	826	8	0	0
T16	108678	3257	0	0
T17	26609	1093	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1377781	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1377781	0	0
T1	131876	12782	0	0
T2	2197	40	0	0
T3	110980	1176	0	0
T11	212557	476	0	0
T12	482226	4250	0	0
T13	2107	11	0	0
T14	68086	13	0	0
T15	826	6	0	0
T16	108678	24	0	0
T17	26609	573	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3269636	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3269636	0	0
T1	131876	3867	0	0
T2	2197	40	0	0
T3	110980	820	0	0
T11	212557	28615	0	0
T12	482226	3643	0	0
T13	2107	11	0	0
T14	68086	3	0	0
T15	826	6	0	0
T16	108678	662	0	0
T17	26609	572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1455313	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1455313	0	0
T1	131876	13383	0	0
T2	2197	44	0	0
T3	110980	1094	0	0
T11	212557	491	0	0
T12	482226	4113	0	0
T13	2107	20	0	0
T14	68086	30	0	0
T15	826	4	0	0
T16	108678	3	0	0
T17	26609	253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2432155	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2432155	0	0
T1	131876	4280	0	0
T2	2197	44	0	0
T3	110980	829	0	0
T11	212557	29475	0	0
T12	482226	3465	0	0
T13	2107	20	0	0
T14	68086	9	0	0
T15	826	4	0	0
T16	108678	57	0	0
T17	26609	252	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1445375	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1445375	0	0
T1	131876	17235	0	0
T2	2197	38	0	0
T3	110980	1179	0	0
T11	212557	400	0	0
T12	482226	4733	0	0
T13	2107	24	0	0
T14	68086	30	0	0
T15	826	8	0	0
T16	108678	0	0	0
T17	26609	278	0	0
T18	0	25879	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3596824	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3596824	0	0
T1	131876	7237	0	0
T2	2197	38	0	0
T3	110980	898	0	0
T11	212557	23644	0	0
T12	482226	3399	0	0
T13	2107	24	0	0
T14	68086	48	0	0
T15	826	8	0	0
T16	108678	0	0	0
T17	26609	278	0	0
T18	0	7380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1431551	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1431551	0	0
T1	131876	14943	0	0
T2	2197	35	0	0
T3	110980	1398	0	0
T11	212557	510	0	0
T12	482226	4062	0	0
T13	2107	19	0	0
T14	68086	12	0	0
T15	826	8	0	0
T16	108678	12	0	0
T17	26609	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3122047	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3122047	0	0
T1	131876	6520	0	0
T2	2197	35	0	0
T3	110980	1076	0	0
T11	212557	30811	0	0
T12	482226	3292	0	0
T13	2107	19	0	0
T14	68086	3	0	0
T15	826	8	0	0
T16	108678	1369	0	0
T17	26609	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1450896	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1450896	0	0
T1	131876	17311	0	0
T2	2197	39	0	0
T3	110980	983	0	0
T11	212557	434	0	0
T12	482226	4238	0	0
T13	2107	24	0	0
T14	68086	10	0	0
T15	826	6	0	0
T16	108678	18	0	0
T17	26609	535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3021946	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3021946	0	0
T1	131876	4467	0	0
T2	2197	39	0	0
T3	110980	770	0	0
T11	212557	23458	0	0
T12	482226	3561	0	0
T13	2107	24	0	0
T14	68086	3	0	0
T15	826	6	0	0
T16	108678	1787	0	0
T17	26609	535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1414741	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1414741	0	0
T1	131876	15132	0	0
T2	2197	36	0	0
T3	110980	1203	0	0
T11	212557	466	0	0
T12	482226	4633	0	0
T13	2107	13	0	0
T14	68086	10	0	0
T15	826	9	0	0
T16	108678	16	0	0
T17	26609	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3182248	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3182248	0	0
T1	131876	7911	0	0
T2	2197	36	0	0
T3	110980	879	0	0
T11	212557	28545	0	0
T12	482226	3815	0	0
T13	2107	13	0	0
T14	68086	5	0	0
T15	826	9	0	0
T16	108678	2220	0	0
T17	26609	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1355760	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1355760	0	0
T1	131876	15695	0	0
T2	2197	30	0	0
T3	110980	1234	0	0
T11	212557	442	0	0
T12	482226	4379	0	0
T13	2107	20	0	0
T14	68086	23	0	0
T15	826	8	0	0
T16	108678	11	0	0
T17	26609	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3305414	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3305414	0	0
T1	131876	7058	0	0
T2	2197	30	0	0
T3	110980	918	0	0
T11	212557	28267	0	0
T12	482226	3641	0	0
T13	2107	20	0	0
T14	68086	10	0	0
T15	826	8	0	0
T16	108678	566	0	0
T17	26609	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1438680	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1438680	0	0
T1	131876	16529	0	0
T2	2197	36	0	0
T3	110980	1138	0	0
T11	212557	443	0	0
T12	482226	4621	0	0
T13	2107	21	0	0
T14	68086	16	0	0
T15	826	4	0	0
T16	108678	25	0	0
T17	26609	284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3282297	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3282297	0	0
T1	131876	5479	0	0
T2	2197	36	0	0
T3	110980	953	0	0
T11	212557	26968	0	0
T12	482226	3724	0	0
T13	2107	21	0	0
T14	68086	3	0	0
T15	826	4	0	0
T16	108678	1177	0	0
T17	26609	284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1442301	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1442301	0	0
T1	131876	14969	0	0
T2	2197	39	0	0
T3	110980	1111	0	0
T11	212557	376	0	0
T12	482226	4493	0	0
T13	2107	24	0	0
T14	68086	46	0	0
T15	826	9	0	0
T16	108678	34	0	0
T17	26609	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2869821	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2869821	0	0
T1	131876	4382	0	0
T2	2197	39	0	0
T3	110980	1092	0	0
T11	212557	19997	0	0
T12	482226	3644	0	0
T13	2107	24	0	0
T14	68086	9	0	0
T15	826	9	0	0
T16	108678	3344	0	0
T17	26609	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1411876	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1411876	0	0
T1	131876	13257	0	0
T2	2197	45	0	0
T3	110980	1209	0	0
T11	212557	401	0	0
T12	482226	4432	0	0
T13	2107	18	0	0
T14	68086	36	0	0
T15	826	8	0	0
T16	108678	29	0	0
T17	26609	746	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3582635	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3582635	0	0
T1	131876	6679	0	0
T2	2197	45	0	0
T3	110980	919	0	0
T11	212557	33462	0	0
T12	482226	3375	0	0
T13	2107	18	0	0
T14	68086	6	0	0
T15	826	8	0	0
T16	108678	2150	0	0
T17	26609	746	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1411871	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1411871	0	0
T1	131876	13129	0	0
T2	2197	46	0	0
T3	110980	949	0	0
T11	212557	402	0	0
T12	482226	4354	0	0
T13	2107	16	0	0
T14	68086	3	0	0
T15	826	5	0	0
T16	108678	16	0	0
T17	26609	543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3661820	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3661820	0	0
T1	131876	5888	0	0
T2	2197	46	0	0
T3	110980	636	0	0
T11	212557	28620	0	0
T12	482226	3677	0	0
T13	2107	16	0	0
T14	68086	1	0	0
T15	826	5	0	0
T16	108678	1291	0	0
T17	26609	543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1459987	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1459987	0	0
T1	131876	16841	0	0
T2	2197	39	0	0
T3	110980	1165	0	0
T11	212557	434	0	0
T12	482226	4770	0	0
T13	2107	22	0	0
T14	68086	31	0	0
T15	826	4	0	0
T16	108678	3	0	0
T17	26609	949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	2970569	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	2970569	0	0
T1	131876	6218	0	0
T2	2197	39	0	0
T3	110980	933	0	0
T11	212557	29322	0	0
T12	482226	3773	0	0
T13	2107	22	0	0
T14	68086	7	0	0
T15	826	4	0	0
T16	108678	340	0	0
T17	26609	949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1439887	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1439887	0	0
T1	131876	19687	0	0
T2	2197	38	0	0
T3	110980	1053	0	0
T11	212557	426	0	0
T12	482226	4397	0	0
T13	2107	19	0	0
T14	68086	24	0	0
T15	826	8	0	0
T16	108678	47	0	0
T17	26609	579	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3032757	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3032757	0	0
T1	131876	8083	0	0
T2	2197	38	0	0
T3	110980	844	0	0
T11	212557	30499	0	0
T12	482226	3549	0	0
T13	2107	19	0	0
T14	68086	5	0	0
T15	826	8	0	0
T16	108678	4848	0	0
T17	26609	579	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1449756	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1449756	0	0
T1	131876	18090	0	0
T2	2197	38	0	0
T3	110980	1126	0	0
T11	212557	397	0	0
T12	482226	4332	0	0
T13	2107	20	0	0
T14	68086	4	0	0
T15	826	7	0	0
T16	108678	34	0	0
T17	26609	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3440480	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3440480	0	0
T1	131876	6326	0	0
T2	2197	38	0	0
T3	110980	743	0	0
T11	212557	24162	0	0
T12	482226	3448	0	0
T13	2107	20	0	0
T14	68086	3	0	0
T15	826	7	0	0
T16	108678	3770	0	0
T17	26609	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	1453998	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	1453998	0	0
T1	131876	20314	0	0
T2	2197	51	0	0
T3	110980	995	0	0
T11	212557	527	0	0
T12	482226	4470	0	0
T13	2107	19	0	0
T14	68086	18	0	0
T15	826	2	0	0
T16	108678	20	0	0
T17	26609	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304526448	3358329	0	0
DepthKnown_A	304526448	304411517	0	0
RvalidKnown_A	304526448	304411517	0	0
WreadyKnown_A	304526448	304411517	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	3358329	0	0
T1	131876	9220	0	0
T2	2197	51	0	0
T3	110980	897	0	0
T11	212557	29676	0	0
T12	482226	3852	0	0
T13	2107	19	0	0
T14	68086	5	0	0
T15	826	2	0	0
T16	108678	1816	0	0
T17	26609	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304526448	304411517	0	0
T1	131876	131872	0	0
T2	2197	2171	0	0
T3	110980	110894	0	0
T11	212557	212553	0	0
T12	482226	482083	0	0
T13	2107	2074	0	0
T14	68086	68045	0	0
T15	826	761	0	0
T16	108678	108664	0	0
T17	26609	25443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0