Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1816710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

285188

1

T1

667

T2

275

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	709812	1			T1	1769		T2	679		T3	118
values[0x0]	682174	1			T1	1649		T2	648		T3	16
values[0x1]	709912	1			T1	1715		T2	695		T3	100

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1409347	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

692551

1

T1

1708

T2

666

T3

82

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7749	1			T1	22		T2	5		T3	3
valid_sources[0x01]	8231	1			T1	21		T2	5		T4	8
valid_sources[0x02]	8648	1			T1	21		T2	7		T3	1
valid_sources[0x03]	8702	1			T1	22		T2	15		T4	5
valid_sources[0x04]	8051	1			T1	19		T2	3		T4	6
valid_sources[0x05]	7594	1			T1	23		T2	12		T4	22
valid_sources[0x06]	9036	1			T1	22		T2	7		T3	1
valid_sources[0x07]	8689	1			T1	20		T2	4		T4	12
valid_sources[0x08]	8674	1			T1	20		T2	5		T3	1
valid_sources[0x09]	8241	1			T1	21		T2	11		T4	15
valid_sources[0x0a]	8477	1			T1	21		T2	7		T4	8
valid_sources[0x0b]	7895	1			T1	20		T2	12		T4	9
valid_sources[0x0c]	7855	1			T1	20		T2	5		T3	1
valid_sources[0x0d]	7774	1			T1	20		T2	5		T3	2
valid_sources[0x0e]	8727	1			T1	20		T2	5		T4	5
valid_sources[0x0f]	7957	1			T1	19		T2	6		T3	4
valid_sources[0x10]	7351	1			T1	20		T2	14		T3	1
valid_sources[0x11]	8053	1			T1	20		T2	7		T3	2
valid_sources[0x12]	8251	1			T1	22		T2	10		T4	11
valid_sources[0x13]	8742	1			T1	18		T2	13		T3	2
valid_sources[0x14]	8096	1			T1	21		T2	16		T3	2
valid_sources[0x15]	8925	1			T1	18		T2	15		T3	2
valid_sources[0x16]	7671	1			T1	23		T2	6		T3	2
valid_sources[0x17]	7956	1			T1	20		T2	11		T3	1
valid_sources[0x18]	8005	1			T1	18		T2	5		T3	1
valid_sources[0x19]	7930	1			T1	20		T2	9		T4	12
valid_sources[0x1a]	9253	1			T1	20		T2	10		T4	17
valid_sources[0x1b]	9454	1			T1	19		T2	6		T4	13
valid_sources[0x1c]	8721	1			T1	18		T2	11		T3	1
valid_sources[0x1d]	7800	1			T1	22		T2	3		T4	16
valid_sources[0x1e]	8335	1			T1	22		T2	10		T4	9
valid_sources[0x1f]	7635	1			T1	18		T2	8		T4	11
valid_sources[0x20]	7999	1			T1	17		T2	7		T3	3
valid_sources[0x21]	7556	1			T1	20		T2	5		T4	17
valid_sources[0x22]	8215	1			T1	20		T2	4		T4	9
valid_sources[0x23]	8468	1			T1	19		T2	7		T3	2
valid_sources[0x24]	9557	1			T1	20		T2	12		T4	6
valid_sources[0x25]	8264	1			T1	17		T2	6		T3	1
valid_sources[0x26]	8264	1			T1	18		T2	13		T4	14
valid_sources[0x27]	7612	1			T1	20		T2	8		T3	1
valid_sources[0x28]	8106	1			T1	20		T2	11		T4	17
valid_sources[0x29]	8455	1			T1	22		T2	7		T3	1
valid_sources[0x2a]	8368	1			T1	22		T2	17		T4	8
valid_sources[0x2b]	7913	1			T1	19		T2	6		T4	11
valid_sources[0x2c]	7975	1			T1	20		T2	11		T3	3
valid_sources[0x2d]	10567	1			T1	20		T2	7		T3	1
valid_sources[0x2e]	8331	1			T1	24		T2	13		T3	2
valid_sources[0x2f]	8180	1			T1	19		T2	6		T4	9
valid_sources[0x30]	8894	1			T1	21		T2	2		T4	14
valid_sources[0x31]	8494	1			T1	19		T2	6		T4	15
valid_sources[0x32]	7821	1			T1	21		T2	12		T3	1
valid_sources[0x33]	7391	1			T1	18		T2	6		T3	1
valid_sources[0x34]	8098	1			T1	19		T2	4		T3	1
valid_sources[0x35]	7960	1			T1	20		T2	9		T4	9
valid_sources[0x36]	7592	1			T1	23		T2	10		T3	1
valid_sources[0x37]	7992	1			T1	21		T2	11		T3	1
valid_sources[0x38]	8643	1			T1	19		T2	6		T3	1
valid_sources[0x39]	8509	1			T1	20		T2	10		T3	1
valid_sources[0x3a]	9186	1			T1	18		T2	6		T3	2
valid_sources[0x3b]	8293	1			T1	19		T2	9		T3	1
valid_sources[0x3c]	8463	1			T1	19		T2	5		T3	2
valid_sources[0x3d]	7829	1			T1	20		T2	3		T4	11
valid_sources[0x3e]	7308	1			T1	23		T2	9		T3	1
valid_sources[0x3f]	8569	1			T1	20		T2	6		T3	1
valid_sources[0x40]	8777	1			T1	18		T2	2		T4	7
valid_sources[0x41]	8515	1			T1	20		T2	7		T3	2
valid_sources[0x42]	7519	1			T1	20		T2	10		T4	11
valid_sources[0x43]	7552	1			T1	23		T2	5		T3	2
valid_sources[0x44]	8426	1			T1	19		T2	8		T4	14
valid_sources[0x45]	7477	1			T1	20		T2	4		T3	1
valid_sources[0x46]	8673	1			T1	21		T2	4		T4	7
valid_sources[0x47]	8148	1			T1	20		T2	10		T3	6
valid_sources[0x48]	8491	1			T1	21		T2	6		T4	15
valid_sources[0x49]	7611	1			T1	21		T2	3		T3	1
valid_sources[0x4a]	8431	1			T1	18		T2	12		T3	2
valid_sources[0x4b]	8311	1			T1	21		T2	3		T3	1
valid_sources[0x4c]	7781	1			T1	21		T2	5		T4	16
valid_sources[0x4d]	8331	1			T1	22		T2	1		T3	1
valid_sources[0x4e]	7714	1			T1	19		T2	9		T3	2
valid_sources[0x4f]	9344	1			T1	19		T2	4		T4	10
valid_sources[0x50]	8009	1			T1	20		T2	6		T3	2
valid_sources[0x51]	8150	1			T1	20		T2	10		T3	1
valid_sources[0x52]	9173	1			T1	21		T2	12		T4	11
valid_sources[0x53]	8260	1			T1	20		T2	8		T4	10
valid_sources[0x54]	8431	1			T1	20		T2	12		T3	3
valid_sources[0x55]	8322	1			T1	20		T2	4		T3	1
valid_sources[0x56]	7998	1			T1	21		T2	11		T4	14
valid_sources[0x57]	7669	1			T1	21		T2	9		T3	2
valid_sources[0x58]	9086	1			T1	22		T2	10		T3	3
valid_sources[0x59]	9740	1			T1	21		T2	7		T4	9
valid_sources[0x5a]	8303	1			T1	20		T2	11		T4	8
valid_sources[0x5b]	8346	1			T1	21		T2	9		T3	1
valid_sources[0x5c]	8287	1			T1	19		T2	7		T3	2
valid_sources[0x5d]	8079	1			T1	21		T2	9		T3	1
valid_sources[0x5e]	8700	1			T1	20		T2	4		T3	1
valid_sources[0x5f]	7829	1			T1	20		T2	7		T4	14
valid_sources[0x60]	7567	1			T1	20		T2	6		T4	12
valid_sources[0x61]	8493	1			T1	19		T2	8		T3	1
valid_sources[0x62]	8438	1			T1	19		T2	6		T3	1
valid_sources[0x63]	7915	1			T1	20		T2	4		T4	10
valid_sources[0x64]	7729	1			T1	21		T2	5		T3	1
valid_sources[0x65]	9098	1			T1	19		T2	4		T3	2
valid_sources[0x66]	7667	1			T1	19		T2	4		T3	1
valid_sources[0x67]	7775	1			T1	19		T2	7		T4	9
valid_sources[0x68]	8251	1			T1	20		T2	11		T4	6
valid_sources[0x69]	8063	1			T1	19		T2	5		T3	1
valid_sources[0x6a]	8361	1			T1	14		T2	7		T4	10
valid_sources[0x6b]	8127	1			T1	20		T2	5		T4	12
valid_sources[0x6c]	8173	1			T1	19		T2	10		T4	11
valid_sources[0x6d]	8469	1			T1	21		T2	6		T3	2
valid_sources[0x6e]	8630	1			T1	19		T2	4		T3	3
valid_sources[0x6f]	7787	1			T1	20		T2	6		T4	11
valid_sources[0x70]	7927	1			T1	22		T2	9		T3	4
valid_sources[0x71]	8759	1			T1	19		T2	13		T3	6
valid_sources[0x72]	7874	1			T1	18		T2	5		T4	8
valid_sources[0x73]	8373	1			T1	19		T2	5		T4	13
valid_sources[0x74]	7623	1			T1	20		T2	8		T3	1
valid_sources[0x75]	7741	1			T1	22		T2	16		T3	2
valid_sources[0x76]	7609	1			T1	19		T2	9		T3	1
valid_sources[0x77]	8914	1			T1	19		T2	6		T3	1
valid_sources[0x78]	8062	1			T1	22		T2	8		T4	10
valid_sources[0x79]	8792	1			T1	17		T2	14		T3	1
valid_sources[0x7a]	9116	1			T1	20		T2	8		T4	13
valid_sources[0x7b]	8213	1			T1	19		T2	4		T3	2
valid_sources[0x7c]	7856	1			T1	18		T2	4		T4	7
valid_sources[0x7d]	8036	1			T1	19		T2	17		T3	1
valid_sources[0x7e]	8179	1			T1	20		T2	10		T3	1
valid_sources[0x7f]	7766	1			T1	18		T2	12		T3	1
valid_sources[0x80]	8612	1			T1	19		T2	8		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29716

1

T1

56

T2

36

T3

6

values[0x0]

all_enables

biggest_size

225567

1

T1

534

T2

207

T3

8

values[0x1]

all_enables

biggest_size

29905

1

T1

77

T2

32

T3

6