Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	349949536	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349949536	0	0
T1	15856256	2110100	0	0
T2	248472	9928	0	0
T3	520128	21343	0	0
T4	2753128	38915	0	0
T13	89432	3278	0	0
T14	45360	933	0	0
T15	2166192	32061	0	0
T16	760704	10803	0	0
T17	349272	7542	0	0
T18	31806992	610266	0	0
T19	5079648	46305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	27748448	27748168	0	0
T2	248472	245168	0	0
T3	520128	515144	0	0
T4	2753128	2749824	0	0
T13	89432	88872	0	0
T14	45360	42560	0	0
T15	2166192	2163784	0	0
T16	760704	758464	0	0
T17	349272	346864	0	0
T18	31806992	31803352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	27748448	27748168	0	0
T2	248472	245168	0	0
T3	520128	515144	0	0
T4	2753128	2749824	0	0
T13	89432	88872	0	0
T14	45360	42560	0	0
T15	2166192	2163784	0	0
T16	760704	758464	0	0
T17	349272	346864	0	0
T18	31806992	31803352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	27748448	27748168	0	0
T2	248472	245168	0	0
T3	520128	515144	0	0
T4	2753128	2749824	0	0
T13	89432	88872	0	0
T14	45360	42560	0	0
T15	2166192	2163784	0	0
T16	760704	758464	0	0
T17	349272	346864	0	0
T18	31806992	31803352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	127961202	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	127961202	0	0
T1	495508	25763	0	0
T2	4437	3864	0	0
T3	9288	8784	0	0
T4	49163	17328	0	0
T13	1597	1505	0	0
T14	810	363	0	0
T15	38682	15176	0	0
T16	13584	5135	0	0
T17	6237	2909	0	0
T18	567982	260482	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	90508889	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	90508889	0	0
T1	495508	187496	0	0
T2	4437	2022	0	0
T3	9288	5033	0	0
T4	49163	6036	0	0
T13	1597	881	0	0
T14	810	190	0	0
T15	38682	4645	0	0
T16	13584	1550	0	0
T17	6237	1525	0	0
T18	567982	85786	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1594471	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1594471	0	0
T2	4437	82	0	0
T3	9288	94	0	0
T4	49163	455	0	0
T13	1597	19	0	0
T14	810	11	0	0
T15	38682	447	0	0
T16	13584	141	0	0
T17	6237	87	0	0
T18	567982	4137	0	0
T19	211652	247	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3168393	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3168393	0	0
T2	4437	82	0	0
T3	9288	94	0	0
T4	49163	142	0	0
T13	1597	19	0	0
T14	810	11	0	0
T15	38682	161	0	0
T16	13584	59	0	0
T17	6237	104	0	0
T18	567982	1913	0	0
T19	211652	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1521315	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1521315	0	0
T2	4437	79	0	0
T3	9288	278	0	0
T4	49163	357	0	0
T13	1597	14	0	0
T14	810	7	0	0
T15	38682	282	0	0
T16	13584	119	0	0
T17	6237	64	0	0
T18	567982	8431	0	0
T19	211652	2192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3263873	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3263873	0	0
T2	4437	79	0	0
T3	9288	278	0	0
T4	49163	110	0	0
T13	1597	14	0	0
T14	810	7	0	0
T15	38682	149	0	0
T16	13584	25	0	0
T17	6237	40	0	0
T18	567982	3847	0	0
T19	211652	4734	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1508221	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1508221	0	0
T2	4437	82	0	0
T3	9288	70	0	0
T4	49163	397	0	0
T13	1597	17	0	0
T14	810	6	0	0
T15	38682	252	0	0
T16	13584	148	0	0
T17	6237	31	0	0
T18	567982	8757	0	0
T19	211652	1116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2663936	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2663936	0	0
T2	4437	82	0	0
T3	9288	70	0	0
T4	49163	164	0	0
T13	1597	17	0	0
T14	810	6	0	0
T15	38682	98	0	0
T16	13584	36	0	0
T17	6237	62	0	0
T18	567982	4285	0	0
T19	211652	2969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1530774	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1530774	0	0
T2	4437	70	0	0
T3	9288	86	0	0
T4	49163	424	0	0
T13	1597	13	0	0
T14	810	4	0	0
T15	38682	268	0	0
T16	13584	56	0	0
T17	6237	40	0	0
T18	567982	4095	0	0
T19	211652	2612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3441205	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3441205	0	0
T2	4437	70	0	0
T3	9288	86	0	0
T4	49163	217	0	0
T13	1597	13	0	0
T14	810	4	0	0
T15	38682	95	0	0
T16	13584	29	0	0
T17	6237	19	0	0
T18	567982	2078	0	0
T19	211652	2361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1537718	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1537718	0	0
T1	495508	1025	0	0
T2	4437	81	0	0
T3	9288	83	0	0
T4	49163	382	0	0
T13	1597	18	0	0
T14	810	10	0	0
T15	38682	244	0	0
T16	13584	87	0	0
T17	6237	84	0	0
T18	567982	5306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3218694	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3218694	0	0
T1	495508	79141	0	0
T2	4437	81	0	0
T3	9288	83	0	0
T4	49163	166	0	0
T13	1597	18	0	0
T14	810	10	0	0
T15	38682	95	0	0
T16	13584	52	0	0
T17	6237	90	0	0
T18	567982	2807	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1555576	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1555576	0	0
T2	4437	75	0	0
T3	9288	89	0	0
T4	49163	513	0	0
T13	1597	16	0	0
T14	810	4	0	0
T15	38682	344	0	0
T16	13584	106	0	0
T17	6237	70	0	0
T18	567982	8230	0	0
T19	211652	1073	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2555747	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2555747	0	0
T2	4437	75	0	0
T3	9288	89	0	0
T4	49163	200	0	0
T13	1597	16	0	0
T14	810	4	0	0
T15	38682	136	0	0
T16	13584	47	0	0
T17	6237	85	0	0
T18	567982	3666	0	0
T19	211652	1366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1598989	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1598989	0	0
T1	495508	943	0	0
T2	4437	78	0	0
T3	9288	84	0	0
T4	49163	373	0	0
T13	1597	21	0	0
T14	810	9	0	0
T15	38682	320	0	0
T16	13584	66	0	0
T17	6237	49	0	0
T18	567982	9519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2777858	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2777858	0	0
T1	495508	78385	0	0
T2	4437	78	0	0
T3	9288	84	0	0
T4	49163	130	0	0
T13	1597	21	0	0
T14	810	9	0	0
T15	38682	114	0	0
T16	13584	17	0	0
T17	6237	36	0	0
T18	567982	4155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1545712	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1545712	0	0
T1	495508	1260	0	0
T2	4437	79	0	0
T3	9288	99	0	0
T4	49163	463	0	0
T13	1597	11	0	0
T14	810	6	0	0
T15	38682	310	0	0
T16	13584	78	0	0
T17	6237	42	0	0
T18	567982	5940	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2845093	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2845093	0	0
T1	495508	107744	0	0
T2	4437	79	0	0
T3	9288	99	0	0
T4	49163	182	0	0
T13	1597	11	0	0
T14	810	6	0	0
T15	38682	124	0	0
T16	13584	25	0	0
T17	6237	55	0	0
T18	567982	2799	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1614851	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1614851	0	0
T2	4437	74	0	0
T3	9288	72	0	0
T4	49163	417	0	0
T13	1597	12	0	0
T14	810	4	0	0
T15	38682	369	0	0
T16	13584	149	0	0
T17	6237	80	0	0
T18	567982	3913	0	0
T19	211652	664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2783813	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2783813	0	0
T2	4437	74	0	0
T3	9288	72	0	0
T4	49163	264	0	0
T13	1597	12	0	0
T14	810	4	0	0
T15	38682	112	0	0
T16	13584	55	0	0
T17	6237	71	0	0
T18	567982	1731	0	0
T19	211652	1277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1572558	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1572558	0	0
T1	495508	1244	0	0
T2	4437	90	0	0
T3	9288	89	0	0
T4	49163	339	0	0
T13	1597	20	0	0
T14	810	5	0	0
T15	38682	298	0	0
T16	13584	98	0	0
T17	6237	53	0	0
T18	567982	7209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3381916	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3381916	0	0
T1	495508	97752	0	0
T2	4437	90	0	0
T3	9288	89	0	0
T4	49163	151	0	0
T13	1597	20	0	0
T14	810	5	0	0
T15	38682	117	0	0
T16	13584	56	0	0
T17	6237	52	0	0
T18	567982	4123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1612763	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1612763	0	0
T1	495508	1400	0	0
T2	4437	73	0	0
T3	9288	88	0	0
T4	49163	353	0	0
T13	1597	17	0	0
T14	810	3	0	0
T15	38682	291	0	0
T16	13584	93	0	0
T17	6237	37	0	0
T18	567982	5425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3371725	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3371725	0	0
T1	495508	101364	0	0
T2	4437	73	0	0
T3	9288	88	0	0
T4	49163	176	0	0
T13	1597	17	0	0
T14	810	3	0	0
T15	38682	124	0	0
T16	13584	38	0	0
T17	6237	14	0	0
T18	567982	3100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1529990	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1529990	0	0
T2	4437	61	0	0
T3	9288	323	0	0
T4	49163	384	0	0
T13	1597	14	0	0
T14	810	5	0	0
T15	38682	315	0	0
T16	13584	102	0	0
T17	6237	49	0	0
T18	567982	6507	0	0
T19	211652	2082	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3290699	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3290699	0	0
T2	4437	61	0	0
T3	9288	323	0	0
T4	49163	211	0	0
T13	1597	14	0	0
T14	810	5	0	0
T15	38682	100	0	0
T16	13584	49	0	0
T17	6237	32	0	0
T18	567982	2902	0	0
T19	211652	1978	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1528817	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1528817	0	0
T1	495508	2534	0	0
T2	4437	60	0	0
T3	9288	85	0	0
T4	49163	371	0	0
T13	1597	18	0	0
T14	810	5	0	0
T15	38682	224	0	0
T16	13584	109	0	0
T17	6237	53	0	0
T18	567982	8064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3467481	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3467481	0	0
T1	495508	197725	0	0
T2	4437	60	0	0
T3	9288	85	0	0
T4	49163	136	0	0
T13	1597	18	0	0
T14	810	5	0	0
T15	38682	72	0	0
T16	13584	83	0	0
T17	6237	61	0	0
T18	567982	3656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1551691	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1551691	0	0
T1	495508	1138	0	0
T2	4437	80	0	0
T3	9288	77	0	0
T4	49163	484	0	0
T13	1597	17	0	0
T14	810	10	0	0
T15	38682	317	0	0
T16	13584	55	0	0
T17	6237	36	0	0
T18	567982	4266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3334808	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3334808	0	0
T1	495508	88003	0	0
T2	4437	80	0	0
T3	9288	77	0	0
T4	49163	229	0	0
T13	1597	17	0	0
T14	810	10	0	0
T15	38682	137	0	0
T16	13584	9	0	0
T17	6237	20	0	0
T18	567982	1965	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1570030	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1570030	0	0
T2	4437	53	0	0
T3	9288	82	0	0
T4	49163	398	0	0
T13	1597	14	0	0
T14	810	10	0	0
T15	38682	343	0	0
T16	13584	220	0	0
T17	6237	64	0	0
T18	567982	10403	0	0
T19	211652	3496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3687586	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3687586	0	0
T2	4437	53	0	0
T3	9288	82	0	0
T4	49163	180	0	0
T13	1597	14	0	0
T14	810	10	0	0
T15	38682	186	0	0
T16	13584	71	0	0
T17	6237	37	0	0
T18	567982	4445	0	0
T19	211652	1723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1555759	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1555759	0	0
T2	4437	57	0	0
T3	9288	68	0	0
T4	49163	312	0	0
T13	1597	18	0	0
T14	810	7	0	0
T15	38682	337	0	0
T16	13584	95	0	0
T17	6237	76	0	0
T18	567982	7852	0	0
T19	211652	2010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3387862	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3387862	0	0
T2	4437	57	0	0
T3	9288	68	0	0
T4	49163	155	0	0
T13	1597	18	0	0
T14	810	7	0	0
T15	38682	122	0	0
T16	13584	19	0	0
T17	6237	73	0	0
T18	567982	3393	0	0
T19	211652	5003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1536221	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1536221	0	0
T1	495508	2587	0	0
T2	4437	69	0	0
T3	9288	78	0	0
T4	49163	481	0	0
T13	1597	21	0	0
T14	810	3	0	0
T15	38682	460	0	0
T16	13584	109	0	0
T17	6237	55	0	0
T18	567982	12186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3328323	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3328323	0	0
T1	495508	192781	0	0
T2	4437	69	0	0
T3	9288	78	0	0
T4	49163	201	0	0
T13	1597	21	0	0
T14	810	3	0	0
T15	38682	146	0	0
T16	13584	33	0	0
T17	6237	73	0	0
T18	567982	5266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1587715	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1587715	0	0
T2	4437	68	0	0
T3	9288	93	0	0
T4	49163	532	0	0
T13	1597	13	0	0
T14	810	8	0	0
T15	38682	309	0	0
T16	13584	145	0	0
T17	6237	63	0	0
T18	567982	10594	0	0
T19	211652	490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3293004	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3293004	0	0
T2	4437	68	0	0
T3	9288	93	0	0
T4	49163	195	0	0
T13	1597	13	0	0
T14	810	8	0	0
T15	38682	118	0	0
T16	13584	55	0	0
T17	6237	92	0	0
T18	567982	4566	0	0
T19	211652	352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1486734	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1486734	0	0
T1	495508	1359	0	0
T2	4437	83	0	0
T3	9288	324	0	0
T4	49163	525	0	0
T13	1597	15	0	0
T14	810	10	0	0
T15	38682	448	0	0
T16	13584	98	0	0
T17	6237	83	0	0
T18	567982	4049	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3649925	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3649925	0	0
T1	495508	109066	0	0
T2	4437	83	0	0
T3	9288	324	0	0
T4	49163	196	0	0
T13	1597	15	0	0
T14	810	10	0	0
T15	38682	154	0	0
T16	13584	62	0	0
T17	6237	97	0	0
T18	567982	2100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1514933	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1514933	0	0
T1	495508	1253	0	0
T2	4437	69	0	0
T3	9288	87	0	0
T4	49163	426	0	0
T13	1597	11	0	0
T14	810	13	0	0
T15	38682	367	0	0
T16	13584	143	0	0
T17	6237	58	0	0
T18	567982	4074	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3293439	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3293439	0	0
T1	495508	96879	0	0
T2	4437	69	0	0
T3	9288	87	0	0
T4	49163	138	0	0
T13	1597	11	0	0
T14	810	13	0	0
T15	38682	133	0	0
T16	13584	48	0	0
T17	6237	47	0	0
T18	567982	1863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1586785	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1586785	0	0
T2	4437	87	0	0
T3	9288	91	0	0
T4	49163	443	0	0
T13	1597	15	0	0
T14	810	6	0	0
T15	38682	324	0	0
T16	13584	120	0	0
T17	6237	66	0	0
T18	567982	6448	0	0
T19	211652	1237	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3240267	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3240267	0	0
T2	4437	87	0	0
T3	9288	91	0	0
T4	49163	223	0	0
T13	1597	15	0	0
T14	810	6	0	0
T15	38682	158	0	0
T16	13584	41	0	0
T17	6237	72	0	0
T18	567982	2678	0	0
T19	211652	1803	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1508139	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1508139	0	0
T1	495508	998	0	0
T2	4437	67	0	0
T3	9288	72	0	0
T4	49163	352	0	0
T13	1597	22	0	0
T14	810	7	0	0
T15	38682	373	0	0
T16	13584	67	0	0
T17	6237	42	0	0
T18	567982	6026	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3722766	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3722766	0	0
T1	495508	81164	0	0
T2	4437	67	0	0
T3	9288	72	0	0
T4	49163	172	0	0
T13	1597	22	0	0
T14	810	7	0	0
T15	38682	143	0	0
T16	13584	17	0	0
T17	6237	60	0	0
T18	567982	2832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1551843	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1551843	0	0
T1	495508	3661	0	0
T2	4437	89	0	0
T3	9288	84	0	0
T4	49163	467	0	0
T13	1597	18	0	0
T14	810	8	0	0
T15	38682	261	0	0
T16	13584	117	0	0
T17	6237	37	0	0
T18	567982	3718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3734105	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3734105	0	0
T1	495508	285108	0	0
T2	4437	89	0	0
T3	9288	84	0	0
T4	49163	163	0	0
T13	1597	18	0	0
T14	810	8	0	0
T15	38682	128	0	0
T16	13584	40	0	0
T17	6237	21	0	0
T18	567982	1782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1580010	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1580010	0	0
T2	4437	72	0	0
T3	9288	333	0	0
T4	49163	292	0	0
T13	1597	13	0	0
T14	810	8	0	0
T15	38682	226	0	0
T16	13584	82	0	0
T17	6237	64	0	0
T18	567982	6441	0	0
T19	211652	2898	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	2849713	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	2849713	0	0
T2	4437	72	0	0
T3	9288	333	0	0
T4	49163	122	0	0
T13	1597	13	0	0
T14	810	8	0	0
T15	38682	139	0	0
T16	13584	46	0	0
T17	6237	38	0	0
T18	567982	2985	0	0
T19	211652	1800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1552289	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1552289	0	0
T1	495508	1303	0	0
T2	4437	77	0	0
T3	9288	641	0	0
T4	49163	275	0	0
T13	1597	23	0	0
T14	810	9	0	0
T15	38682	275	0	0
T16	13584	116	0	0
T17	6237	80	0	0
T18	567982	8364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	3432735	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	3432735	0	0
T1	495508	102183	0	0
T2	4437	77	0	0
T3	9288	641	0	0
T4	49163	100	0	0
T13	1597	23	0	0
T14	810	9	0	0
T15	38682	127	0	0
T16	13584	58	0	0
T17	6237	72	0	0
T18	567982	3817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1571863	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1571863	0	0
T1	495508	1005	0	0
T2	4437	84	0	0
T3	9288	97	0	0
T4	49163	369	0	0
T13	1597	18	0	0
T14	810	7	0	0
T15	38682	255	0	0
T16	13584	182	0	0
T17	6237	75	0	0
T18	567982	4152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	4068514	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	4068514	0	0
T1	495508	87842	0	0
T2	4437	84	0	0
T3	9288	97	0	0
T4	49163	168	0	0
T13	1597	18	0	0
T14	810	7	0	0
T15	38682	128	0	0
T16	13584	48	0	0
T17	6237	61	0	0
T18	567982	2086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	1551539	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	1551539	0	0
T1	495508	2115	0	0
T2	4437	82	0	0
T3	9288	96	0	0
T4	49163	347	0	0
T13	1597	18	0	0
T14	810	5	0	0
T15	38682	503	0	0
T16	13584	85	0	0
T17	6237	45	0	0
T18	567982	6382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319494823	4268659	0	0
DepthKnown_A	319494823	319371535	0	0
RvalidKnown_A	319494823	319371535	0	0
WreadyKnown_A	319494823	319371535	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	4268659	0	0
T1	495508	167879	0	0
T2	4437	82	0	0
T3	9288	96	0	0
T4	49163	129	0	0
T13	1597	18	0	0
T14	810	5	0	0
T15	38682	162	0	0
T16	13584	14	0	0
T17	6237	41	0	0
T18	567982	2670	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319494823	319371535	0	0
T1	495508	495503	0	0
T2	4437	4378	0	0
T3	9288	9199	0	0
T4	49163	49104	0	0
T13	1597	1587	0	0
T14	810	760	0	0
T15	38682	38639	0	0
T16	13584	13544	0	0
T17	6237	6194	0	0
T18	567982	567917	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0