Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1714793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268796

1

T1

370

T2

153

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	674131	1			T1	909		T2	424		T3	57
values[0x0]	637718	1			T1	901		T2	384		T3	43
values[0x1]	671740	1			T1	889		T2	394		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1327751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

655838

1

T1

851

T2

378

T3

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7466	1			T1	29		T2	3		T20	13
valid_sources[0x01]	7171	1			T1	5		T2	5		T4	1
valid_sources[0x02]	7003	1			T1	27		T2	3		T3	1
valid_sources[0x03]	7870	1			T2	3		T20	7		T5	6
valid_sources[0x04]	7707	1			T1	15		T2	12		T20	2
valid_sources[0x05]	7415	1			T1	25		T2	4		T3	1
valid_sources[0x06]	7193	1			T1	5		T2	2		T4	2
valid_sources[0x07]	7717	1			T1	4		T2	9		T4	1
valid_sources[0x08]	7041	1			T1	15		T2	4		T4	2
valid_sources[0x09]	7403	1			T1	16		T2	5		T3	1
valid_sources[0x0a]	7765	1			T1	3		T2	9		T3	1
valid_sources[0x0b]	8277	1			T1	6		T2	14		T4	3
valid_sources[0x0c]	7701	1			T1	5		T2	13		T20	7
valid_sources[0x0d]	6938	1			T1	6		T2	3		T3	1
valid_sources[0x0e]	7155	1			T1	10		T2	5		T3	1
valid_sources[0x0f]	8556	1			T1	4		T2	2		T20	8
valid_sources[0x10]	8484	1			T1	9		T2	1		T20	6
valid_sources[0x11]	8152	1			T1	7		T3	1		T20	3
valid_sources[0x12]	7555	1			T1	17		T2	2		T20	8
valid_sources[0x13]	7523	1			T3	1		T20	10		T5	10
valid_sources[0x14]	8123	1			T1	19		T2	7		T3	1
valid_sources[0x15]	6692	1			T2	5		T20	4		T5	5
valid_sources[0x16]	7335	1			T2	5		T20	8		T5	7
valid_sources[0x17]	8610	1			T2	8		T3	1		T20	9
valid_sources[0x18]	7760	1			T1	19		T2	3		T3	2
valid_sources[0x19]	7863	1			T1	20		T2	3		T3	1
valid_sources[0x1a]	7988	1			T1	18		T2	6		T3	1
valid_sources[0x1b]	7356	1			T1	10		T2	14		T3	2
valid_sources[0x1c]	7593	1			T1	6		T2	8		T3	1
valid_sources[0x1d]	7085	1			T2	1		T20	10		T5	7
valid_sources[0x1e]	7380	1			T1	3		T2	6		T20	5
valid_sources[0x1f]	7264	1			T1	7		T2	7		T3	2
valid_sources[0x20]	7629	1			T1	12		T2	2		T3	1
valid_sources[0x21]	7073	1			T1	3		T2	8		T20	7
valid_sources[0x22]	7479	1			T1	11		T2	3		T20	8
valid_sources[0x23]	7185	1			T1	13		T2	3		T4	2
valid_sources[0x24]	7533	1			T1	31		T2	4		T3	1
valid_sources[0x25]	8066	1			T1	7		T2	4		T3	1
valid_sources[0x26]	7957	1			T1	8		T2	5		T20	8
valid_sources[0x27]	7218	1			T1	12		T2	8		T3	1
valid_sources[0x28]	7970	1			T1	31		T2	9		T20	16
valid_sources[0x29]	7436	1			T1	1		T2	7		T3	2
valid_sources[0x2a]	7601	1			T2	10		T20	13		T5	1
valid_sources[0x2b]	7843	1			T1	19		T2	8		T20	14
valid_sources[0x2c]	8282	1			T1	23		T2	6		T4	1
valid_sources[0x2d]	8353	1			T1	1		T2	4		T3	2
valid_sources[0x2e]	7907	1			T1	26		T2	7		T20	6
valid_sources[0x2f]	7222	1			T1	44		T2	8		T20	8
valid_sources[0x30]	7776	1			T1	26		T2	3		T4	1
valid_sources[0x31]	7259	1			T1	13		T2	9		T3	1
valid_sources[0x32]	6863	1			T2	5		T20	7		T5	3
valid_sources[0x33]	7820	1			T1	9		T2	4		T3	2
valid_sources[0x34]	7453	1			T1	8		T2	6		T20	7
valid_sources[0x35]	8887	1			T2	2		T20	10		T5	6
valid_sources[0x36]	8827	1			T1	17		T2	3		T4	1
valid_sources[0x37]	8623	1			T2	1		T20	5		T5	1
valid_sources[0x38]	8788	1			T1	1		T2	1		T4	5
valid_sources[0x39]	7267	1			T1	2		T2	2		T4	1
valid_sources[0x3a]	8070	1			T1	8		T2	2		T20	7
valid_sources[0x3b]	8109	1			T1	9		T2	1		T20	7
valid_sources[0x3c]	7926	1			T1	17		T2	3		T20	14
valid_sources[0x3d]	7431	1			T1	4		T2	3		T3	2
valid_sources[0x3e]	7835	1			T1	6		T2	5		T3	1
valid_sources[0x3f]	9673	1			T1	17		T2	5		T3	1
valid_sources[0x40]	7272	1			T1	8		T20	9		T5	2
valid_sources[0x41]	7379	1			T1	35		T2	4		T3	2
valid_sources[0x42]	7898	1			T1	8		T2	2		T20	8
valid_sources[0x43]	7458	1			T1	10		T2	6		T3	2
valid_sources[0x44]	7339	1			T1	9		T2	10		T20	13
valid_sources[0x45]	7707	1			T1	10		T2	4		T20	13
valid_sources[0x46]	7983	1			T1	21		T20	11		T5	7
valid_sources[0x47]	7976	1			T1	11		T2	1		T3	2
valid_sources[0x48]	7324	1			T1	24		T2	5		T3	1
valid_sources[0x49]	7122	1			T1	13		T2	4		T4	2
valid_sources[0x4a]	8103	1			T1	10		T2	3		T4	2
valid_sources[0x4b]	8270	1			T1	9		T2	1		T3	1
valid_sources[0x4c]	8487	1			T1	3		T2	8		T3	1
valid_sources[0x4d]	7464	1			T2	5		T20	11		T5	2
valid_sources[0x4e]	8121	1			T1	34		T2	5		T20	10
valid_sources[0x4f]	7366	1			T1	1		T2	4		T20	10
valid_sources[0x50]	7966	1			T1	11		T2	1		T3	2
valid_sources[0x51]	7400	1			T2	3		T3	1		T4	9
valid_sources[0x52]	7472	1			T1	12		T2	10		T3	2
valid_sources[0x53]	7492	1			T2	4		T4	2		T20	18
valid_sources[0x54]	8119	1			T2	2		T3	1		T20	12
valid_sources[0x55]	8354	1			T1	20		T2	4		T3	1
valid_sources[0x56]	7551	1			T1	1		T2	6		T20	7
valid_sources[0x57]	7575	1			T1	13		T2	4		T3	1
valid_sources[0x58]	7041	1			T1	15		T2	5		T4	2
valid_sources[0x59]	8209	1			T1	18		T2	8		T20	8
valid_sources[0x5a]	7247	1			T1	8		T2	5		T20	2
valid_sources[0x5b]	7185	1			T1	9		T2	3		T20	14
valid_sources[0x5c]	7452	1			T1	18		T2	4		T4	5
valid_sources[0x5d]	8778	1			T1	12		T2	1		T20	10
valid_sources[0x5e]	7980	1			T1	7		T2	3		T3	2
valid_sources[0x5f]	7698	1			T1	8		T2	3		T3	1
valid_sources[0x60]	7667	1			T1	15		T2	8		T20	9
valid_sources[0x61]	7407	1			T1	1		T2	2		T20	5
valid_sources[0x62]	8838	1			T1	15		T2	4		T20	13
valid_sources[0x63]	8162	1			T1	5		T4	4		T20	8
valid_sources[0x64]	7714	1			T1	6		T2	4		T20	6
valid_sources[0x65]	7313	1			T1	7		T2	2		T20	4
valid_sources[0x66]	7438	1			T1	3		T2	5		T3	2
valid_sources[0x67]	8046	1			T1	23		T2	2		T3	1
valid_sources[0x68]	8882	1			T2	4		T20	13		T5	4
valid_sources[0x69]	7699	1			T1	20		T2	6		T20	10
valid_sources[0x6a]	6733	1			T1	12		T2	3		T20	6
valid_sources[0x6b]	7806	1			T1	1		T2	8		T3	1
valid_sources[0x6c]	7651	1			T1	15		T2	4		T3	1
valid_sources[0x6d]	7935	1			T1	6		T2	6		T20	9
valid_sources[0x6e]	8041	1			T1	21		T2	4		T20	7
valid_sources[0x6f]	7877	1			T1	11		T2	3		T3	2
valid_sources[0x70]	8366	1			T1	3		T2	5		T20	8
valid_sources[0x71]	8327	1			T1	33		T2	6		T20	10
valid_sources[0x72]	7385	1			T1	16		T2	3		T3	1
valid_sources[0x73]	7678	1			T1	3		T2	4		T20	10
valid_sources[0x74]	7603	1			T1	17		T2	5		T20	7
valid_sources[0x75]	7630	1			T2	3		T20	8		T5	3
valid_sources[0x76]	7571	1			T1	4		T2	6		T4	3
valid_sources[0x77]	7588	1			T1	14		T2	8		T4	1
valid_sources[0x78]	7874	1			T1	11		T2	2		T20	12
valid_sources[0x79]	8722	1			T1	23		T20	9		T5	6
valid_sources[0x7a]	7669	1			T1	1		T2	3		T4	1
valid_sources[0x7b]	7660	1			T1	6		T2	2		T3	2
valid_sources[0x7c]	8627	1			T1	13		T2	2		T4	1
valid_sources[0x7d]	8992	1			T1	47		T2	10		T4	2
valid_sources[0x7e]	6950	1			T1	5		T2	3		T4	3
valid_sources[0x7f]	8523	1			T1	3		T2	8		T4	1
valid_sources[0x80]	7760	1			T1	5		T2	11		T20	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28851

1

T1

38

T2

14

T3

4

values[0x0]

all_enables

biggest_size

211248

1

T1

300

T2

126

T3

11

values[0x1]

all_enables

biggest_size

28697

1

T1

32

T2

13

T3

4