Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	340839635	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	340839635	0	0
T1	997260	62684	0	0
T2	119056	4499	0	0
T3	31304	724	0	0
T4	4166344	73539	0	0
T5	2844520	133611	0	0
T17	0	10775	0	0
T19	235480	8848	0	0
T20	246680	10661	0	0
T21	4784416	110273	0	0
T22	72576	4772	0	0
T23	44016	725	0	0
T24	6923448	85015	0	0
T25	0	24803	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2792328	2787624	0	0
T2	119056	118496	0	0
T3	31304	29736	0	0
T4	4166344	4162816	0	0
T5	2844520	2830128	0	0
T19	235480	234192	0	0
T20	246680	244608	0	0
T21	4784416	4782960	0	0
T22	72576	71848	0	0
T23	44016	39872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2792328	2787624	0	0
T2	119056	118496	0	0
T3	31304	29736	0	0
T4	4166344	4162816	0	0
T5	2844520	2830128	0	0
T19	235480	234192	0	0
T20	246680	244608	0	0
T21	4784416	4782960	0	0
T22	72576	71848	0	0
T23	44016	39872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2792328	2787624	0	0
T2	119056	118496	0	0
T3	31304	29736	0	0
T4	4166344	4162816	0	0
T5	2844520	2830128	0	0
T19	235480	234192	0	0
T20	246680	244608	0	0
T21	4784416	4782960	0	0
T22	72576	71848	0	0
T23	44016	39872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	124849777	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	124849777	0	0
T1	49863	21294	0	0
T2	2126	2047	0	0
T3	559	280	0	0
T4	74399	72170	0	0
T5	50795	49637	0	0
T19	4205	3583	0	0
T20	4405	4144	0	0
T21	85436	45199	0	0
T22	1296	1193	0	0
T23	786	281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	88394411	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	88394411	0	0
T1	49863	10049	0	0
T2	2126	1202	0	0
T3	559	148	0	0
T4	74399	360	0	0
T5	50795	29680	0	0
T19	4205	2041	0	0
T20	4405	2173	0	0
T21	85436	21690	0	0
T22	1296	1193	0	0
T23	786	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1514419	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1514419	0	0
T1	49863	4181	0	0
T2	2126	24	0	0
T3	559	3	0	0
T4	74399	49	0	0
T5	50795	1074	0	0
T19	4205	61	0	0
T20	4405	89	0	0
T21	85436	599	0	0
T22	1296	252	0	0
T23	786	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3721898	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3721898	0	0
T1	49863	1798	0	0
T2	2126	24	0	0
T3	559	3	0	0
T4	74399	9	0	0
T5	50795	1074	0	0
T19	4205	61	0	0
T20	4405	89	0	0
T21	85436	714	0	0
T22	1296	252	0	0
T23	786	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1468294	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1468294	0	0
T2	2126	22	0	0
T3	559	4	0	0
T4	74399	6	0	0
T5	50795	1103	0	0
T17	0	424	0	0
T19	4205	57	0	0
T20	4405	78	0	0
T21	85436	1054	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	3120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3499640	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3499640	0	0
T2	2126	22	0	0
T3	559	4	0	0
T4	74399	4	0	0
T5	50795	1102	0	0
T17	0	261	0	0
T19	4205	57	0	0
T20	4405	78	0	0
T21	85436	1042	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	2552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1491407	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1491407	0	0
T2	2126	19	0	0
T3	559	5	0	0
T4	74399	43	0	0
T5	50795	826	0	0
T17	0	416	0	0
T19	4205	64	0	0
T20	4405	70	0	0
T21	85436	778	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	3210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2623817	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2623817	0	0
T2	2126	19	0	0
T3	559	5	0	0
T4	74399	8	0	0
T5	50795	825	0	0
T17	0	345	0	0
T19	4205	64	0	0
T20	4405	70	0	0
T21	85436	676	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	1543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1486302	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1486302	0	0
T2	2126	25	0	0
T3	559	6	0	0
T4	74399	11	0	0
T5	50795	1448	0	0
T17	0	476	0	0
T19	4205	61	0	0
T20	4405	84	0	0
T21	85436	819	0	0
T22	1296	0	0	0
T23	786	1	0	0
T24	192318	0	0	0
T25	0	11472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3302431	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3302431	0	0
T2	2126	25	0	0
T3	559	6	0	0
T4	74399	4	0	0
T5	50795	1448	0	0
T17	0	351	0	0
T19	4205	61	0	0
T20	4405	84	0	0
T21	85436	716	0	0
T22	1296	0	0	0
T23	786	1	0	0
T24	192318	0	0	0
T25	0	13331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1520985	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1520985	0	0
T2	2126	27	0	0
T3	559	9	0	0
T4	74399	23	0	0
T5	50795	1072	0	0
T17	0	450	0	0
T19	4205	54	0	0
T20	4405	82	0	0
T21	85436	664	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	3982	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3028009	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3028009	0	0
T2	2126	27	0	0
T3	559	9	0	0
T4	74399	5	0	0
T5	50795	1072	0	0
T17	0	391	0	0
T19	4205	54	0	0
T20	4405	82	0	0
T21	85436	766	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1496418	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1496418	0	0
T2	2126	23	0	0
T3	559	2	0	0
T4	74399	26	0	0
T5	50795	606	0	0
T17	0	432	0	0
T19	4205	55	0	0
T20	4405	67	0	0
T21	85436	806	0	0
T22	1296	0	0	0
T23	786	9	0	0
T24	192318	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3342192	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3342192	0	0
T2	2126	23	0	0
T3	559	2	0	0
T4	74399	4	0	0
T5	50795	606	0	0
T17	0	388	0	0
T19	4205	55	0	0
T20	4405	67	0	0
T21	85436	929	0	0
T22	1296	0	0	0
T23	786	9	0	0
T24	192318	418	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1463056	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1463056	0	0
T1	49863	3952	0	0
T2	2126	27	0	0
T3	559	5	0	0
T4	74399	10	0	0
T5	50795	609	0	0
T19	4205	50	0	0
T20	4405	66	0	0
T21	85436	810	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	0	4088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3075676	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3075676	0	0
T1	49863	1960	0	0
T2	2126	27	0	0
T3	559	5	0	0
T4	74399	3	0	0
T5	50795	609	0	0
T19	4205	50	0	0
T20	4405	66	0	0
T21	85436	762	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	0	722	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1475118	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1475118	0	0
T2	2126	15	0	0
T3	559	3	0	0
T4	74399	28	0	0
T5	50795	794	0	0
T17	0	357	0	0
T19	4205	60	0	0
T20	4405	95	0	0
T21	85436	820	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	192318	1862	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2453662	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2453662	0	0
T2	2126	15	0	0
T3	559	3	0	0
T4	74399	7	0	0
T5	50795	794	0	0
T17	0	185	0	0
T19	4205	60	0	0
T20	4405	95	0	0
T21	85436	899	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	192318	933	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1481642	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1481642	0	0
T1	49863	2094	0	0
T2	2126	27	0	0
T3	559	6	0	0
T4	74399	36	0	0
T5	50795	911	0	0
T19	4205	63	0	0
T20	4405	85	0	0
T21	85436	933	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	0	2692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3172963	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3172963	0	0
T1	49863	839	0	0
T2	2126	27	0	0
T3	559	6	0	0
T4	74399	7	0	0
T5	50795	911	0	0
T19	4205	63	0	0
T20	4405	85	0	0
T21	85436	946	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	0	990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1494515	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1494515	0	0
T2	2126	25	0	0
T3	559	3	0	0
T4	74399	26	0	0
T5	50795	732	0	0
T17	0	459	0	0
T19	4205	61	0	0
T20	4405	75	0	0
T21	85436	685	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	1557	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3166192	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3166192	0	0
T2	2126	25	0	0
T3	559	3	0	0
T4	74399	7	0	0
T5	50795	732	0	0
T17	0	394	0	0
T19	4205	61	0	0
T20	4405	75	0	0
T21	85436	705	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	1523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1493371	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1493371	0	0
T2	2126	24	0	0
T3	559	6	0	0
T4	74399	23	0	0
T5	50795	1351	0	0
T17	0	449	0	0
T19	4205	76	0	0
T20	4405	96	0	0
T21	85436	759	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	2481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2694282	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2694282	0	0
T2	2126	24	0	0
T3	559	6	0	0
T4	74399	4	0	0
T5	50795	1351	0	0
T17	0	368	0	0
T19	4205	76	0	0
T20	4405	96	0	0
T21	85436	852	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	192318	1364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1461385	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1461385	0	0
T2	2126	22	0	0
T3	559	9	0	0
T4	74399	25	0	0
T5	50795	879	0	0
T17	0	425	0	0
T19	4205	69	0	0
T20	4405	77	0	0
T21	85436	800	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	192318	2927	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3081725	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3081725	0	0
T2	2126	22	0	0
T3	559	9	0	0
T4	74399	231	0	0
T5	50795	879	0	0
T17	0	314	0	0
T19	4205	69	0	0
T20	4405	77	0	0
T21	85436	826	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	192318	1028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1484592	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1484592	0	0
T2	2126	22	0	0
T3	559	7	0	0
T4	74399	21	0	0
T5	50795	1129	0	0
T17	0	537	0	0
T19	4205	73	0	0
T20	4405	77	0	0
T21	85436	804	0	0
T22	1296	0	0	0
T23	786	7	0	0
T24	192318	1509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2841508	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2841508	0	0
T2	2126	22	0	0
T3	559	7	0	0
T4	74399	4	0	0
T5	50795	1129	0	0
T17	0	388	0	0
T19	4205	73	0	0
T20	4405	77	0	0
T21	85436	757	0	0
T22	1296	0	0	0
T23	786	7	0	0
T24	192318	824	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1509607	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1509607	0	0
T2	2126	30	0	0
T3	559	3	0	0
T4	74399	29	0	0
T5	50795	1159	0	0
T17	0	372	0	0
T19	4205	58	0	0
T20	4405	90	0	0
T21	85436	762	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	192318	562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3029827	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3029827	0	0
T2	2126	30	0	0
T3	559	3	0	0
T4	74399	4	0	0
T5	50795	1158	0	0
T17	0	276	0	0
T19	4205	58	0	0
T20	4405	90	0	0
T21	85436	684	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	192318	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1503058	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1503058	0	0
T2	2126	15	0	0
T3	559	5	0	0
T4	74399	13	0	0
T5	50795	919	0	0
T19	4205	56	0	0
T20	4405	79	0	0
T21	85436	843	0	0
T22	1296	251	0	0
T23	786	8	0	0
T24	192318	2016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3635028	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3635028	0	0
T2	2126	15	0	0
T3	559	5	0	0
T4	74399	3	0	0
T5	50795	919	0	0
T19	4205	56	0	0
T20	4405	79	0	0
T21	85436	772	0	0
T22	1296	251	0	0
T23	786	8	0	0
T24	192318	976	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1469061	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1469061	0	0
T2	2126	27	0	0
T3	559	3	0	0
T4	74399	27	0	0
T5	50795	1165	0	0
T19	4205	58	0	0
T20	4405	89	0	0
T21	85436	720	0	0
T22	1296	203	0	0
T23	786	1	0	0
T24	192318	1725	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2637630	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2637630	0	0
T2	2126	27	0	0
T3	559	3	0	0
T4	74399	5	0	0
T5	50795	1165	0	0
T19	4205	58	0	0
T20	4405	89	0	0
T21	85436	829	0	0
T22	1296	203	0	0
T23	786	1	0	0
T24	192318	742	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1512181	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1512181	0	0
T2	2126	23	0	0
T3	559	7	0	0
T4	74399	14	0	0
T5	50795	846	0	0
T17	0	329	0	0
T19	4205	56	0	0
T20	4405	87	0	0
T21	85436	923	0	0
T22	1296	0	0	0
T23	786	9	0	0
T24	192318	2856	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3118692	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3118692	0	0
T2	2126	23	0	0
T3	559	7	0	0
T4	74399	4	0	0
T5	50795	846	0	0
T17	0	228	0	0
T19	4205	56	0	0
T20	4405	87	0	0
T21	85436	846	0	0
T22	1296	0	0	0
T23	786	9	0	0
T24	192318	758	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1524400	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1524400	0	0
T1	49863	1718	0	0
T2	2126	10	0	0
T3	559	5	0	0
T4	74399	28	0	0
T5	50795	1715	0	0
T19	4205	61	0	0
T20	4405	75	0	0
T21	85436	929	0	0
T22	1296	0	0	0
T23	786	7	0	0
T24	0	3228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3448856	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3448856	0	0
T1	49863	826	0	0
T2	2126	10	0	0
T3	559	5	0	0
T4	74399	6	0	0
T5	50795	1715	0	0
T19	4205	61	0	0
T20	4405	75	0	0
T21	85436	842	0	0
T22	1296	0	0	0
T23	786	7	0	0
T24	0	649	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1491393	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1491393	0	0
T1	49863	1218	0	0
T2	2126	30	0	0
T3	559	7	0	0
T4	74399	22	0	0
T5	50795	1105	0	0
T19	4205	56	0	0
T20	4405	82	0	0
T21	85436	881	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	0	3687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3534138	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3534138	0	0
T1	49863	1068	0	0
T2	2126	30	0	0
T3	559	7	0	0
T4	74399	6	0	0
T5	50795	1105	0	0
T19	4205	56	0	0
T20	4405	82	0	0
T21	85436	700	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	0	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1495014	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1495014	0	0
T1	49863	2253	0	0
T2	2126	22	0	0
T3	559	7	0	0
T4	74399	15	0	0
T5	50795	1152	0	0
T19	4205	68	0	0
T20	4405	96	0	0
T21	85436	711	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	0	2367	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3825271	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3825271	0	0
T1	49863	928	0	0
T2	2126	22	0	0
T3	559	7	0	0
T4	74399	3	0	0
T5	50795	1152	0	0
T19	4205	68	0	0
T20	4405	96	0	0
T21	85436	637	0	0
T22	1296	0	0	0
T23	786	3	0	0
T24	0	717	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1504547	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1504547	0	0
T1	49863	1791	0	0
T2	2126	24	0	0
T3	559	8	0	0
T4	74399	11	0	0
T5	50795	843	0	0
T19	4205	59	0	0
T20	4405	80	0	0
T21	85436	844	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	0	1252	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3312345	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3312345	0	0
T1	49863	879	0	0
T2	2126	24	0	0
T3	559	8	0	0
T4	74399	2	0	0
T5	50795	842	0	0
T19	4205	59	0	0
T20	4405	80	0	0
T21	85436	776	0	0
T22	1296	0	0	0
T23	786	6	0	0
T24	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1532565	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1532565	0	0
T2	2126	33	0	0
T3	559	7	0	0
T4	74399	11	0	0
T5	50795	1159	0	0
T17	0	320	0	0
T19	4205	64	0	0
T20	4405	67	0	0
T21	85436	656	0	0
T22	1296	0	0	0
T23	786	8	0	0
T24	192318	2599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3318421	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3318421	0	0
T2	2126	33	0	0
T3	559	7	0	0
T4	74399	2	0	0
T5	50795	1159	0	0
T17	0	313	0	0
T19	4205	64	0	0
T20	4405	67	0	0
T21	85436	657	0	0
T22	1296	0	0	0
T23	786	8	0	0
T24	192318	1677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1465799	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1465799	0	0
T1	49863	2304	0	0
T2	2126	23	0	0
T3	559	8	0	0
T4	74399	14	0	0
T5	50795	590	0	0
T19	4205	51	0	0
T20	4405	87	0	0
T21	85436	835	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	0	3227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	2999434	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	2999434	0	0
T1	49863	1032	0	0
T2	2126	23	0	0
T3	559	8	0	0
T4	74399	3	0	0
T5	50795	590	0	0
T19	4205	51	0	0
T20	4405	87	0	0
T21	85436	711	0	0
T22	1296	0	0	0
T23	786	4	0	0
T24	0	1021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1493819	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1493819	0	0
T2	2126	23	0	0
T3	559	8	0	0
T4	74399	20	0	0
T5	50795	1410	0	0
T19	4205	59	0	0
T20	4405	72	0	0
T21	85436	800	0	0
T22	1296	235	0	0
T23	786	9	0	0
T24	192318	1214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3884609	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3884609	0	0
T2	2126	23	0	0
T3	559	8	0	0
T4	74399	4	0	0
T5	50795	1410	0	0
T19	4205	59	0	0
T20	4405	72	0	0
T21	85436	815	0	0
T22	1296	235	0	0
T23	786	9	0	0
T24	192318	1299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1496840	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1496840	0	0
T1	49863	1782	0	0
T2	2126	21	0	0
T3	559	3	0	0
T4	74399	55	0	0
T5	50795	1114	0	0
T19	4205	52	0	0
T20	4405	79	0	0
T21	85436	803	0	0
T22	1296	252	0	0
T23	786	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3209015	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3209015	0	0
T1	49863	718	0	0
T2	2126	21	0	0
T3	559	3	0	0
T4	74399	9	0	0
T5	50795	1114	0	0
T19	4205	52	0	0
T20	4405	79	0	0
T21	85436	835	0	0
T22	1296	252	0	0
T23	786	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1482763	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1482763	0	0
T2	2126	24	0	0
T3	559	2	0	0
T4	74399	16	0	0
T5	50795	848	0	0
T17	0	315	0	0
T19	4205	64	0	0
T20	4405	69	0	0
T21	85436	870	0	0
T22	1296	0	0	0
T23	786	10	0	0
T24	192318	2885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3367402	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3367402	0	0
T2	2126	24	0	0
T3	559	2	0	0
T4	74399	4	0	0
T5	50795	848	0	0
T17	0	279	0	0
T19	4205	64	0	0
T20	4405	69	0	0
T21	85436	991	0	0
T22	1296	0	0	0
T23	786	10	0	0
T24	192318	2212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	1526449	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	1526449	0	0
T2	2126	18	0	0
T3	559	7	0	0
T4	74399	47	0	0
T5	50795	590	0	0
T17	0	278	0	0
T19	4205	46	0	0
T20	4405	79	0	0
T21	85436	801	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	4196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310302530	3931784	0	0
DepthKnown_A	310302530	310167585	0	0
RvalidKnown_A	310302530	310167585	0	0
WreadyKnown_A	310302530	310167585	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	3931784	0	0
T2	2126	18	0	0
T3	559	7	0	0
T4	74399	8	0	0
T5	50795	590	0	0
T17	0	255	0	0
T19	4205	46	0	0
T20	4405	79	0	0
T21	85436	990	0	0
T22	1296	0	0	0
T23	786	5	0	0
T24	192318	1865	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310302530	310167585	0	0
T1	49863	49779	0	0
T2	2126	2116	0	0
T3	559	531	0	0
T4	74399	74336	0	0
T5	50795	50538	0	0
T19	4205	4182	0	0
T20	4405	4368	0	0
T21	85436	85410	0	0
T22	1296	1283	0	0
T23	786	712	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0