Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1776024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

278414

1

T1

364

T2

22

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	696335	1			T1	830		T2	46		T3	34
values[0x0]	661948	1			T1	841		T2	50		T3	33
values[0x1]	696155	1			T1	803		T2	45		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1376246	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

678192

1

T1

826

T2

52

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7328	1			T4	13		T15	1		T16	102
valid_sources[0x01]	7207	1			T2	1		T4	5		T16	90
valid_sources[0x02]	8216	1			T2	1		T4	2		T13	2
valid_sources[0x03]	8225	1			T4	4		T15	1		T13	1
valid_sources[0x04]	8122	1			T4	12		T13	2		T16	138
valid_sources[0x05]	7884	1			T5	2		T4	10		T13	1
valid_sources[0x06]	7704	1			T1	45		T4	11		T16	104
valid_sources[0x07]	7512	1			T15	1		T13	1		T16	113
valid_sources[0x08]	9446	1			T2	1		T4	8		T15	1
valid_sources[0x09]	9278	1			T4	5		T13	2		T16	80
valid_sources[0x0a]	8042	1			T3	1		T4	30		T13	1
valid_sources[0x0b]	8480	1			T3	2		T4	9		T16	65
valid_sources[0x0c]	7802	1			T4	14		T16	61		T17	24
valid_sources[0x0d]	7757	1			T3	1		T4	6		T16	104
valid_sources[0x0e]	8444	1			T1	58		T2	1		T4	3
valid_sources[0x0f]	9525	1			T1	94		T5	2		T4	16
valid_sources[0x10]	7678	1			T2	2		T4	27		T13	2
valid_sources[0x11]	6745	1			T3	2		T4	12		T16	114
valid_sources[0x12]	8507	1			T5	4		T4	15		T16	83
valid_sources[0x13]	8175	1			T2	1		T4	10		T16	63
valid_sources[0x14]	7685	1			T5	1		T4	6		T16	89
valid_sources[0x15]	7872	1			T2	1		T3	1		T5	3
valid_sources[0x16]	8252	1			T1	9		T4	4		T15	1
valid_sources[0x17]	7199	1			T3	1		T4	5		T16	80
valid_sources[0x18]	8110	1			T3	1		T4	12		T15	3
valid_sources[0x19]	9617	1			T4	27		T16	68		T17	20
valid_sources[0x1a]	7956	1			T3	1		T4	14		T13	2
valid_sources[0x1b]	7695	1			T3	1		T4	15		T15	2
valid_sources[0x1c]	7834	1			T2	1		T3	1		T4	16
valid_sources[0x1d]	9373	1			T2	3		T4	4		T15	1
valid_sources[0x1e]	7329	1			T4	9		T16	63		T17	28
valid_sources[0x1f]	7697	1			T4	3		T16	135		T17	16
valid_sources[0x20]	8018	1			T2	1		T5	4		T4	10
valid_sources[0x21]	8169	1			T4	8		T15	4		T16	50
valid_sources[0x22]	8030	1			T4	11		T13	1		T16	103
valid_sources[0x23]	7374	1			T1	99		T4	6		T13	1
valid_sources[0x24]	7817	1			T4	1		T15	3		T16	108
valid_sources[0x25]	7646	1			T2	1		T3	1		T4	11
valid_sources[0x26]	8530	1			T2	1		T5	1		T4	13
valid_sources[0x27]	7427	1			T4	11		T15	2		T16	105
valid_sources[0x28]	8210	1			T4	10		T15	1		T16	154
valid_sources[0x29]	7889	1			T1	13		T2	1		T5	2
valid_sources[0x2a]	7818	1			T2	2		T4	3		T16	90
valid_sources[0x2b]	8094	1			T2	2		T4	20		T15	3
valid_sources[0x2c]	7572	1			T2	1		T4	2		T13	1
valid_sources[0x2d]	7696	1			T2	2		T5	1		T4	2
valid_sources[0x2e]	7211	1			T5	1		T4	17		T16	78
valid_sources[0x2f]	7681	1			T1	90		T4	2		T16	67
valid_sources[0x30]	8165	1			T4	8		T15	1		T13	1
valid_sources[0x31]	7574	1			T4	5		T16	84		T17	16
valid_sources[0x32]	7724	1			T1	214		T4	10		T16	77
valid_sources[0x33]	7604	1			T3	1		T4	6		T16	76
valid_sources[0x34]	6745	1			T4	2		T13	1		T16	99
valid_sources[0x35]	7164	1			T2	1		T4	7		T13	2
valid_sources[0x36]	8670	1			T4	16		T16	131		T17	10
valid_sources[0x37]	8302	1			T4	18		T16	88		T17	32
valid_sources[0x38]	9237	1			T3	1		T4	15		T16	56
valid_sources[0x39]	7420	1			T1	14		T2	1		T5	2
valid_sources[0x3a]	7894	1			T2	1		T5	1		T4	11
valid_sources[0x3b]	7116	1			T4	3		T16	93		T17	47
valid_sources[0x3c]	8887	1			T3	1		T4	11		T15	1
valid_sources[0x3d]	7427	1			T2	4		T5	3		T4	12
valid_sources[0x3e]	8236	1			T1	88		T4	26		T15	3
valid_sources[0x3f]	7373	1			T2	2		T5	2		T4	6
valid_sources[0x40]	9229	1			T2	2		T4	10		T16	82
valid_sources[0x41]	8194	1			T2	1		T3	1		T4	5
valid_sources[0x42]	10308	1			T2	3		T4	6		T16	108
valid_sources[0x43]	7835	1			T4	15		T16	70		T17	7
valid_sources[0x44]	9190	1			T2	1		T4	3		T13	1
valid_sources[0x45]	7882	1			T1	8		T2	1		T3	1
valid_sources[0x46]	7763	1			T2	1		T3	1		T4	7
valid_sources[0x47]	7257	1			T3	2		T4	5		T16	72
valid_sources[0x48]	7926	1			T3	1		T4	1		T15	1
valid_sources[0x49]	7815	1			T2	2		T3	1		T4	4
valid_sources[0x4a]	7730	1			T3	1		T16	109		T17	15
valid_sources[0x4b]	7326	1			T1	59		T3	1		T5	2
valid_sources[0x4c]	7256	1			T3	1		T5	2		T4	5
valid_sources[0x4d]	7272	1			T5	11		T4	4		T15	3
valid_sources[0x4e]	8039	1			T1	28		T4	4		T13	2
valid_sources[0x4f]	7777	1			T4	4		T16	63		T17	27
valid_sources[0x50]	7518	1			T4	5		T16	65		T17	57
valid_sources[0x51]	8372	1			T2	1		T4	7		T13	5
valid_sources[0x52]	8116	1			T3	1		T5	1		T4	13
valid_sources[0x53]	7324	1			T3	1		T4	3		T16	50
valid_sources[0x54]	7769	1			T5	2		T4	10		T16	81
valid_sources[0x55]	7719	1			T2	1		T3	1		T4	5
valid_sources[0x56]	7767	1			T2	1		T4	18		T13	1
valid_sources[0x57]	8248	1			T4	17		T16	87		T17	31
valid_sources[0x58]	8745	1			T4	10		T16	71		T17	6
valid_sources[0x59]	8241	1			T1	18		T4	21		T16	57
valid_sources[0x5a]	8685	1			T2	1		T3	1		T4	13
valid_sources[0x5b]	8728	1			T4	15		T16	87		T17	52
valid_sources[0x5c]	8899	1			T2	1		T3	1		T4	6
valid_sources[0x5d]	8485	1			T2	1		T16	68		T17	34
valid_sources[0x5e]	7572	1			T2	1		T5	1		T4	7
valid_sources[0x5f]	9365	1			T3	1		T4	14		T16	85
valid_sources[0x60]	7285	1			T3	1		T5	1		T4	9
valid_sources[0x61]	7006	1			T5	1		T4	12		T13	1
valid_sources[0x62]	7739	1			T4	5		T16	87		T17	20
valid_sources[0x63]	8658	1			T4	10		T16	90		T17	27
valid_sources[0x64]	7517	1			T2	1		T4	13		T16	112
valid_sources[0x65]	7381	1			T1	8		T4	25		T15	2
valid_sources[0x66]	7226	1			T1	75		T2	2		T5	6
valid_sources[0x67]	7335	1			T4	15		T16	77		T17	19
valid_sources[0x68]	8380	1			T4	16		T16	63		T17	15
valid_sources[0x69]	7620	1			T2	1		T3	1		T4	5
valid_sources[0x6a]	7968	1			T3	1		T4	11		T13	1
valid_sources[0x6b]	8571	1			T2	2		T3	1		T4	8
valid_sources[0x6c]	8026	1			T3	1		T4	3		T16	122
valid_sources[0x6d]	8011	1			T2	2		T4	4		T15	1
valid_sources[0x6e]	9246	1			T5	1		T4	13		T13	1
valid_sources[0x6f]	8011	1			T2	4		T5	9		T4	5
valid_sources[0x70]	8074	1			T4	20		T16	65		T17	23
valid_sources[0x71]	7376	1			T2	3		T3	1		T4	17
valid_sources[0x72]	7017	1			T2	2		T4	21		T16	105
valid_sources[0x73]	7608	1			T3	1		T4	14		T15	2
valid_sources[0x74]	7627	1			T4	11		T15	1		T16	74
valid_sources[0x75]	7622	1			T1	127		T2	1		T4	6
valid_sources[0x76]	7354	1			T4	8		T13	1		T16	63
valid_sources[0x77]	7597	1			T3	2		T5	3		T4	10
valid_sources[0x78]	7751	1			T3	2		T4	8		T13	1
valid_sources[0x79]	8635	1			T5	1		T4	14		T15	1
valid_sources[0x7a]	8066	1			T2	1		T4	15		T13	1
valid_sources[0x7b]	8109	1			T2	4		T3	1		T5	4
valid_sources[0x7c]	9043	1			T5	3		T4	6		T16	76
valid_sources[0x7d]	8353	1			T4	23		T16	80		T17	38
valid_sources[0x7e]	8153	1			T4	6		T16	69		T17	9
valid_sources[0x7f]	8000	1			T5	2		T4	14		T13	1
valid_sources[0x80]	7680	1			T3	2		T4	11		T16	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29661

1

T1

42

T2

1

T5

2

values[0x0]

all_enables

biggest_size

219364

1

T1

297

T2

20

T3

13

values[0x1]

all_enables

biggest_size

29389

1

T1

25

T2

1

T3

3