Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	354065951	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354065951	0	0
T1	2480632	34838	0	0
T2	6646584	218277	0	0
T3	32984	519	0	0
T4	3067008	82730	0	0
T5	26152	729	0	0
T13	3271016	57505	0	0
T14	162008	4229	0	0
T15	3048640	48848	0	0
T16	2200184	93700	0	0
T17	9641520	190254	0	0
T18	0	14033	0	0
T19	0	84742	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2480632	2478392	0	0
T2	6646584	6645688	0	0
T3	32984	29680	0	0
T4	3067008	3064936	0	0
T5	26152	24472	0	0
T13	3271016	3268944	0	0
T14	162008	161616	0	0
T15	3048640	3046512	0	0
T16	2200184	2197608	0	0
T17	9641520	9636200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2480632	2478392	0	0
T2	6646584	6645688	0	0
T3	32984	29680	0	0
T4	3067008	3064936	0	0
T5	26152	24472	0	0
T13	3271016	3268944	0	0
T14	162008	161616	0	0
T15	3048640	3046512	0	0
T16	2200184	2197608	0	0
T17	9641520	9636200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2480632	2478392	0	0
T2	6646584	6645688	0	0
T3	32984	29680	0	0
T4	3067008	3064936	0	0
T5	26152	24472	0	0
T13	3271016	3268944	0	0
T14	162008	161616	0	0
T15	3048640	3046512	0	0
T16	2200184	2197608	0	0
T17	9641520	9636200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	122436067	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	122436067	0	0
T1	44297	15664	0	0
T2	118689	116572	0	0
T3	589	204	0	0
T4	54768	19442	0	0
T5	467	285	0	0
T13	58411	56599	0	0
T14	2893	1725	0	0
T15	54440	20830	0	0
T16	39289	38989	0	0
T17	172170	81145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	96242550	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	96242550	0	0
T1	44297	5424	0	0
T2	118689	50534	0	0
T3	589	105	0	0
T4	54768	21923	0	0
T5	467	148	0	0
T13	58411	188	0	0
T14	2893	856	0	0
T15	54440	7300	0	0
T16	39289	21473	0	0
T17	172170	25918	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1497324	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1497324	0	0
T1	44297	285	0	0
T2	118689	2	0	0
T3	589	5	0	0
T4	54768	1956	0	0
T5	467	1	0	0
T13	58411	0	0	0
T14	2893	12	0	0
T15	54440	564	0	0
T16	39289	618	0	0
T17	172170	956	0	0
T18	0	421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3981450	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3981450	0	0
T1	44297	150	0	0
T2	118689	606	0	0
T3	589	5	0	0
T4	54768	1886	0	0
T5	467	1	0	0
T13	58411	0	0	0
T14	2893	17	0	0
T15	54440	216	0	0
T16	39289	618	0	0
T17	172170	391	0	0
T18	0	202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1551127	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1551127	0	0
T1	44297	418	0	0
T2	118689	9	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	8	0	0
T14	2893	30	0	0
T15	54440	678	0	0
T16	39289	400	0	0
T17	172170	924	0	0
T18	0	432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	4316001	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	4316001	0	0
T1	44297	187	0	0
T2	118689	560	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	3	0	0
T14	2893	20	0	0
T15	54440	289	0	0
T16	39289	400	0	0
T17	172170	369	0	0
T18	0	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1482281	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1482281	0	0
T1	44297	406	0	0
T2	118689	19	0	0
T3	589	5	0	0
T4	54768	1707	0	0
T5	467	6	0	0
T13	58411	3	0	0
T14	2893	30	0	0
T15	54440	485	0	0
T16	39289	416	0	0
T17	172170	1004	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	4436497	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	4436497	0	0
T1	44297	145	0	0
T2	118689	675	0	0
T3	589	5	0	0
T4	54768	1706	0	0
T5	467	6	0	0
T13	58411	1	0	0
T14	2893	27	0	0
T15	54440	220	0	0
T16	39289	416	0	0
T17	172170	443	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1503636	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1503636	0	0
T1	44297	386	0	0
T2	118689	10	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	29	0	0
T14	2893	38	0	0
T15	54440	583	0	0
T16	39289	652	0	0
T17	172170	3224	0	0
T18	0	392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3887991	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3887991	0	0
T1	44297	128	0	0
T2	118689	779	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	6	0	0
T14	2893	59	0	0
T15	54440	270	0	0
T16	39289	652	0	0
T17	172170	1243	0	0
T18	0	311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1433929	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1433929	0	0
T1	44297	328	0	0
T2	118689	13	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	10	0	0
T13	58411	15	0	0
T14	2893	35	0	0
T15	54440	470	0	0
T16	39289	397	0	0
T17	172170	1179	0	0
T18	0	474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3072516	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3072516	0	0
T1	44297	113	0	0
T2	118689	1491	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	10	0	0
T13	58411	3	0	0
T14	2893	17	0	0
T15	54440	274	0	0
T16	39289	397	0	0
T17	172170	533	0	0
T18	0	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1497281	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1497281	0	0
T1	44297	351	0	0
T2	118689	28	0	0
T3	589	2	0	0
T4	54768	0	0	0
T5	467	10	0	0
T13	58411	39	0	0
T14	2893	9	0	0
T15	54440	382	0	0
T16	39289	637	0	0
T17	172170	3130	0	0
T18	0	399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3208731	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3208731	0	0
T1	44297	140	0	0
T2	118689	1966	0	0
T3	589	2	0	0
T4	54768	0	0	0
T5	467	10	0	0
T13	58411	9	0	0
T14	2893	29	0	0
T15	54440	173	0	0
T16	39289	637	0	0
T17	172170	1165	0	0
T18	0	325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1468974	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1468974	0	0
T1	44297	314	0	0
T2	118689	8	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	11	0	0
T13	58411	31	0	0
T14	2893	33	0	0
T15	54440	560	0	0
T16	39289	377	0	0
T17	172170	4839	0	0
T18	0	315	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	2918373	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	2918373	0	0
T1	44297	149	0	0
T2	118689	1467	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	11	0	0
T13	58411	6	0	0
T14	2893	40	0	0
T15	54440	256	0	0
T16	39289	377	0	0
T17	172170	2220	0	0
T18	0	255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1488087	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1488087	0	0
T1	44297	359	0	0
T2	118689	39	0	0
T3	589	1	0	0
T4	54768	0	0	0
T5	467	7	0	0
T13	58411	12	0	0
T14	2893	30	0	0
T15	54440	448	0	0
T16	39289	668	0	0
T17	172170	3068	0	0
T18	0	419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3342361	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3342361	0	0
T1	44297	133	0	0
T2	118689	1607	0	0
T3	589	1	0	0
T4	54768	0	0	0
T5	467	7	0	0
T13	58411	3	0	0
T14	2893	54	0	0
T15	54440	254	0	0
T16	39289	668	0	0
T17	172170	1199	0	0
T18	0	299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1462845	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1462845	0	0
T1	44297	265	0	0
T2	118689	23	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	8	0	0
T14	2893	26	0	0
T15	54440	441	0	0
T16	39289	857	0	0
T17	172170	2647	0	0
T18	0	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3168709	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3168709	0	0
T1	44297	107	0	0
T2	118689	1697	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	3	0	0
T14	2893	15	0	0
T15	54440	154	0	0
T16	39289	857	0	0
T17	172170	1168	0	0
T18	0	264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1460437	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1460437	0	0
T1	44297	429	0	0
T2	118689	33	0	0
T3	589	0	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	28	0	0
T14	2893	54	0	0
T15	54440	492	0	0
T16	39289	893	0	0
T17	172170	912	0	0
T18	0	483	0	0
T19	0	1059	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	2947393	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	2947393	0	0
T1	44297	183	0	0
T2	118689	2299	0	0
T3	589	0	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	6	0	0
T14	2893	72	0	0
T15	54440	144	0	0
T16	39289	893	0	0
T17	172170	327	0	0
T18	0	286	0	0
T19	0	83683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1487867	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1487867	0	0
T1	44297	277	0	0
T2	118689	23	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	17	0	0
T14	2893	29	0	0
T15	54440	438	0	0
T16	39289	894	0	0
T17	172170	4621	0	0
T18	0	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3665336	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3665336	0	0
T1	44297	142	0	0
T2	118689	1374	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	5	0	0
T13	58411	4	0	0
T14	2893	48	0	0
T15	54440	252	0	0
T16	39289	894	0	0
T17	172170	1918	0	0
T18	0	330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1515190	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1515190	0	0
T1	44297	375	0	0
T2	118689	34	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	27	0	0
T14	2893	33	0	0
T15	54440	592	0	0
T16	39289	404	0	0
T17	172170	987	0	0
T18	0	584	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	4125077	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	4125077	0	0
T1	44297	187	0	0
T2	118689	2626	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	7	0	0
T14	2893	26	0	0
T15	54440	280	0	0
T16	39289	404	0	0
T17	172170	447	0	0
T18	0	510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1502503	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1502503	0	0
T1	44297	441	0	0
T2	118689	10	0	0
T3	589	2	0	0
T4	54768	2174	0	0
T5	467	8	0	0
T13	58411	37	0	0
T14	2893	31	0	0
T15	54440	507	0	0
T16	39289	398	0	0
T17	172170	937	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3622864	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3622864	0	0
T1	44297	163	0	0
T2	118689	449	0	0
T3	589	2	0	0
T4	54768	2214	0	0
T5	467	8	0	0
T13	58411	8	0	0
T14	2893	17	0	0
T15	54440	292	0	0
T16	39289	398	0	0
T17	172170	401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1490442	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1490442	0	0
T1	44297	444	0	0
T2	118689	33	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	2	0	0
T13	58411	16	0	0
T14	2893	32	0	0
T15	54440	546	0	0
T16	39289	392	0	0
T17	172170	3220	0	0
T18	0	503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3032554	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3032554	0	0
T1	44297	165	0	0
T2	118689	1714	0	0
T3	589	6	0	0
T4	54768	0	0	0
T5	467	2	0	0
T13	58411	3	0	0
T14	2893	18	0	0
T15	54440	339	0	0
T16	39289	392	0	0
T17	172170	1228	0	0
T18	0	337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1482724	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1482724	0	0
T1	44297	478	0	0
T2	118689	19	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	6	0	0
T13	58411	18	0	0
T14	2893	25	0	0
T15	54440	587	0	0
T16	39289	388	0	0
T17	172170	993	0	0
T18	0	497	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3740563	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3740563	0	0
T1	44297	195	0	0
T2	118689	3171	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	6	0	0
T13	58411	5	0	0
T14	2893	43	0	0
T15	54440	206	0	0
T16	39289	388	0	0
T17	172170	487	0	0
T18	0	416	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1510027	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1510027	0	0
T1	44297	390	0	0
T2	118689	32	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	11	0	0
T14	2893	53	0	0
T15	54440	550	0	0
T16	39289	617	0	0
T17	172170	2965	0	0
T18	0	509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	4372273	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	4372273	0	0
T1	44297	137	0	0
T2	118689	2768	0	0
T3	589	7	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	3	0	0
T14	2893	64	0	0
T15	54440	273	0	0
T16	39289	617	0	0
T17	172170	1163	0	0
T18	0	346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1459710	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1459710	0	0
T1	44297	448	0	0
T2	118689	10	0	0
T3	589	8	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	34	0	0
T14	2893	18	0	0
T15	54440	395	0	0
T16	39289	700	0	0
T17	172170	1062	0	0
T18	0	477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3146747	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3146747	0	0
T1	44297	194	0	0
T2	118689	854	0	0
T3	589	8	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	8	0	0
T14	2893	6	0	0
T15	54440	166	0	0
T16	39289	700	0	0
T17	172170	404	0	0
T18	0	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1475148	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1475148	0	0
T1	44297	368	0	0
T2	118689	30	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	6	0	0
T13	58411	31	0	0
T14	2893	26	0	0
T15	54440	533	0	0
T16	39289	638	0	0
T17	172170	939	0	0
T18	0	377	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3183047	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3183047	0	0
T1	44297	206	0	0
T2	118689	2885	0	0
T3	589	4	0	0
T4	54768	0	0	0
T5	467	6	0	0
T13	58411	6	0	0
T14	2893	19	0	0
T15	54440	209	0	0
T16	39289	638	0	0
T17	172170	404	0	0
T18	0	221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1465734	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1465734	0	0
T1	44297	277	0	0
T2	118689	23	0	0
T3	589	2	0	0
T4	54768	0	0	0
T5	467	2	0	0
T13	58411	22	0	0
T14	2893	18	0	0
T15	54440	473	0	0
T16	39289	379	0	0
T17	172170	2102	0	0
T18	0	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	4086959	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	4086959	0	0
T1	44297	150	0	0
T2	118689	2601	0	0
T3	589	2	0	0
T4	54768	0	0	0
T5	467	2	0	0
T13	58411	4	0	0
T14	2893	19	0	0
T15	54440	219	0	0
T16	39289	379	0	0
T17	172170	1306	0	0
T18	0	385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1416721	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1416721	0	0
T1	44297	318	0	0
T2	118689	78	0	0
T3	589	5	0	0
T4	54768	1230	0	0
T5	467	2	0	0
T13	58411	10	0	0
T14	2893	6	0	0
T15	54440	540	0	0
T16	39289	1726	0	0
T17	172170	903	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3614115	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3614115	0	0
T1	44297	104	0	0
T2	118689	4969	0	0
T3	589	5	0	0
T4	54768	1761	0	0
T5	467	2	0	0
T13	58411	3	0	0
T14	2893	4	0	0
T15	54440	254	0	0
T16	39289	1726	0	0
T17	172170	362	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1483687	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1483687	0	0
T1	44297	323	0	0
T2	118689	14	0	0
T3	589	1	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	16	0	0
T14	2893	3	0	0
T15	54440	521	0	0
T16	39289	644	0	0
T17	172170	2468	0	0
T18	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3294790	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3294790	0	0
T1	44297	125	0	0
T2	118689	2470	0	0
T3	589	1	0	0
T4	54768	0	0	0
T5	467	4	0	0
T13	58411	3	0	0
T14	2893	19	0	0
T15	54440	241	0	0
T16	39289	644	0	0
T17	172170	1167	0	0
T18	0	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1423384	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1423384	0	0
T1	44297	362	0	0
T2	118689	31	0	0
T3	589	3	0	0
T4	54768	4253	0	0
T5	467	1	0	0
T13	58411	45	0	0
T14	2893	44	0	0
T15	54440	490	0	0
T16	39289	397	0	0
T17	172170	996	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3539823	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3539823	0	0
T1	44297	242	0	0
T2	118689	2152	0	0
T3	589	3	0	0
T4	54768	3892	0	0
T5	467	1	0	0
T13	58411	7	0	0
T14	2893	42	0	0
T15	54440	255	0	0
T16	39289	397	0	0
T17	172170	439	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1501426	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1501426	0	0
T1	44297	248	0	0
T2	118689	37	0	0
T3	589	4	0	0
T4	54768	1556	0	0
T5	467	8	0	0
T13	58411	5	0	0
T14	2893	8	0	0
T15	54440	658	0	0
T16	39289	672	0	0
T17	172170	6458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3424120	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3424120	0	0
T1	44297	144	0	0
T2	118689	2284	0	0
T3	589	4	0	0
T4	54768	2104	0	0
T5	467	8	0	0
T13	58411	2	0	0
T14	2893	17	0	0
T15	54440	247	0	0
T16	39289	672	0	0
T17	172170	3218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1499511	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1499511	0	0
T1	44297	304	0	0
T2	118689	14	0	0
T3	589	1	0	0
T4	54768	1464	0	0
T5	467	5	0	0
T13	58411	32	0	0
T14	2893	85	0	0
T15	54440	407	0	0
T16	39289	827	0	0
T17	172170	1087	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	2524963	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	2524963	0	0
T1	44297	135	0	0
T2	118689	447	0	0
T3	589	1	0	0
T4	54768	2164	0	0
T5	467	5	0	0
T13	58411	6	0	0
T14	2893	55	0	0
T15	54440	255	0	0
T16	39289	827	0	0
T17	172170	360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1498671	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1498671	0	0
T1	44297	263	0	0
T2	118689	27	0	0
T3	589	2	0	0
T4	54768	1427	0	0
T5	467	10	0	0
T13	58411	2	0	0
T14	2893	34	0	0
T15	54440	647	0	0
T16	39289	378	0	0
T17	172170	2674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3525605	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3525605	0	0
T1	44297	124	0	0
T2	118689	2325	0	0
T3	589	2	0	0
T4	54768	1870	0	0
T5	467	10	0	0
T13	58411	2	0	0
T14	2893	24	0	0
T15	54440	299	0	0
T16	39289	378	0	0
T17	172170	1421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1506887	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1506887	0	0
T1	44297	460	0	0
T2	118689	24	0	0
T3	589	1	0	0
T4	54768	1464	0	0
T5	467	9	0	0
T13	58411	18	0	0
T14	2893	41	0	0
T15	54440	560	0	0
T16	39289	813	0	0
T17	172170	1176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3684585	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3684585	0	0
T1	44297	219	0	0
T2	118689	2634	0	0
T3	589	1	0	0
T4	54768	2220	0	0
T5	467	9	0	0
T13	58411	4	0	0
T14	2893	43	0	0
T15	54440	240	0	0
T16	39289	813	0	0
T17	172170	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	1442270	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	1442270	0	0
T1	44297	256	0	0
T2	118689	14	0	0
T3	589	2	0	0
T4	54768	2211	0	0
T5	467	5	0	0
T13	58411	16	0	0
T14	2893	9	0	0
T15	54440	569	0	0
T16	39289	437	0	0
T17	172170	2312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	328180319	3516068	0	0
DepthKnown_A	328180319	328053647	0	0
RvalidKnown_A	328180319	328053647	0	0
WreadyKnown_A	328180319	328053647	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	3516068	0	0
T1	44297	110	0	0
T2	118689	1664	0	0
T3	589	2	0	0
T4	54768	2106	0	0
T5	467	5	0	0
T13	58411	73	0	0
T14	2893	42	0	0
T15	54440	325	0	0
T16	39289	437	0	0
T17	172170	1198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328180319	328053647	0	0
T1	44297	44257	0	0
T2	118689	118673	0	0
T3	589	530	0	0
T4	54768	54731	0	0
T5	467	437	0	0
T13	58411	58374	0	0
T14	2893	2886	0	0
T15	54440	54402	0	0
T16	39289	39243	0	0
T17	172170	172075	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0