Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1681917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264055

1

T1

13

T4

302

T3

323

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	658492	1			T1	41		T2	6		T4	776
values[0x0]	627994	1			T1	39		T4	763		T3	771
values[0x1]	659486	1			T1	50		T2	8		T4	806

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304182	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

641790

1

T1

41

T2

7

T4

734

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7045	1			T4	6		T5	1		T6	3
valid_sources[0x01]	7187	1			T5	1		T6	4		T15	2
valid_sources[0x02]	7325	1			T1	1		T4	13		T3	72
valid_sources[0x03]	7471	1			T1	1		T4	6		T3	111
valid_sources[0x04]	8028	1			T4	8		T6	4		T15	3
valid_sources[0x05]	8478	1			T4	26		T6	5		T16	18
valid_sources[0x06]	8190	1			T1	1		T4	33		T6	2
valid_sources[0x07]	7119	1			T1	1		T4	28		T3	83
valid_sources[0x08]	8069	1			T1	2		T4	45		T6	14
valid_sources[0x09]	7208	1			T4	22		T6	18		T16	18
valid_sources[0x0a]	7387	1			T4	18		T6	5		T16	1
valid_sources[0x0b]	6969	1			T6	7		T15	1		T16	16
valid_sources[0x0c]	7739	1			T4	6		T6	7		T15	1
valid_sources[0x0d]	7104	1			T1	1		T2	1		T4	15
valid_sources[0x0e]	7503	1			T4	14		T6	3		T14	8
valid_sources[0x0f]	7092	1			T4	5		T6	2		T16	10
valid_sources[0x10]	7360	1			T4	10		T6	7		T16	18
valid_sources[0x11]	8178	1			T2	1		T6	7		T14	3
valid_sources[0x12]	7968	1			T4	26		T6	6		T15	1
valid_sources[0x13]	7170	1			T4	14		T5	2		T6	10
valid_sources[0x14]	8322	1			T1	1		T4	5		T6	5
valid_sources[0x15]	8572	1			T4	16		T6	5		T15	6
valid_sources[0x16]	7080	1			T1	1		T4	12		T3	2
valid_sources[0x17]	7452	1			T1	1		T2	1		T5	1
valid_sources[0x18]	7489	1			T1	1		T4	8		T6	2
valid_sources[0x19]	7156	1			T6	15		T14	1		T16	15
valid_sources[0x1a]	6624	1			T6	3		T17	14		T18	30
valid_sources[0x1b]	7270	1			T1	2		T4	9		T6	6
valid_sources[0x1c]	8610	1			T1	1		T4	15		T6	13
valid_sources[0x1d]	7111	1			T6	14		T16	6		T17	4
valid_sources[0x1e]	7486	1			T4	31		T6	1		T16	2
valid_sources[0x1f]	8007	1			T4	18		T3	76		T6	5
valid_sources[0x20]	8024	1			T4	13		T6	12		T16	20
valid_sources[0x21]	7393	1			T1	2		T4	20		T6	7
valid_sources[0x22]	7319	1			T3	92		T6	5		T14	3
valid_sources[0x23]	7681	1			T4	7		T6	2		T15	2
valid_sources[0x24]	7300	1			T4	36		T6	5		T16	4
valid_sources[0x25]	8272	1			T1	2		T6	4		T16	10
valid_sources[0x26]	7133	1			T1	2		T3	392		T6	4
valid_sources[0x27]	8219	1			T4	26		T6	8		T15	1
valid_sources[0x28]	6993	1			T6	1		T15	1		T16	3
valid_sources[0x29]	7881	1			T1	3		T6	9		T15	5
valid_sources[0x2a]	6930	1			T4	68		T6	2		T16	7
valid_sources[0x2b]	8780	1			T5	1		T6	5		T14	4
valid_sources[0x2c]	6980	1			T4	16		T5	1		T6	6
valid_sources[0x2d]	7005	1			T1	2		T4	8		T6	12
valid_sources[0x2e]	7243	1			T4	5		T3	60		T6	5
valid_sources[0x2f]	6954	1			T4	11		T6	9		T16	3
valid_sources[0x30]	7037	1			T6	13		T16	18		T17	17
valid_sources[0x31]	7532	1			T1	2		T5	1		T6	13
valid_sources[0x32]	7273	1			T4	6		T6	9		T16	16
valid_sources[0x33]	7740	1			T1	1		T6	5		T14	6
valid_sources[0x34]	7889	1			T4	32		T6	15		T14	1
valid_sources[0x35]	7549	1			T1	1		T6	14		T16	7
valid_sources[0x36]	7109	1			T4	10		T6	7		T16	15
valid_sources[0x37]	7456	1			T6	8		T15	2		T14	5
valid_sources[0x38]	7514	1			T6	20		T16	28		T17	9
valid_sources[0x39]	7448	1			T4	9		T6	12		T14	1
valid_sources[0x3a]	7743	1			T1	3		T6	17		T15	2
valid_sources[0x3b]	6929	1			T1	3		T6	3		T16	7
valid_sources[0x3c]	7653	1			T5	1		T6	8		T16	11
valid_sources[0x3d]	7570	1			T1	2		T6	9		T15	4
valid_sources[0x3e]	7371	1			T6	19		T16	31		T17	9
valid_sources[0x3f]	7265	1			T6	12		T16	10		T17	2
valid_sources[0x40]	7694	1			T4	8		T6	3		T14	2
valid_sources[0x41]	8124	1			T6	8		T16	4		T17	1
valid_sources[0x42]	7558	1			T4	33		T6	8		T16	21
valid_sources[0x43]	8221	1			T1	2		T6	6		T16	5
valid_sources[0x44]	7091	1			T4	30		T6	2		T15	1
valid_sources[0x45]	8345	1			T4	55		T5	1		T6	12
valid_sources[0x46]	8378	1			T1	1		T6	13		T16	10
valid_sources[0x47]	7658	1			T1	1		T6	6		T14	5
valid_sources[0x48]	7068	1			T1	1		T4	25		T6	6
valid_sources[0x49]	7110	1			T4	41		T6	11		T15	1
valid_sources[0x4a]	8114	1			T4	28		T6	4		T14	2
valid_sources[0x4b]	7405	1			T4	7		T6	10		T16	27
valid_sources[0x4c]	7611	1			T4	13		T6	5		T14	11
valid_sources[0x4d]	7294	1			T1	1		T2	1		T6	8
valid_sources[0x4e]	7438	1			T6	4		T16	14		T17	1
valid_sources[0x4f]	7352	1			T6	8		T16	25		T17	4
valid_sources[0x50]	7264	1			T4	34		T6	2		T14	2
valid_sources[0x51]	7938	1			T4	27		T6	2		T15	1
valid_sources[0x52]	6921	1			T4	6		T6	6		T15	5
valid_sources[0x53]	7690	1			T6	13		T14	7		T17	4
valid_sources[0x54]	7405	1			T4	18		T6	4		T16	3
valid_sources[0x55]	6881	1			T4	11		T6	6		T16	6
valid_sources[0x56]	7874	1			T4	16		T6	5		T15	1
valid_sources[0x57]	7270	1			T1	2		T6	3		T14	3
valid_sources[0x58]	7605	1			T6	1		T15	1		T16	17
valid_sources[0x59]	7407	1			T1	2		T6	3		T15	1
valid_sources[0x5a]	8145	1			T4	15		T6	9		T15	1
valid_sources[0x5b]	7152	1			T1	1		T4	19		T6	6
valid_sources[0x5c]	7150	1			T1	1		T6	10		T16	5
valid_sources[0x5d]	7286	1			T6	5		T16	27		T17	8
valid_sources[0x5e]	6719	1			T1	2		T17	7		T18	9
valid_sources[0x5f]	7517	1			T1	1		T2	1		T4	5
valid_sources[0x60]	7369	1			T4	15		T6	3		T15	1
valid_sources[0x61]	7824	1			T4	13		T6	4		T14	1
valid_sources[0x62]	8688	1			T3	81		T6	2		T14	6
valid_sources[0x63]	6815	1			T16	32		T17	4		T18	5
valid_sources[0x64]	7256	1			T6	10		T16	24		T17	5
valid_sources[0x65]	6842	1			T1	2		T6	8		T15	1
valid_sources[0x66]	7684	1			T1	2		T2	2		T6	9
valid_sources[0x67]	7518	1			T1	3		T6	9		T15	1
valid_sources[0x68]	7283	1			T1	2		T4	16		T6	6
valid_sources[0x69]	7898	1			T1	1		T3	31		T6	2
valid_sources[0x6a]	7306	1			T1	1		T4	18		T6	11
valid_sources[0x6b]	8243	1			T4	26		T6	5		T15	2
valid_sources[0x6c]	7958	1			T1	1		T4	13		T6	3
valid_sources[0x6d]	7814	1			T1	1		T4	7		T6	8
valid_sources[0x6e]	7735	1			T5	1		T6	3		T16	7
valid_sources[0x6f]	8138	1			T6	13		T14	2		T16	30
valid_sources[0x70]	8047	1			T6	6		T15	1		T14	5
valid_sources[0x71]	7765	1			T1	1		T4	14		T3	42
valid_sources[0x72]	8737	1			T4	14		T6	7		T15	2
valid_sources[0x73]	6991	1			T4	11		T6	2		T16	9
valid_sources[0x74]	7763	1			T6	6		T15	2		T14	9
valid_sources[0x75]	8261	1			T5	1		T6	2		T15	2
valid_sources[0x76]	8385	1			T1	1		T6	3		T16	17
valid_sources[0x77]	8879	1			T6	5		T15	1		T16	13
valid_sources[0x78]	7003	1			T1	2		T6	14		T14	2
valid_sources[0x79]	7781	1			T4	5		T5	1		T6	10
valid_sources[0x7a]	7033	1			T4	16		T5	1		T6	9
valid_sources[0x7b]	7481	1			T4	13		T6	2		T15	3
valid_sources[0x7c]	6425	1			T1	1		T4	11		T6	7
valid_sources[0x7d]	6810	1			T6	9		T16	22		T17	1
valid_sources[0x7e]	7207	1			T4	8		T6	3		T15	2
valid_sources[0x7f]	7477	1			T4	19		T6	9		T16	5
valid_sources[0x80]	8663	1			T6	1		T15	3		T16	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27994

1

T1

4

T4

32

T3

35

values[0x0]

all_enables

biggest_size

208255

1

T1

8

T4

228

T3

254

values[0x1]

all_enables

biggest_size

27806

1

T1

1

T4

42

T3

34