Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	350678579	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350678579	0	0
T1	23240	638	0	0
T2	414176	7897	0	0
T3	267568	11488	0	0
T4	273392	9364	0	0
T5	837144	14936	0	0
T6	220864	8864	0	0
T14	65968	1792	0	0
T15	245616	4585	0	0
T16	277872	15792	0	0
T17	1591632	32816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23240	22232	0	0
T2	414176	398720	0	0
T3	267568	265776	0	0
T4	273392	271936	0	0
T5	837144	802368	0	0
T6	220864	216664	0	0
T14	65968	62832	0	0
T15	245616	244608	0	0
T16	277872	274904	0	0
T17	1591632	1589504	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23240	22232	0	0
T2	414176	398720	0	0
T3	267568	265776	0	0
T4	273392	271936	0	0
T5	837144	802368	0	0
T6	220864	216664	0	0
T14	65968	62832	0	0
T15	245616	244608	0	0
T16	277872	274904	0	0
T17	1591632	1589504	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23240	22232	0	0
T2	414176	398720	0	0
T3	267568	265776	0	0
T4	273392	271936	0	0
T5	837144	802368	0	0
T6	220864	216664	0	0
T14	65968	62832	0	0
T15	245616	244608	0	0
T16	277872	274904	0	0
T17	1591632	1589504	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	128545140	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	128545140	0	0
T1	415	248	0	0
T2	7396	3555	0	0
T3	4778	4454	0	0
T4	4882	2345	0	0
T5	14949	6390	0	0
T6	3944	3461	0	0
T14	1178	819	0	0
T15	4386	1974	0	0
T16	4962	4644	0	0
T17	28422	15820	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	91405076	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	91405076	0	0
T1	415	130	0	0
T2	7396	1006	0	0
T3	4778	2346	0	0
T4	4882	2345	0	0
T5	14949	1971	0	0
T6	3944	1801	0	0
T14	1178	485	0	0
T15	4386	600	0	0
T16	4962	3716	0	0
T17	28422	3576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1521994	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1521994	0	0
T1	415	9	0	0
T2	7396	46	0	0
T3	4778	73	0	0
T4	4882	87	0	0
T5	14949	174	0	0
T6	3944	56	0	0
T14	1178	9	0	0
T15	4386	51	0	0
T16	4962	319	0	0
T17	28422	421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3687616	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3687616	0	0
T1	415	9	0	0
T2	7396	32	0	0
T3	4778	73	0	0
T4	4882	87	0	0
T5	14949	45	0	0
T6	3944	56	0	0
T14	1178	9	0	0
T15	4386	14	0	0
T16	4962	319	0	0
T17	28422	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1463383	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1463383	0	0
T1	415	2	0	0
T2	7396	104	0	0
T3	4778	93	0	0
T4	4882	91	0	0
T5	14949	1294	0	0
T6	3944	80	0	0
T14	1178	10	0	0
T15	4386	64	0	0
T16	4962	52	0	0
T17	28422	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3141207	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3141207	0	0
T1	415	2	0	0
T2	7396	48	0	0
T3	4778	93	0	0
T4	4882	91	0	0
T5	14949	586	0	0
T6	3944	80	0	0
T14	1178	10	0	0
T15	4386	29	0	0
T16	4962	52	0	0
T17	28422	139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1503363	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1503363	0	0
T1	415	2	0	0
T2	7396	46	0	0
T3	4778	81	0	0
T4	4882	71	0	0
T5	14949	168	0	0
T6	3944	68	0	0
T14	1178	5	0	0
T15	4386	12	0	0
T16	4962	28	0	0
T17	28422	262	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	4063144	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	4063144	0	0
T1	415	2	0	0
T2	7396	33	0	0
T3	4778	81	0	0
T4	4882	71	0	0
T5	14949	79	0	0
T6	3944	68	0	0
T14	1178	5	0	0
T15	4386	8	0	0
T16	4962	28	0	0
T17	28422	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1551088	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1551088	0	0
T1	415	1	0	0
T2	7396	109	0	0
T3	4778	76	0	0
T4	4882	85	0	0
T5	14949	107	0	0
T6	3944	58	0	0
T14	1178	11	0	0
T15	4386	85	0	0
T16	4962	29	0	0
T17	28422	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3414976	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3414976	0	0
T1	415	1	0	0
T2	7396	33	0	0
T3	4778	76	0	0
T4	4882	85	0	0
T5	14949	63	0	0
T6	3944	58	0	0
T14	1178	11	0	0
T15	4386	33	0	0
T16	4962	29	0	0
T17	28422	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1506555	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1506555	0	0
T1	415	4	0	0
T2	7396	97	0	0
T3	4778	89	0	0
T4	4882	89	0	0
T5	14949	84	0	0
T6	3944	70	0	0
T14	1178	10	0	0
T15	4386	81	0	0
T16	4962	254	0	0
T17	28422	312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	2758895	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	2758895	0	0
T1	415	4	0	0
T2	7396	44	0	0
T3	4778	89	0	0
T4	4882	89	0	0
T5	14949	46	0	0
T6	3944	70	0	0
T14	1178	10	0	0
T15	4386	27	0	0
T16	4962	254	0	0
T17	28422	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1468993	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1468993	0	0
T1	415	9	0	0
T2	7396	62	0	0
T3	4778	88	0	0
T4	4882	85	0	0
T5	14949	129	0	0
T6	3944	76	0	0
T14	1178	6	0	0
T15	4386	73	0	0
T16	4962	35	0	0
T17	28422	267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3095288	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3095288	0	0
T1	415	9	0	0
T2	7396	33	0	0
T3	4778	88	0	0
T4	4882	85	0	0
T5	14949	45	0	0
T6	3944	76	0	0
T14	1178	6	0	0
T15	4386	10	0	0
T16	4962	35	0	0
T17	28422	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1525731	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1525731	0	0
T1	415	4	0	0
T2	7396	63	0	0
T3	4778	94	0	0
T4	4882	85	0	0
T5	14949	57	0	0
T6	3944	73	0	0
T14	1178	10	0	0
T15	4386	41	0	0
T16	4962	313	0	0
T17	28422	263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3245513	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3245513	0	0
T1	415	4	0	0
T2	7396	41	0	0
T3	4778	94	0	0
T4	4882	85	0	0
T5	14949	56	0	0
T6	3944	73	0	0
T14	1178	10	0	0
T15	4386	36	0	0
T16	4962	313	0	0
T17	28422	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1537749	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1537749	0	0
T1	415	5	0	0
T2	7396	51	0	0
T3	4778	84	0	0
T4	4882	80	0	0
T5	14949	202	0	0
T6	3944	64	0	0
T14	1178	15	0	0
T15	4386	27	0	0
T16	4962	40	0	0
T17	28422	356	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3745894	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3745894	0	0
T1	415	5	0	0
T2	7396	7	0	0
T3	4778	84	0	0
T4	4882	80	0	0
T5	14949	82	0	0
T6	3944	64	0	0
T14	1178	15	0	0
T15	4386	41	0	0
T16	4962	40	0	0
T17	28422	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1528756	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1528756	0	0
T1	415	8	0	0
T2	7396	101	0	0
T3	4778	92	0	0
T4	4882	80	0	0
T5	14949	76	0	0
T6	3944	78	0	0
T14	1178	6	0	0
T15	4386	26	0	0
T16	4962	241	0	0
T17	28422	371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3876204	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3876204	0	0
T1	415	8	0	0
T2	7396	9	0	0
T3	4778	92	0	0
T4	4882	80	0	0
T5	14949	30	0	0
T6	3944	78	0	0
T14	1178	6	0	0
T15	4386	5	0	0
T16	4962	241	0	0
T17	28422	168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1522980	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1522980	0	0
T1	415	3	0	0
T2	7396	73	0	0
T3	4778	86	0	0
T4	4882	88	0	0
T5	14949	98	0	0
T6	3944	62	0	0
T14	1178	11	0	0
T15	4386	93	0	0
T16	4962	41	0	0
T17	28422	335	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3898838	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3898838	0	0
T1	415	3	0	0
T2	7396	22	0	0
T3	4778	86	0	0
T4	4882	88	0	0
T5	14949	31	0	0
T6	3944	62	0	0
T14	1178	11	0	0
T15	4386	33	0	0
T16	4962	41	0	0
T17	28422	173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1460422	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1460422	0	0
T1	415	3	0	0
T2	7396	67	0	0
T3	4778	84	0	0
T4	4882	89	0	0
T5	14949	79	0	0
T6	3944	69	0	0
T14	1178	4	0	0
T15	4386	103	0	0
T16	4962	263	0	0
T17	28422	264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3228062	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3228062	0	0
T1	415	3	0	0
T2	7396	62	0	0
T3	4778	84	0	0
T4	4882	89	0	0
T5	14949	47	0	0
T6	3944	69	0	0
T14	1178	4	0	0
T15	4386	33	0	0
T16	4962	263	0	0
T17	28422	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1511738	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1511738	0	0
T1	415	8	0	0
T2	7396	83	0	0
T3	4778	92	0	0
T4	4882	96	0	0
T5	14949	126	0	0
T6	3944	75	0	0
T14	1178	9	0	0
T15	4386	16	0	0
T16	4962	27	0	0
T17	28422	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3279270	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3279270	0	0
T1	415	8	0	0
T2	7396	32	0	0
T3	4778	92	0	0
T4	4882	96	0	0
T5	14949	42	0	0
T6	3944	75	0	0
T14	1178	9	0	0
T15	4386	6	0	0
T16	4962	27	0	0
T17	28422	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1449163	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1449163	0	0
T1	415	4	0	0
T2	7396	70	0	0
T3	4778	68	0	0
T4	4882	89	0	0
T5	14949	101	0	0
T6	3944	71	0	0
T14	1178	9	0	0
T15	4386	36	0	0
T16	4962	41	0	0
T17	28422	404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3272854	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3272854	0	0
T1	415	4	0	0
T2	7396	33	0	0
T3	4778	68	0	0
T4	4882	89	0	0
T5	14949	48	0	0
T6	3944	71	0	0
T14	1178	9	0	0
T15	4386	6	0	0
T16	4962	41	0	0
T17	28422	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1488321	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1488321	0	0
T1	415	2	0	0
T2	7396	66	0	0
T3	4778	95	0	0
T4	4882	85	0	0
T5	14949	116	0	0
T6	3944	66	0	0
T14	1178	13	0	0
T15	4386	47	0	0
T16	4962	34	0	0
T17	28422	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3429106	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3429106	0	0
T1	415	2	0	0
T2	7396	14	0	0
T3	4778	95	0	0
T4	4882	85	0	0
T5	14949	18	0	0
T6	3944	66	0	0
T14	1178	13	0	0
T15	4386	22	0	0
T16	4962	34	0	0
T17	28422	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1413824	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1413824	0	0
T1	415	2	0	0
T2	7396	129	0	0
T3	4778	70	0	0
T4	4882	88	0	0
T5	14949	112	0	0
T6	3944	53	0	0
T14	1178	3	0	0
T15	4386	63	0	0
T16	4962	32	0	0
T17	28422	362	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3085129	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3085129	0	0
T1	415	2	0	0
T2	7396	37	0	0
T3	4778	70	0	0
T4	4882	88	0	0
T5	14949	26	0	0
T6	3944	53	0	0
T14	1178	3	0	0
T15	4386	19	0	0
T16	4962	32	0	0
T17	28422	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1488531	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1488531	0	0
T1	415	3	0	0
T2	7396	101	0	0
T3	4778	82	0	0
T4	4882	101	0	0
T5	14949	86	0	0
T6	3944	66	0	0
T14	1178	12	0	0
T15	4386	40	0	0
T16	4962	253	0	0
T17	28422	311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3054650	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3054650	0	0
T1	415	3	0	0
T2	7396	30	0	0
T3	4778	82	0	0
T4	4882	101	0	0
T5	14949	48	0	0
T6	3944	66	0	0
T14	1178	12	0	0
T15	4386	42	0	0
T16	4962	253	0	0
T17	28422	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1472556	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1472556	0	0
T1	415	9	0	0
T2	7396	131	0	0
T3	4778	88	0	0
T4	4882	87	0	0
T5	14949	130	0	0
T6	3944	75	0	0
T14	1178	5	0	0
T15	4386	38	0	0
T16	4962	43	0	0
T17	28422	417	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	2948882	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	2948882	0	0
T1	415	9	0	0
T2	7396	35	0	0
T3	4778	88	0	0
T4	4882	87	0	0
T5	14949	46	0	0
T6	3944	75	0	0
T14	1178	5	0	0
T15	4386	17	0	0
T16	4962	43	0	0
T17	28422	125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1425147	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1425147	0	0
T1	415	3	0	0
T2	7396	33	0	0
T3	4778	92	0	0
T4	4882	92	0	0
T5	14949	83	0	0
T6	3944	60	0	0
T14	1178	5	0	0
T15	4386	94	0	0
T16	4962	242	0	0
T17	28422	467	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3256061	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3256061	0	0
T1	415	3	0	0
T2	7396	10	0	0
T3	4778	92	0	0
T4	4882	92	0	0
T5	14949	39	0	0
T6	3944	60	0	0
T14	1178	5	0	0
T15	4386	18	0	0
T16	4962	242	0	0
T17	28422	185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1473755	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1473755	0	0
T1	415	5	0	0
T2	7396	99	0	0
T3	4778	91	0	0
T4	4882	79	0	0
T5	14949	103	0	0
T6	3944	53	0	0
T14	1178	10	0	0
T15	4386	26	0	0
T16	4962	43	0	0
T17	28422	483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3431702	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3431702	0	0
T1	415	5	0	0
T2	7396	38	0	0
T3	4778	91	0	0
T4	4882	79	0	0
T5	14949	27	0	0
T6	3944	53	0	0
T14	1178	10	0	0
T15	4386	15	0	0
T16	4962	43	0	0
T17	28422	150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1468730	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1468730	0	0
T1	415	12	0	0
T2	7396	82	0	0
T3	4778	95	0	0
T4	4882	100	0	0
T5	14949	133	0	0
T6	3944	50	0	0
T14	1178	8	0	0
T15	4386	50	0	0
T16	4962	30	0	0
T17	28422	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	2787576	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	2787576	0	0
T1	415	12	0	0
T2	7396	38	0	0
T3	4778	95	0	0
T4	4882	100	0	0
T5	14949	51	0	0
T6	3944	50	0	0
T14	1178	8	0	0
T15	4386	26	0	0
T16	4962	30	0	0
T17	28422	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1499487	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1499487	0	0
T1	415	3	0	0
T2	7396	107	0	0
T3	4778	91	0	0
T4	4882	84	0	0
T5	14949	102	0	0
T6	3944	64	0	0
T14	1178	10	0	0
T15	4386	53	0	0
T16	4962	36	0	0
T17	28422	284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	4510152	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	4510152	0	0
T1	415	3	0	0
T2	7396	47	0	0
T3	4778	91	0	0
T4	4882	84	0	0
T5	14949	35	0	0
T6	3944	64	0	0
T14	1178	10	0	0
T15	4386	27	0	0
T16	4962	36	0	0
T17	28422	113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1495214	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1495214	0	0
T1	415	10	0	0
T2	7396	82	0	0
T3	4778	100	0	0
T4	4882	78	0	0
T5	14949	84	0	0
T6	3944	62	0	0
T14	1178	16	0	0
T15	4386	55	0	0
T16	4962	54	0	0
T17	28422	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3343545	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3343545	0	0
T1	415	10	0	0
T2	7396	22	0	0
T3	4778	100	0	0
T4	4882	78	0	0
T5	14949	39	0	0
T6	3944	62	0	0
T14	1178	16	0	0
T15	4386	28	0	0
T16	4962	54	0	0
T17	28422	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1477855	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1477855	0	0
T1	415	2	0	0
T2	7396	209	0	0
T3	4778	89	0	0
T4	4882	69	0	0
T5	14949	82	0	0
T6	3944	74	0	0
T14	1178	9	0	0
T15	4386	48	0	0
T16	4962	318	0	0
T17	28422	412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3618819	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3618819	0	0
T1	415	2	0	0
T2	7396	110	0	0
T3	4778	89	0	0
T4	4882	69	0	0
T5	14949	30	0	0
T6	3944	74	0	0
T14	1178	9	0	0
T15	4386	8	0	0
T16	4962	318	0	0
T17	28422	143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1498802	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1498802	0	0
T1	415	4	0	0
T2	7396	96	0	0
T3	4778	80	0	0
T4	4882	90	0	0
T5	14949	78	0	0
T6	3944	68	0	0
T14	1178	13	0	0
T15	4386	73	0	0
T16	4962	548	0	0
T17	28422	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3293261	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3293261	0	0
T1	415	4	0	0
T2	7396	38	0	0
T3	4778	80	0	0
T4	4882	90	0	0
T5	14949	38	0	0
T6	3944	68	0	0
T14	1178	13	0	0
T15	4386	63	0	0
T16	4962	548	0	0
T17	28422	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1475055	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1475055	0	0
T1	415	4	0	0
T2	7396	55	0	0
T3	4778	102	0	0
T4	4882	82	0	0
T5	14949	702	0	0
T6	3944	70	0	0
T14	1178	12	0	0
T15	4386	14	0	0
T16	4962	38	0	0
T17	28422	283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	2637843	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	2637843	0	0
T1	415	4	0	0
T2	7396	23	0	0
T3	4778	102	0	0
T4	4882	82	0	0
T5	14949	263	0	0
T6	3944	70	0	0
T14	1178	12	0	0
T15	4386	7	0	0
T16	4962	38	0	0
T17	28422	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1484479	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1484479	0	0
T1	415	3	0	0
T2	7396	82	0	0
T3	4778	77	0	0
T4	4882	96	0	0
T5	14949	54	0	0
T6	3944	74	0	0
T14	1178	7	0	0
T15	4386	64	0	0
T16	4962	326	0	0
T17	28422	394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3208006	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3208006	0	0
T1	415	3	0	0
T2	7396	73	0	0
T3	4778	77	0	0
T4	4882	96	0	0
T5	14949	28	0	0
T6	3944	74	0	0
T14	1178	7	0	0
T15	4386	18	0	0
T16	4962	326	0	0
T17	28422	143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	1475924	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	1475924	0	0
T1	415	6	0	0
T2	7396	105	0	0
T3	4778	92	0	0
T4	4882	91	0	0
T5	14949	83	0	0
T6	3944	66	0	0
T14	1178	6	0	0
T15	4386	38	0	0
T16	4962	36	0	0
T17	28422	313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313188510	3226275	0	0
DepthKnown_A	313188510	313076423	0	0
RvalidKnown_A	313188510	313076423	0	0
WreadyKnown_A	313188510	313076423	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	3226275	0	0
T1	415	6	0	0
T2	7396	43	0	0
T3	4778	92	0	0
T4	4882	91	0	0
T5	14949	44	0	0
T6	3944	66	0	0
T14	1178	6	0	0
T15	4386	9	0	0
T16	4962	36	0	0
T17	28422	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313188510	313076423	0	0
T1	415	397	0	0
T2	7396	7120	0	0
T3	4778	4746	0	0
T4	4882	4856	0	0
T5	14949	14328	0	0
T6	3944	3869	0	0
T14	1178	1122	0	0
T15	4386	4368	0	0
T16	4962	4909	0	0
T17	28422	28384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0