Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1917724	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

300522

1

T1

145

T2

105

T3

131

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	749345	1			T1	537		T2	230		T3	345
values[0x0]	719183	1			T1	75		T2	240		T3	342
values[0x1]	749718	1			T1	535		T2	226		T3	304

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1486329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

731917

1

T1

449

T2

243

T3

316

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8922	1			T2	1		T3	20		T5	1
valid_sources[0x01]	8073	1			T1	3		T2	1		T5	1
valid_sources[0x02]	8095	1			T1	51		T2	6		T3	8
valid_sources[0x03]	8272	1			T1	9		T2	5		T3	12
valid_sources[0x04]	8133	1			T1	17		T4	1		T5	1
valid_sources[0x05]	8215	1			T1	1		T4	1		T14	24
valid_sources[0x06]	8962	1			T2	1		T16	20		T17	15
valid_sources[0x07]	8516	1			T1	6		T4	1		T14	18
valid_sources[0x08]	8568	1			T1	38		T2	2		T5	1
valid_sources[0x09]	8729	1			T1	2		T2	4		T3	13
valid_sources[0x0a]	8988	1			T1	1		T14	9		T20	4
valid_sources[0x0b]	8502	1			T1	44		T2	1		T4	1
valid_sources[0x0c]	8498	1			T2	1		T14	39		T17	11
valid_sources[0x0d]	8786	1			T1	70		T2	4		T4	1
valid_sources[0x0e]	9530	1			T1	45		T13	1		T14	19
valid_sources[0x0f]	8853	1			T2	9		T3	16		T4	1
valid_sources[0x10]	8137	1			T1	4		T2	1		T3	18
valid_sources[0x11]	8280	1			T2	1		T17	24		T19	3
valid_sources[0x12]	9119	1			T1	17		T2	3		T5	1
valid_sources[0x13]	8040	1			T1	3		T3	7		T5	1
valid_sources[0x14]	8355	1			T1	30		T4	1		T5	1
valid_sources[0x15]	7949	1			T2	1		T4	1		T5	1
valid_sources[0x16]	8364	1			T5	1		T13	2		T14	33
valid_sources[0x17]	8888	1			T2	1		T4	1		T14	25
valid_sources[0x18]	8770	1			T2	5		T14	7		T17	10
valid_sources[0x19]	8074	1			T2	5		T4	1		T5	2
valid_sources[0x1a]	9368	1			T3	12		T14	15		T16	18
valid_sources[0x1b]	8514	1			T1	2		T2	1		T4	18
valid_sources[0x1c]	8370	1			T20	3		T22	1		T188	2
valid_sources[0x1d]	8392	1			T2	2		T3	32		T5	1
valid_sources[0x1e]	9344	1			T1	20		T2	7		T4	1
valid_sources[0x1f]	8679	1			T2	3		T5	2		T17	17
valid_sources[0x20]	8139	1			T2	3		T3	16		T14	1
valid_sources[0x21]	8785	1			T1	1		T2	3		T4	2
valid_sources[0x22]	8836	1			T1	3		T2	2		T3	11
valid_sources[0x23]	8523	1			T1	3		T5	1		T14	7
valid_sources[0x24]	8619	1			T1	1		T2	1		T13	2
valid_sources[0x25]	9024	1			T2	12		T14	1		T16	14
valid_sources[0x26]	8870	1			T1	9		T2	7		T3	12
valid_sources[0x27]	8584	1			T2	2		T14	17		T20	1
valid_sources[0x28]	9057	1			T1	1		T2	4		T3	14
valid_sources[0x29]	8742	1			T1	2		T2	3		T5	1
valid_sources[0x2a]	9252	1			T2	1		T14	11		T16	20
valid_sources[0x2b]	8478	1			T2	5		T13	1		T15	4
valid_sources[0x2c]	8830	1			T1	3		T2	2		T13	1
valid_sources[0x2d]	8692	1			T2	1		T4	2		T14	10
valid_sources[0x2e]	8221	1			T1	1		T2	2		T5	1
valid_sources[0x2f]	8464	1			T2	2		T3	9		T13	1
valid_sources[0x30]	7630	1			T1	2		T2	2		T14	8
valid_sources[0x31]	8465	1			T1	3		T13	1		T17	4
valid_sources[0x32]	8628	1			T1	5		T3	18		T4	1
valid_sources[0x33]	8174	1			T1	3		T2	4		T4	1
valid_sources[0x34]	8640	1			T1	1		T2	2		T4	1
valid_sources[0x35]	9260	1			T1	6		T2	4		T4	1
valid_sources[0x36]	10087	1			T2	2		T4	1		T5	1
valid_sources[0x37]	8343	1			T1	1		T2	9		T5	1
valid_sources[0x38]	8988	1			T2	2		T14	13		T20	6
valid_sources[0x39]	8164	1			T1	69		T2	1		T14	16
valid_sources[0x3a]	8580	1			T2	3		T4	1		T5	1
valid_sources[0x3b]	9605	1			T1	6		T2	1		T4	2
valid_sources[0x3c]	9158	1			T2	3		T14	2		T20	6
valid_sources[0x3d]	9041	1			T2	4		T4	1		T5	1
valid_sources[0x3e]	8781	1			T2	1		T3	32		T4	1
valid_sources[0x3f]	9394	1			T13	1		T14	13		T16	15
valid_sources[0x40]	8376	1			T1	5		T2	5		T4	2
valid_sources[0x41]	8393	1			T2	3		T3	12		T4	1
valid_sources[0x42]	8223	1			T2	6		T5	1		T14	2
valid_sources[0x43]	9057	1			T2	2		T5	1		T16	9
valid_sources[0x44]	8257	1			T2	10		T14	12		T17	36
valid_sources[0x45]	8522	1			T1	14		T2	1		T14	19
valid_sources[0x46]	9857	1			T2	5		T4	1		T5	1
valid_sources[0x47]	9803	1			T1	1		T2	2		T14	23
valid_sources[0x48]	8174	1			T1	1		T2	2		T14	1
valid_sources[0x49]	8524	1			T2	1		T3	24		T14	17
valid_sources[0x4a]	9109	1			T1	31		T3	10		T4	1
valid_sources[0x4b]	8039	1			T4	1		T14	26		T17	3
valid_sources[0x4c]	7897	1			T1	1		T2	6		T13	1
valid_sources[0x4d]	8344	1			T2	3		T3	17		T13	1
valid_sources[0x4e]	8544	1			T1	1		T14	13		T17	15
valid_sources[0x4f]	9308	1			T1	7		T2	5		T3	12
valid_sources[0x50]	8741	1			T2	6		T5	1		T14	10
valid_sources[0x51]	9093	1			T1	4		T2	7		T13	2
valid_sources[0x52]	8544	1			T1	7		T2	4		T3	15
valid_sources[0x53]	8938	1			T1	1		T2	1		T3	17
valid_sources[0x54]	8594	1			T1	1		T2	2		T3	11
valid_sources[0x55]	9122	1			T1	2		T2	2		T13	1
valid_sources[0x56]	8165	1			T1	2		T2	9		T3	14
valid_sources[0x57]	8857	1			T4	2		T5	1		T19	6
valid_sources[0x58]	8465	1			T1	32		T15	4		T16	13
valid_sources[0x59]	9037	1			T2	1		T14	16		T15	6
valid_sources[0x5a]	8503	1			T2	2		T3	19		T20	10
valid_sources[0x5b]	8545	1			T1	1		T2	6		T13	1
valid_sources[0x5c]	9255	1			T1	5		T2	1		T3	18
valid_sources[0x5d]	7970	1			T1	1		T2	2		T14	23
valid_sources[0x5e]	9688	1			T1	12		T2	2		T14	10
valid_sources[0x5f]	8037	1			T14	5		T17	11		T20	8
valid_sources[0x60]	7865	1			T2	2		T3	8		T4	1
valid_sources[0x61]	8228	1			T2	3		T3	14		T14	26
valid_sources[0x62]	8582	1			T1	22		T4	1		T188	3
valid_sources[0x63]	9244	1			T2	2		T3	17		T14	6
valid_sources[0x64]	8899	1			T1	2		T2	4		T3	4
valid_sources[0x65]	9617	1			T4	5		T5	1		T13	1
valid_sources[0x66]	8870	1			T2	2		T5	2		T14	15
valid_sources[0x67]	7840	1			T1	1		T2	2		T5	2
valid_sources[0x68]	8415	1			T1	1		T2	2		T14	20
valid_sources[0x69]	9231	1			T14	42		T20	10		T22	2
valid_sources[0x6a]	8417	1			T1	5		T5	1		T14	11
valid_sources[0x6b]	9765	1			T2	1		T5	1		T14	6
valid_sources[0x6c]	7653	1			T2	3		T3	21		T13	1
valid_sources[0x6d]	8432	1			T1	8		T3	18		T14	5
valid_sources[0x6e]	8870	1			T1	2		T2	9		T14	12
valid_sources[0x6f]	8661	1			T2	1		T14	48		T16	10
valid_sources[0x70]	8440	1			T2	1		T5	1		T14	2
valid_sources[0x71]	9073	1			T1	6		T2	10		T14	1
valid_sources[0x72]	8692	1			T1	10		T2	3		T14	18
valid_sources[0x73]	8443	1			T1	13		T2	3		T5	1
valid_sources[0x74]	11082	1			T2	8		T3	10		T4	1
valid_sources[0x75]	8261	1			T1	51		T2	2		T4	1
valid_sources[0x76]	8476	1			T2	7		T13	2		T14	9
valid_sources[0x77]	8498	1			T1	4		T2	4		T14	9
valid_sources[0x78]	8069	1			T14	2		T20	2		T22	1
valid_sources[0x79]	9754	1			T1	8		T2	2		T4	1
valid_sources[0x7a]	8697	1			T4	2		T14	17		T17	45
valid_sources[0x7b]	8587	1			T1	1		T2	1		T4	1
valid_sources[0x7c]	8881	1			T2	3		T4	1		T5	1
valid_sources[0x7d]	9875	1			T1	1		T20	4		T188	2
valid_sources[0x7e]	8660	1			T2	2		T5	1		T17	5
valid_sources[0x7f]	8578	1			T1	10		T2	1		T14	16
valid_sources[0x80]	7941	1			T1	1		T2	2		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31382

1

T1

55

T2

11

T3

11

values[0x0]

all_enables

biggest_size

237768

1

T1

37

T2

90

T3

110

values[0x1]

all_enables

biggest_size

31372

1

T1

53

T2

4

T3

10