Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	370628971	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	370628971	0	0
T1	2892120	120465	0	0
T2	48169688	1176454	0	0
T3	2023896	30470	0	0
T4	177800	3399	0	0
T5	238056	8904	0	0
T13	2304400	49759	0	0
T14	285096	12033	0	0
T15	171584	5799	0	0
T16	112784	3652	0	0
T17	22588776	3019887	0	0
T18	0	382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2892120	2848216	0	0
T2	48169688	48168400	0	0
T3	2023896	2022384	0	0
T4	177800	167272	0	0
T5	238056	237216	0	0
T13	2304400	2300928	0	0
T14	285096	282912	0	0
T15	171584	168000	0	0
T16	112784	111776	0	0
T17	22588776	22588552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2892120	2848216	0	0
T2	48169688	48168400	0	0
T3	2023896	2022384	0	0
T4	177800	167272	0	0
T5	238056	237216	0	0
T13	2304400	2300928	0	0
T14	285096	282912	0	0
T15	171584	168000	0	0
T16	112784	111776	0	0
T17	22588776	22588552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2892120	2848216	0	0
T2	48169688	48168400	0	0
T3	2023896	2022384	0	0
T4	177800	167272	0	0
T5	238056	237216	0	0
T13	2304400	2300928	0	0
T14	285096	282912	0	0
T15	171584	168000	0	0
T16	112784	111776	0	0
T17	22588776	22588552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	133189127	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	133189127	0	0
T1	51645	49339	0	0
T2	860173	480868	0	0
T3	36141	7743	0	0
T4	3175	1432	0	0
T5	4251	4100	0	0
T13	41150	21235	0	0
T14	5091	4670	0	0
T15	3064	2640	0	0
T16	2014	915	0	0
T17	403371	200401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	97542194	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	97542194	0	0
T1	51645	26155	0	0
T2	860173	230164	0	0
T3	36141	7521	0	0
T4	3175	696	0	0
T5	4251	2374	0	0
T13	41150	8674	0	0
T14	5091	2455	0	0
T15	3064	1543	0	0
T16	2014	915	0	0
T17	403371	937855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1604548	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1604548	0	0
T1	51645	1059	0	0
T2	860173	10296	0	0
T3	36141	207	0	0
T4	3175	29	0	0
T5	4251	50	0	0
T13	41150	234	0	0
T14	5091	105	0	0
T15	3064	38	0	0
T16	2014	37	0	0
T17	403371	42659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3481258	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3481258	0	0
T1	51645	1059	0	0
T2	860173	10775	0	0
T3	36141	225	0	0
T4	3175	29	0	0
T5	4251	50	0	0
T13	41150	258	0	0
T14	5091	105	0	0
T15	3064	38	0	0
T16	2014	37	0	0
T17	403371	35654	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1574497	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1574497	0	0
T1	51645	775	0	0
T2	860173	11412	0	0
T3	36141	236	0	0
T4	3175	14	0	0
T5	4251	34	0	0
T13	41150	1926	0	0
T14	5091	102	0	0
T15	3064	37	0	0
T16	2014	36	0	0
T17	403371	40477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3513623	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3513623	0	0
T1	51645	775	0	0
T2	860173	11664	0	0
T3	36141	315	0	0
T4	3175	32	0	0
T5	4251	34	0	0
T13	41150	1547	0	0
T14	5091	102	0	0
T15	3064	37	0	0
T16	2014	36	0	0
T17	403371	43863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1619238	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1619238	0	0
T1	51645	1000	0	0
T2	860173	8078	0	0
T3	36141	193	0	0
T4	3175	26	0	0
T5	4251	42	0	0
T13	41150	192	0	0
T14	5091	101	0	0
T15	3064	39	0	0
T16	2014	40	0	0
T17	403371	37307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3656739	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3656739	0	0
T1	51645	1000	0	0
T2	860173	7832	0	0
T3	36141	197	0	0
T4	3175	9	0	0
T5	4251	42	0	0
T13	41150	222	0	0
T14	5091	101	0	0
T15	3064	39	0	0
T16	2014	40	0	0
T17	403371	44250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1604817	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1604817	0	0
T1	51645	743	0	0
T2	860173	10473	0	0
T3	36141	186	0	0
T4	3175	18	0	0
T5	4251	41	0	0
T13	41150	230	0	0
T14	5091	74	0	0
T15	3064	35	0	0
T16	2014	34	0	0
T17	403371	39936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3537822	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3537822	0	0
T1	51645	743	0	0
T2	860173	10734	0	0
T3	36141	224	0	0
T4	3175	18	0	0
T5	4251	41	0	0
T13	41150	126	0	0
T14	5091	74	0	0
T15	3064	35	0	0
T16	2014	34	0	0
T17	403371	39200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1620104	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1620104	0	0
T1	51645	838	0	0
T2	860173	7134	0	0
T3	36141	301	0	0
T4	3175	38	0	0
T5	4251	42	0	0
T13	41150	281	0	0
T14	5091	99	0	0
T15	3064	22	0	0
T16	2014	37	0	0
T17	403371	32698	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3869460	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3869460	0	0
T1	51645	838	0	0
T2	860173	8029	0	0
T3	36141	271	0	0
T4	3175	21	0	0
T5	4251	42	0	0
T13	41150	185	0	0
T14	5091	99	0	0
T15	3064	22	0	0
T16	2014	37	0	0
T17	403371	30040	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1590315	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1590315	0	0
T1	51645	557	0	0
T2	860173	5921	0	0
T3	36141	246	0	0
T4	3175	24	0	0
T5	4251	38	0	0
T13	41150	259	0	0
T14	5091	96	0	0
T15	3064	27	0	0
T16	2014	33	0	0
T17	403371	32875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3275474	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3275474	0	0
T1	51645	557	0	0
T2	860173	6010	0	0
T3	36141	218	0	0
T4	3175	63	0	0
T5	4251	38	0	0
T13	41150	184	0	0
T14	5091	96	0	0
T15	3064	27	0	0
T16	2014	33	0	0
T17	403371	37451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1624630	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1624630	0	0
T1	51645	557	0	0
T2	860173	10856	0	0
T3	36141	292	0	0
T4	3175	42	0	0
T5	4251	42	0	0
T13	41150	313	0	0
T14	5091	89	0	0
T15	3064	32	0	0
T16	2014	29	0	0
T17	403371	39186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3694307	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3694307	0	0
T1	51645	557	0	0
T2	860173	10984	0	0
T3	36141	266	0	0
T4	3175	33	0	0
T5	4251	42	0	0
T13	41150	246	0	0
T14	5091	89	0	0
T15	3064	32	0	0
T16	2014	29	0	0
T17	403371	31924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1624261	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1624261	0	0
T1	51645	835	0	0
T2	860173	11043	0	0
T3	36141	292	0	0
T4	3175	37	0	0
T5	4251	51	0	0
T13	41150	207	0	0
T14	5091	93	0	0
T15	3064	23	0	0
T16	2014	36	0	0
T17	403371	35444	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	4301343	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	4301343	0	0
T1	51645	835	0	0
T2	860173	10844	0	0
T3	36141	215	0	0
T4	3175	24	0	0
T5	4251	51	0	0
T13	41150	166	0	0
T14	5091	93	0	0
T15	3064	23	0	0
T16	2014	36	0	0
T17	403371	31606	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1597038	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1597038	0	0
T1	51645	536	0	0
T2	860173	7212	0	0
T3	36141	354	0	0
T4	3175	17	0	0
T5	4251	45	0	0
T13	41150	353	0	0
T14	5091	89	0	0
T15	3064	30	0	0
T16	2014	35	0	0
T17	403371	27845	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3844828	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3844828	0	0
T1	51645	536	0	0
T2	860173	8372	0	0
T3	36141	309	0	0
T4	3175	29	0	0
T5	4251	45	0	0
T13	41150	180	0	0
T14	5091	89	0	0
T15	3064	30	0	0
T16	2014	35	0	0
T17	403371	28678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1608386	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1608386	0	0
T1	51645	1077	0	0
T2	860173	6029	0	0
T3	36141	281	0	0
T4	3175	6	0	0
T5	4251	57	0	0
T13	41150	258	0	0
T14	5091	84	0	0
T15	3064	36	0	0
T16	2014	32	0	0
T17	403371	36461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3379400	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3379400	0	0
T1	51645	1077	0	0
T2	860173	5474	0	0
T3	36141	350	0	0
T4	3175	1	0	0
T5	4251	57	0	0
T13	41150	182	0	0
T14	5091	84	0	0
T15	3064	36	0	0
T16	2014	32	0	0
T17	403371	35062	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1626460	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1626460	0	0
T1	51645	551	0	0
T2	860173	8221	0	0
T3	36141	293	0	0
T4	3175	17	0	0
T5	4251	32	0	0
T13	41150	248	0	0
T14	5091	95	0	0
T15	3064	25	0	0
T16	2014	27	0	0
T17	403371	31390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3517099	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3517099	0	0
T1	51645	551	0	0
T2	860173	7477	0	0
T3	36141	245	0	0
T4	3175	31	0	0
T5	4251	32	0	0
T13	41150	234	0	0
T14	5091	95	0	0
T15	3064	25	0	0
T16	2014	27	0	0
T17	403371	33541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1572535	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1572535	0	0
T1	51645	546	0	0
T2	860173	9467	0	0
T3	36141	261	0	0
T4	3175	43	0	0
T5	4251	46	0	0
T13	41150	317	0	0
T14	5091	85	0	0
T15	3064	32	0	0
T16	2014	37	0	0
T17	403371	40412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3652873	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3652873	0	0
T1	51645	546	0	0
T2	860173	9687	0	0
T3	36141	334	0	0
T4	3175	16	0	0
T5	4251	46	0	0
T13	41150	306	0	0
T14	5091	85	0	0
T15	3064	32	0	0
T16	2014	37	0	0
T17	403371	37031	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1619114	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1619114	0	0
T1	51645	543	0	0
T2	860173	5007	0	0
T3	36141	342	0	0
T4	3175	34	0	0
T5	4251	60	0	0
T13	41150	204	0	0
T14	5091	94	0	0
T15	3064	27	0	0
T16	2014	44	0	0
T17	403371	31007	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	2996964	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	2996964	0	0
T1	51645	543	0	0
T2	860173	4825	0	0
T3	36141	341	0	0
T4	3175	30	0	0
T5	4251	60	0	0
T13	41150	143	0	0
T14	5091	94	0	0
T15	3064	27	0	0
T16	2014	44	0	0
T17	403371	30887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1596261	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1596261	0	0
T1	51645	557	0	0
T2	860173	12523	0	0
T3	36141	265	0	0
T4	3175	30	0	0
T5	4251	35	0	0
T13	41150	188	0	0
T14	5091	88	0	0
T15	3064	35	0	0
T16	2014	26	0	0
T17	403371	31155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3020689	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3020689	0	0
T1	51645	557	0	0
T2	860173	10167	0	0
T3	36141	263	0	0
T4	3175	44	0	0
T5	4251	35	0	0
T13	41150	164	0	0
T14	5091	88	0	0
T15	3064	35	0	0
T16	2014	26	0	0
T17	403371	33368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1642371	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1642371	0	0
T1	51645	1090	0	0
T2	860173	9792	0	0
T3	36141	262	0	0
T4	3175	42	0	0
T5	4251	49	0	0
T13	41150	254	0	0
T14	5091	98	0	0
T15	3064	34	0	0
T16	2014	36	0	0
T17	403371	38180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3841915	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3841915	0	0
T1	51645	1090	0	0
T2	860173	11982	0	0
T3	36141	215	0	0
T4	3175	13	0	0
T5	4251	49	0	0
T13	41150	168	0	0
T14	5091	98	0	0
T15	3064	34	0	0
T16	2014	36	0	0
T17	403371	41609	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1642877	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1642877	0	0
T1	51645	1040	0	0
T2	860173	12404	0	0
T3	36141	261	0	0
T4	3175	31	0	0
T5	4251	47	0	0
T13	41150	2681	0	0
T14	5091	78	0	0
T15	3064	21	0	0
T16	2014	32	0	0
T17	403371	38130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	4306488	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	4306488	0	0
T1	51645	1040	0	0
T2	860173	8764	0	0
T3	36141	246	0	0
T4	3175	7	0	0
T5	4251	47	0	0
T13	41150	1950	0	0
T14	5091	78	0	0
T15	3064	21	0	0
T16	2014	32	0	0
T17	403371	40237	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1616435	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1616435	0	0
T1	51645	1055	0	0
T2	860173	12338	0	0
T3	36141	289	0	0
T4	3175	50	0	0
T5	4251	39	0	0
T13	41150	256	0	0
T14	5091	75	0	0
T15	3064	31	0	0
T16	2014	37	0	0
T17	403371	31285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	4062786	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	4062786	0	0
T1	51645	1055	0	0
T2	860173	11590	0	0
T3	36141	285	0	0
T4	3175	22	0	0
T5	4251	39	0	0
T13	41150	211	0	0
T14	5091	75	0	0
T15	3064	31	0	0
T16	2014	37	0	0
T17	403371	36983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1608505	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1608505	0	0
T1	51645	607	0	0
T2	860173	9466	0	0
T3	36141	333	0	0
T4	3175	32	0	0
T5	4251	43	0	0
T13	41150	266	0	0
T14	5091	106	0	0
T15	3064	33	0	0
T16	2014	31	0	0
T17	403371	29756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	4241379	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	4241379	0	0
T1	51645	607	0	0
T2	860173	8599	0	0
T3	36141	274	0	0
T4	3175	29	0	0
T5	4251	43	0	0
T13	41150	264	0	0
T14	5091	106	0	0
T15	3064	33	0	0
T16	2014	31	0	0
T17	403371	30038	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1663652	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1663652	0	0
T1	51645	777	0	0
T2	860173	5500	0	0
T3	36141	254	0	0
T4	3175	0	0	0
T5	4251	51	0	0
T13	41150	328	0	0
T14	5091	101	0	0
T15	3064	36	0	0
T16	2014	30	0	0
T17	403371	36291	0	0
T18	0	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3801490	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3801490	0	0
T1	51645	777	0	0
T2	860173	3518	0	0
T3	36141	238	0	0
T4	3175	0	0	0
T5	4251	51	0	0
T13	41150	251	0	0
T14	5091	101	0	0
T15	3064	36	0	0
T16	2014	30	0	0
T17	403371	39220	0	0
T18	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1595294	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1595294	0	0
T1	51645	738	0	0
T2	860173	9175	0	0
T3	36141	346	0	0
T4	3175	12	0	0
T5	4251	65	0	0
T13	41150	259	0	0
T14	5091	95	0	0
T15	3064	32	0	0
T16	2014	26	0	0
T17	403371	26395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3469424	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3469424	0	0
T1	51645	738	0	0
T2	860173	8495	0	0
T3	36141	307	0	0
T4	3175	29	0	0
T5	4251	65	0	0
T13	41150	143	0	0
T14	5091	95	0	0
T15	3064	32	0	0
T16	2014	26	0	0
T17	403371	25128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1573715	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1573715	0	0
T1	51645	1141	0	0
T2	860173	7339	0	0
T3	36141	303	0	0
T4	3175	17	0	0
T5	4251	49	0	0
T13	41150	302	0	0
T14	5091	87	0	0
T15	3064	33	0	0
T16	2014	30	0	0
T17	403371	27909	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3233152	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3233152	0	0
T1	51645	1141	0	0
T2	860173	9335	0	0
T3	36141	266	0	0
T4	3175	35	0	0
T5	4251	49	0	0
T13	41150	197	0	0
T14	5091	87	0	0
T15	3064	33	0	0
T16	2014	30	0	0
T17	403371	32411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1542723	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1542723	0	0
T1	51645	1048	0	0
T2	860173	7165	0	0
T3	36141	316	0	0
T4	3175	4	0	0
T5	4251	45	0	0
T13	41150	254	0	0
T14	5091	82	0	0
T15	3064	21	0	0
T16	2014	40	0	0
T17	403371	34565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3266970	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3266970	0	0
T1	51645	1047	0	0
T2	860173	8783	0	0
T3	36141	303	0	0
T4	3175	17	0	0
T5	4251	45	0	0
T13	41150	215	0	0
T14	5091	82	0	0
T15	3064	21	0	0
T16	2014	40	0	0
T17	403371	30157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1597079	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1597079	0	0
T1	51645	1027	0	0
T2	860173	6351	0	0
T3	36141	402	0	0
T4	3175	13	0	0
T5	4251	42	0	0
T13	41150	248	0	0
T14	5091	80	0	0
T15	3064	29	0	0
T16	2014	48	0	0
T17	403371	37013	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	2837434	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	2837434	0	0
T1	51645	1027	0	0
T2	860173	5036	0	0
T3	36141	354	0	0
T4	3175	16	0	0
T5	4251	42	0	0
T13	41150	176	0	0
T14	5091	80	0	0
T15	3064	29	0	0
T16	2014	48	0	0
T17	403371	26863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1565818	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1565818	0	0
T1	51645	876	0	0
T2	860173	4318	0	0
T3	36141	356	0	0
T4	3175	6	0	0
T5	4251	46	0	0
T13	41150	232	0	0
T14	5091	94	0	0
T15	3064	22	0	0
T16	2014	24	0	0
T17	403371	36900	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3500475	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3500475	0	0
T1	51645	876	0	0
T2	860173	3836	0	0
T3	36141	348	0	0
T4	3175	14	0	0
T5	4251	46	0	0
T13	41150	216	0	0
T14	5091	94	0	0
T15	3064	22	0	0
T16	2014	24	0	0
T17	403371	35867	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1669282	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1669282	0	0
T1	51645	1051	0	0
T2	860173	9472	0	0
T3	36141	250	0	0
T4	3175	12	0	0
T5	4251	36	0	0
T13	41150	291	0	0
T14	5091	89	0	0
T15	3064	24	0	0
T16	2014	29	0	0
T17	403371	35961	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3270870	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3270870	0	0
T1	51645	1051	0	0
T2	860173	8959	0	0
T3	36141	234	0	0
T4	3175	19	0	0
T5	4251	36	0	0
T13	41150	269	0	0
T14	5091	89	0	0
T15	3064	24	0	0
T16	2014	29	0	0
T17	403371	39342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1634413	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1634413	0	0
T1	51645	571	0	0
T2	860173	7499	0	0
T3	36141	288	0	0
T4	3175	10	0	0
T5	4251	44	0	0
T13	41150	230	0	0
T14	5091	81	0	0
T15	3064	23	0	0
T16	2014	36	0	0
T17	403371	37407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	2915423	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	2915423	0	0
T1	51645	571	0	0
T2	860173	7935	0	0
T3	36141	298	0	0
T4	3175	15	0	0
T5	4251	44	0	0
T13	41150	207	0	0
T14	5091	81	0	0
T15	3064	23	0	0
T16	2014	36	0	0
T17	403371	32910	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	1596268	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	1596268	0	0
T1	51645	1291	0	0
T2	860173	11513	0	0
T3	36141	328	0	0
T4	3175	31	0	0
T5	4251	44	0	0
T13	41150	365	0	0
T14	5091	94	0	0
T15	3064	31	0	0
T16	2014	29	0	0
T17	403371	35389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	337613338	3977329	0	0
DepthKnown_A	337613338	337487027	0	0
RvalidKnown_A	337613338	337487027	0	0
WreadyKnown_A	337613338	337487027	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	3977329	0	0
T1	51645	1291	0	0
T2	860173	9712	0	0
T3	36141	328	0	0
T4	3175	40	0	0
T5	4251	44	0	0
T13	41150	264	0	0
T14	5091	94	0	0
T15	3064	31	0	0
T16	2014	29	0	0
T17	403371	34278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337613338	337487027	0	0
T1	51645	50861	0	0
T2	860173	860150	0	0
T3	36141	36114	0	0
T4	3175	2987	0	0
T5	4251	4236	0	0
T13	41150	41088	0	0
T14	5091	5052	0	0
T15	3064	3000	0	0
T16	2014	1996	0	0
T17	403371	403367	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0