Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1566958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245605

1

T1

105

T2

40

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613815	1			T1	237		T2	77		T3	45
values[0x0]	583915	1			T1	227		T2	85		T3	42
values[0x1]	614833	1			T1	218		T2	96		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1213437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599126

1

T1

236

T2

96

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8380	1			T3	2		T5	1		T4	2
valid_sources[0x01]	7024	1			T1	6		T3	1		T4	2
valid_sources[0x02]	7668	1			T5	3		T4	2		T20	5
valid_sources[0x03]	6869	1			T3	1		T4	14		T22	1
valid_sources[0x04]	8197	1			T5	1		T22	2		T20	3
valid_sources[0x05]	7396	1			T2	4		T5	1		T4	2
valid_sources[0x06]	6830	1			T4	1		T20	6		T23	2
valid_sources[0x07]	7020	1			T3	2		T4	2		T20	4
valid_sources[0x08]	6923	1			T2	6		T3	1		T5	2
valid_sources[0x09]	7776	1			T3	1		T5	2		T4	4
valid_sources[0x0a]	6608	1			T5	1		T4	1		T20	7
valid_sources[0x0b]	6236	1			T5	1		T4	1		T20	2
valid_sources[0x0c]	7901	1			T5	2		T4	4		T21	4
valid_sources[0x0d]	6205	1			T5	2		T20	3		T24	5
valid_sources[0x0e]	6515	1			T4	1		T20	4		T23	3
valid_sources[0x0f]	6581	1			T3	2		T5	3		T21	1
valid_sources[0x10]	7407	1			T20	8		T23	2		T24	2
valid_sources[0x11]	7802	1			T3	1		T5	3		T20	6
valid_sources[0x12]	6522	1			T3	2		T5	1		T4	7
valid_sources[0x13]	7380	1			T2	10		T3	1		T5	1
valid_sources[0x14]	7359	1			T4	3		T20	9		T24	7
valid_sources[0x15]	7066	1			T1	84		T5	3		T4	1
valid_sources[0x16]	7113	1			T5	1		T4	1		T21	2
valid_sources[0x17]	6899	1			T5	1		T4	2		T20	5
valid_sources[0x18]	6824	1			T3	1		T5	2		T4	1
valid_sources[0x19]	8412	1			T2	5		T5	1		T4	2
valid_sources[0x1a]	7140	1			T5	2		T4	2		T20	3
valid_sources[0x1b]	6671	1			T5	2		T4	1		T21	5
valid_sources[0x1c]	7378	1			T5	2		T4	1		T20	7
valid_sources[0x1d]	7069	1			T4	2		T20	5		T23	1
valid_sources[0x1e]	6782	1			T4	1		T20	1		T23	2
valid_sources[0x1f]	7517	1			T5	4		T4	2		T21	2
valid_sources[0x20]	6431	1			T5	3		T4	3		T20	3
valid_sources[0x21]	6834	1			T2	5		T3	2		T4	1
valid_sources[0x22]	6426	1			T3	2		T4	1		T20	5
valid_sources[0x23]	6829	1			T5	4		T4	2		T21	2
valid_sources[0x24]	7488	1			T2	2		T3	2		T5	3
valid_sources[0x25]	6542	1			T21	1		T20	3		T23	4
valid_sources[0x26]	7334	1			T5	1		T4	8		T20	10
valid_sources[0x27]	7285	1			T4	2		T22	2		T20	7
valid_sources[0x28]	8543	1			T2	3		T3	2		T4	4
valid_sources[0x29]	6463	1			T3	2		T4	2		T22	1
valid_sources[0x2a]	7333	1			T2	8		T5	1		T20	8
valid_sources[0x2b]	7961	1			T5	6		T4	4		T20	3
valid_sources[0x2c]	6709	1			T4	2		T21	2		T17	11
valid_sources[0x2d]	7175	1			T3	3		T5	1		T4	1
valid_sources[0x2e]	7746	1			T20	5		T23	6		T24	34
valid_sources[0x2f]	7491	1			T2	6		T5	1		T4	4
valid_sources[0x30]	6559	1			T3	1		T5	2		T20	3
valid_sources[0x31]	6739	1			T2	6		T4	1		T22	1
valid_sources[0x32]	7607	1			T2	8		T5	1		T21	2
valid_sources[0x33]	7689	1			T5	4		T4	1		T22	1
valid_sources[0x34]	5971	1			T2	1		T5	1		T22	1
valid_sources[0x35]	8745	1			T3	1		T5	5		T4	4
valid_sources[0x36]	7778	1			T2	4		T4	3		T20	10
valid_sources[0x37]	6607	1			T5	3		T4	4		T20	8
valid_sources[0x38]	7532	1			T3	3		T5	1		T4	2
valid_sources[0x39]	7082	1			T4	1		T20	7		T23	6
valid_sources[0x3a]	7352	1			T5	1		T22	2		T20	4
valid_sources[0x3b]	7023	1			T5	1		T4	2		T21	3
valid_sources[0x3c]	6680	1			T4	6		T21	2		T22	1
valid_sources[0x3d]	7505	1			T3	3		T5	1		T4	2
valid_sources[0x3e]	6694	1			T5	2		T4	1		T22	2
valid_sources[0x3f]	6944	1			T2	7		T5	3		T4	12
valid_sources[0x40]	7950	1			T2	4		T3	1		T5	8
valid_sources[0x41]	6545	1			T3	2		T4	5		T22	2
valid_sources[0x42]	7014	1			T4	6		T22	3		T20	10
valid_sources[0x43]	7477	1			T5	1		T21	1		T20	5
valid_sources[0x44]	7229	1			T4	4		T22	1		T20	6
valid_sources[0x45]	6986	1			T20	6		T24	16		T26	1
valid_sources[0x46]	7719	1			T3	1		T4	1		T21	2
valid_sources[0x47]	6742	1			T1	69		T22	1		T20	8
valid_sources[0x48]	7109	1			T2	8		T3	3		T5	2
valid_sources[0x49]	6816	1			T3	2		T5	2		T4	2
valid_sources[0x4a]	6528	1			T4	5		T20	6		T23	3
valid_sources[0x4b]	6129	1			T5	2		T22	4		T20	8
valid_sources[0x4c]	6538	1			T5	1		T4	2		T22	2
valid_sources[0x4d]	8613	1			T5	5		T4	4		T22	1
valid_sources[0x4e]	6253	1			T5	1		T22	1		T20	5
valid_sources[0x4f]	6703	1			T5	1		T4	1		T20	3
valid_sources[0x50]	6646	1			T20	4		T23	5		T24	12
valid_sources[0x51]	7284	1			T2	3		T5	3		T4	4
valid_sources[0x52]	6713	1			T5	4		T4	2		T21	2
valid_sources[0x53]	7474	1			T3	1		T5	2		T22	1
valid_sources[0x54]	6802	1			T4	3		T21	1		T20	1
valid_sources[0x55]	6566	1			T3	1		T5	2		T4	2
valid_sources[0x56]	6674	1			T5	1		T4	2		T21	3
valid_sources[0x57]	8850	1			T2	5		T5	2		T4	1
valid_sources[0x58]	6344	1			T2	1		T3	2		T4	1
valid_sources[0x59]	6951	1			T5	3		T4	10		T21	2
valid_sources[0x5a]	6591	1			T5	1		T20	11		T23	3
valid_sources[0x5b]	6845	1			T5	2		T4	2		T22	2
valid_sources[0x5c]	7647	1			T5	3		T4	5		T20	1
valid_sources[0x5d]	6295	1			T5	5		T20	3		T23	3
valid_sources[0x5e]	6670	1			T3	1		T5	2		T4	3
valid_sources[0x5f]	7503	1			T21	2		T17	10		T20	5
valid_sources[0x60]	6710	1			T5	1		T4	2		T21	1
valid_sources[0x61]	6786	1			T5	1		T4	1		T20	6
valid_sources[0x62]	6719	1			T3	1		T20	3		T23	2
valid_sources[0x63]	7559	1			T2	3		T3	1		T5	2
valid_sources[0x64]	7476	1			T5	1		T4	1		T22	1
valid_sources[0x65]	7157	1			T3	1		T4	2		T22	2
valid_sources[0x66]	7339	1			T5	2		T4	6		T21	6
valid_sources[0x67]	6646	1			T5	1		T20	5		T23	1
valid_sources[0x68]	7176	1			T2	5		T3	1		T4	2
valid_sources[0x69]	8991	1			T3	1		T5	2		T4	3
valid_sources[0x6a]	6976	1			T5	1		T21	3		T20	5
valid_sources[0x6b]	7377	1			T5	2		T4	8		T22	4
valid_sources[0x6c]	6952	1			T5	1		T4	6		T21	1
valid_sources[0x6d]	6297	1			T2	8		T3	1		T5	1
valid_sources[0x6e]	6720	1			T2	3		T4	6		T20	7
valid_sources[0x6f]	6950	1			T3	1		T5	4		T4	9
valid_sources[0x70]	7851	1			T5	3		T4	5		T20	2
valid_sources[0x71]	7435	1			T5	1		T4	1		T22	1
valid_sources[0x72]	6258	1			T2	7		T5	1		T4	6
valid_sources[0x73]	6469	1			T3	3		T5	3		T22	3
valid_sources[0x74]	7737	1			T2	2		T20	6		T23	4
valid_sources[0x75]	7041	1			T3	1		T5	1		T4	1
valid_sources[0x76]	7096	1			T5	2		T22	2		T20	6
valid_sources[0x77]	8043	1			T2	1		T5	1		T22	1
valid_sources[0x78]	7321	1			T3	1		T5	5		T4	2
valid_sources[0x79]	6547	1			T4	7		T20	5		T23	1
valid_sources[0x7a]	7968	1			T3	2		T5	1		T4	2
valid_sources[0x7b]	6817	1			T4	5		T22	5		T17	36
valid_sources[0x7c]	7081	1			T2	6		T3	2		T5	3
valid_sources[0x7d]	6633	1			T3	2		T4	3		T20	4
valid_sources[0x7e]	7377	1			T3	2		T20	7		T23	2
valid_sources[0x7f]	6930	1			T2	6		T4	2		T20	5
valid_sources[0x80]	6510	1			T2	3		T5	2		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25797

1

T1

12

T2

6

T3

4

values[0x0]

all_enables

biggest_size

193908

1

T1

84

T2

30

T3

18

values[0x1]

all_enables

biggest_size

25900

1

T1

9

T2

4

T3

4