Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	329228596	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329228596	0	0
T1	969920	18048	0	0
T2	315280	8594	0	0
T3	43736	672	0	0
T4	18772880	353653	0	0
T5	840840	33933	0	0
T17	7039368	208818	0	0
T18	0	648	0	0
T20	164360	6842	0	0
T21	10453576	171720	0	0
T22	7901544	251018	0	0
T23	55104	2828	0	0
T24	0	54797	0	0
T25	0	172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	969920	967512	0	0
T2	315280	312872	0	0
T3	43736	38920	0	0
T4	18772880	18766664	0	0
T5	840840	830536	0	0
T17	7039368	7037408	0	0
T20	164360	162904	0	0
T21	10453576	10452456	0	0
T22	7901544	7900648	0	0
T23	55104	52696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	969920	967512	0	0
T2	315280	312872	0	0
T3	43736	38920	0	0
T4	18772880	18766664	0	0
T5	840840	830536	0	0
T17	7039368	7037408	0	0
T20	164360	162904	0	0
T21	10453576	10452456	0	0
T22	7901544	7900648	0	0
T23	55104	52696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	969920	967512	0	0
T2	315280	312872	0	0
T3	43736	38920	0	0
T4	18772880	18766664	0	0
T5	840840	830536	0	0
T17	7039368	7037408	0	0
T20	164360	162904	0	0
T21	10453576	10452456	0	0
T22	7901544	7900648	0	0
T23	55104	52696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T17	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	114249979	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	114249979	0	0
T1	17320	7972	0	0
T2	5630	2208	0	0
T3	781	264	0	0
T4	335230	141173	0	0
T5	15015	14344	0	0
T17	125703	123651	0	0
T20	2935	2655	0	0
T21	186671	77861	0	0
T22	141099	139352	0	0
T23	984	707	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	89117789	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	89117789	0	0
T1	17320	2366	0	0
T2	5630	2089	0	0
T3	781	136	0	0
T4	335230	51786	0	0
T5	15015	7688	0	0
T17	125703	42225	0	0
T20	2935	1397	0	0
T21	186671	20622	0	0
T22	141099	55493	0	0
T23	984	707	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1348919	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1348919	0	0
T1	17320	190	0	0
T2	5630	0	0	0
T3	781	2	0	0
T4	335230	8339	0	0
T5	15015	363	0	0
T17	125703	33	0	0
T18	0	11	0	0
T20	2935	61	0	0
T21	186671	1153	0	0
T22	141099	6	0	0
T23	984	0	0	0
T25	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2866961	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2866961	0	0
T1	17320	77	0	0
T2	5630	0	0	0
T3	781	2	0	0
T4	335230	3774	0	0
T5	15015	362	0	0
T17	125703	2708	0	0
T18	0	11	0	0
T20	2935	61	0	0
T21	186671	481	0	0
T22	141099	936	0	0
T23	984	0	0	0
T25	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1381875	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1381875	0	0
T1	17320	218	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	5746	0	0
T5	15015	456	0	0
T17	125703	28	0	0
T18	0	11	0	0
T20	2935	49	0	0
T21	186671	1597	0	0
T22	141099	11	0	0
T23	984	0	0	0
T25	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3412788	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3412788	0	0
T1	17320	132	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	2446	0	0
T5	15015	456	0	0
T17	125703	1357	0	0
T18	0	11	0	0
T20	2935	49	0	0
T21	186671	666	0	0
T22	141099	2436	0	0
T23	984	0	0	0
T25	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1407320	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1407320	0	0
T1	17320	177	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	1670	0	0
T5	15015	176	0	0
T17	125703	52	0	0
T18	0	11	0	0
T20	2935	51	0	0
T21	186671	2740	0	0
T22	141099	37	0	0
T23	984	0	0	0
T24	0	2473	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3453601	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3453601	0	0
T1	17320	44	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	785	0	0
T5	15015	176	0	0
T17	125703	1810	0	0
T18	0	11	0	0
T20	2935	51	0	0
T21	186671	1117	0	0
T22	141099	2942	0	0
T23	984	0	0	0
T24	0	3340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1426926	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1426926	0	0
T1	17320	299	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	3504	0	0
T5	15015	189	0	0
T17	125703	27	0	0
T18	0	10	0	0
T20	2935	38	0	0
T21	186671	1200	0	0
T22	141099	42	0	0
T23	984	0	0	0
T25	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3188888	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3188888	0	0
T1	17320	125	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	1581	0	0
T5	15015	189	0	0
T17	125703	2224	0	0
T18	0	10	0	0
T20	2935	38	0	0
T21	186671	1097	0	0
T22	141099	2131	0	0
T23	984	0	0	0
T25	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1350457	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1350457	0	0
T1	17320	251	0	0
T2	5630	0	0	0
T3	781	9	0	0
T4	335230	1645	0	0
T5	15015	211	0	0
T17	125703	28	0	0
T18	0	14	0	0
T20	2935	50	0	0
T21	186671	1334	0	0
T22	141099	29	0	0
T23	984	0	0	0
T24	0	2317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3421460	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3421460	0	0
T1	17320	74	0	0
T2	5630	0	0	0
T3	781	9	0	0
T4	335230	777	0	0
T5	15015	211	0	0
T17	125703	1847	0	0
T18	0	14	0	0
T20	2935	50	0	0
T21	186671	1699	0	0
T22	141099	3777	0	0
T23	984	0	0	0
T24	0	2421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1432429	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1432429	0	0
T1	17320	215	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	4935	0	0
T5	15015	192	0	0
T17	125703	13	0	0
T18	0	12	0	0
T20	2935	51	0	0
T21	186671	1810	0	0
T22	141099	41	0	0
T23	984	0	0	0
T25	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3492832	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3492832	0	0
T1	17320	126	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	2647	0	0
T5	15015	192	0	0
T17	125703	582	0	0
T18	0	12	0	0
T20	2935	51	0	0
T21	186671	493	0	0
T22	141099	1985	0	0
T23	984	0	0	0
T25	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1387254	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1387254	0	0
T1	17320	228	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	7599	0	0
T5	15015	174	0	0
T17	125703	15	0	0
T18	0	10	0	0
T20	2935	47	0	0
T21	186671	1618	0	0
T22	141099	24	0	0
T23	984	0	0	0
T24	0	2357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2998182	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2998182	0	0
T1	17320	86	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	3280	0	0
T5	15015	174	0	0
T17	125703	711	0	0
T18	0	10	0	0
T20	2935	47	0	0
T21	186671	922	0	0
T22	141099	2857	0	0
T23	984	0	0	0
T24	0	2135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1431600	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1431600	0	0
T1	17320	207	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	9552	0	0
T5	15015	168	0	0
T17	125703	19	0	0
T18	0	6	0	0
T20	2935	56	0	0
T21	186671	392	0	0
T22	141099	43	0	0
T23	984	0	0	0
T25	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2413596	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2413596	0	0
T1	17320	123	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	4376	0	0
T5	15015	168	0	0
T17	125703	1375	0	0
T18	0	6	0	0
T20	2935	56	0	0
T21	186671	321	0	0
T22	141099	3417	0	0
T23	984	0	0	0
T25	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1386125	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1386125	0	0
T1	17320	193	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	3274	0	0
T5	15015	187	0	0
T17	125703	14	0	0
T18	0	9	0	0
T20	2935	65	0	0
T21	186671	1192	0	0
T22	141099	27	0	0
T23	984	0	0	0
T25	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2895996	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2895996	0	0
T1	17320	124	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	1392	0	0
T5	15015	187	0	0
T17	125703	3	0	0
T18	0	9	0	0
T20	2935	65	0	0
T21	186671	1180	0	0
T22	141099	1440	0	0
T23	984	0	0	0
T25	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1371089	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1371089	0	0
T1	17320	119	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	5096	0	0
T5	15015	189	0	0
T17	125703	12	0	0
T18	0	15	0	0
T20	2935	44	0	0
T21	186671	1936	0	0
T22	141099	9	0	0
T23	984	0	0	0
T24	0	1983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3116982	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3116982	0	0
T1	17320	67	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	3153	0	0
T5	15015	189	0	0
T17	125703	654	0	0
T18	0	15	0	0
T20	2935	44	0	0
T21	186671	7	0	0
T22	141099	349	0	0
T23	984	0	0	0
T24	0	2100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1378009	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1378009	0	0
T1	17320	205	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	1439	0	0
T5	15015	207	0	0
T17	125703	25	0	0
T18	0	8	0	0
T20	2935	48	0	0
T21	186671	1397	0	0
T22	141099	24	0	0
T23	984	0	0	0
T24	0	1674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3208206	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3208206	0	0
T1	17320	110	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	697	0	0
T5	15015	207	0	0
T17	125703	598	0	0
T18	0	8	0	0
T20	2935	48	0	0
T21	186671	533	0	0
T22	141099	1515	0	0
T23	984	0	0	0
T24	0	1831	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1398423	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1398423	0	0
T1	17320	151	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	5387	0	0
T5	15015	401	0	0
T17	125703	46	0	0
T18	0	13	0	0
T20	2935	45	0	0
T21	186671	1240	0	0
T22	141099	17	0	0
T23	984	0	0	0
T24	0	2317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3030599	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3030599	0	0
T1	17320	78	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	2374	0	0
T5	15015	401	0	0
T17	125703	3181	0	0
T18	0	13	0	0
T20	2935	45	0	0
T21	186671	687	0	0
T22	141099	926	0	0
T23	984	0	0	0
T24	0	2393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1390913	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1390913	0	0
T1	17320	252	0	0
T2	5630	0	0	0
T3	781	5	0	0
T4	335230	6174	0	0
T5	15015	182	0	0
T17	125703	35	0	0
T18	0	9	0	0
T20	2935	53	0	0
T21	186671	3111	0	0
T22	141099	15	0	0
T23	984	0	0	0
T24	0	1511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3399728	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3399728	0	0
T1	17320	74	0	0
T2	5630	0	0	0
T3	781	5	0	0
T4	335230	2700	0	0
T5	15015	182	0	0
T17	125703	1371	0	0
T18	0	9	0	0
T20	2935	53	0	0
T21	186671	1451	0	0
T22	141099	770	0	0
T23	984	0	0	0
T24	0	1995	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1420651	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1420651	0	0
T1	17320	165	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	3452	0	0
T5	15015	187	0	0
T17	125703	19	0	0
T18	0	12	0	0
T20	2935	55	0	0
T21	186671	2836	0	0
T22	141099	24	0	0
T23	984	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3280318	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3280318	0	0
T1	17320	79	0	0
T2	5630	0	0	0
T3	781	7	0	0
T4	335230	1556	0	0
T5	15015	187	0	0
T17	125703	1548	0	0
T18	0	12	0	0
T20	2935	55	0	0
T21	186671	1421	0	0
T22	141099	786	0	0
T23	984	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1452171	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1452171	0	0
T1	17320	235	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	6419	0	0
T5	15015	180	0	0
T17	125703	30	0	0
T18	0	16	0	0
T20	2935	51	0	0
T21	186671	3585	0	0
T22	141099	15	0	0
T23	984	0	0	0
T25	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3512656	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3512656	0	0
T1	17320	81	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	2718	0	0
T5	15015	180	0	0
T17	125703	1943	0	0
T18	0	16	0	0
T20	2935	51	0	0
T21	186671	513	0	0
T22	141099	1533	0	0
T23	984	0	0	0
T25	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1417439	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1417439	0	0
T1	17320	208	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	4094	0	0
T5	15015	194	0	0
T17	125703	56	0	0
T18	0	10	0	0
T20	2935	45	0	0
T21	186671	1698	0	0
T22	141099	42	0	0
T23	984	0	0	0
T25	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3268546	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3268546	0	0
T1	17320	52	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	1837	0	0
T5	15015	194	0	0
T17	125703	1361	0	0
T18	0	10	0	0
T20	2935	45	0	0
T21	186671	577	0	0
T22	141099	3390	0	0
T23	984	0	0	0
T25	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1382293	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1382293	0	0
T1	17320	131	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	3515	0	0
T5	15015	199	0	0
T17	125703	4	0	0
T18	0	12	0	0
T20	2935	45	0	0
T21	186671	2201	0	0
T22	141099	24	0	0
T23	984	0	0	0
T24	0	2135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2815904	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2815904	0	0
T1	17320	43	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	1489	0	0
T5	15015	199	0	0
T17	125703	1834	0	0
T18	0	12	0	0
T20	2935	45	0	0
T21	186671	729	0	0
T22	141099	2598	0	0
T23	984	0	0	0
T24	0	2195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1381275	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1381275	0	0
T1	17320	160	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	1348	0	0
T5	15015	201	0	0
T17	125703	13	0	0
T18	0	8	0	0
T20	2935	59	0	0
T21	186671	4123	0	0
T22	141099	45	0	0
T23	984	0	0	0
T24	0	2094	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2653048	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2653048	0	0
T1	17320	84	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	781	0	0
T5	15015	201	0	0
T17	125703	1072	0	0
T18	0	8	0	0
T20	2935	59	0	0
T21	186671	1248	0	0
T22	141099	3254	0	0
T23	984	0	0	0
T24	0	2129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1402522	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1402522	0	0
T1	17320	139	0	0
T2	5630	2208	0	0
T3	781	5	0	0
T4	335230	1468	0	0
T5	15015	171	0	0
T17	125703	2	0	0
T18	0	11	0	0
T20	2935	57	0	0
T21	186671	5	0	0
T22	141099	45	0	0
T23	984	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3844158	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3844158	0	0
T1	17320	79	0	0
T2	5630	2089	0	0
T3	781	5	0	0
T4	335230	661	0	0
T5	15015	171	0	0
T17	125703	1274	0	0
T18	0	11	0	0
T20	2935	57	0	0
T21	186671	0	0	0
T22	141099	3714	0	0
T23	984	0	0	0
T25	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1374778	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1374778	0	0
T1	17320	146	0	0
T2	5630	0	0	0
T3	781	8	0	0
T4	335230	1467	0	0
T5	15015	202	0	0
T17	125703	25	0	0
T18	0	18	0	0
T20	2935	40	0	0
T21	186671	2862	0	0
T22	141099	18	0	0
T23	984	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3611093	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3611093	0	0
T1	17320	63	0	0
T2	5630	0	0	0
T3	781	8	0	0
T4	335230	767	0	0
T5	15015	202	0	0
T17	125703	2149	0	0
T18	0	18	0	0
T20	2935	40	0	0
T21	186671	1240	0	0
T22	141099	1295	0	0
T23	984	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1416494	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1416494	0	0
T1	17320	233	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	1502	0	0
T5	15015	270	0	0
T17	125703	22	0	0
T18	0	21	0	0
T20	2935	56	0	0
T21	186671	2461	0	0
T22	141099	17	0	0
T23	984	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3620905	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3620905	0	0
T1	17320	87	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	754	0	0
T5	15015	270	0	0
T17	125703	1187	0	0
T18	0	21	0	0
T20	2935	56	0	0
T21	186671	704	0	0
T22	141099	1614	0	0
T23	984	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1428202	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1428202	0	0
T1	17320	260	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	1522	0	0
T5	15015	186	0	0
T17	125703	17	0	0
T18	0	9	0	0
T20	2935	52	0	0
T21	186671	2519	0	0
T22	141099	36	0	0
T23	984	0	0	0
T24	0	2337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3818837	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3818837	0	0
T1	17320	105	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	773	0	0
T5	15015	186	0	0
T17	125703	416	0	0
T18	0	9	0	0
T20	2935	52	0	0
T21	186671	626	0	0
T22	141099	3758	0	0
T23	984	0	0	0
T24	0	2246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1358339	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1358339	0	0
T1	17320	230	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	1642	0	0
T5	15015	166	0	0
T17	125703	64	0	0
T18	0	15	0	0
T20	2935	45	0	0
T21	186671	3287	0	0
T22	141099	41	0	0
T23	984	0	0	0
T24	0	3724	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2952328	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2952328	0	0
T1	17320	91	0	0
T2	5630	0	0	0
T3	781	6	0	0
T4	335230	668	0	0
T5	15015	166	0	0
T17	125703	3403	0	0
T18	0	15	0	0
T20	2935	45	0	0
T21	186671	83	0	0
T22	141099	2723	0	0
T23	984	0	0	0
T24	0	3669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1362792	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1362792	0	0
T1	17320	149	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	1420	0	0
T5	15015	189	0	0
T17	125703	20	0	0
T18	0	12	0	0
T20	2935	50	0	0
T21	186671	1744	0	0
T22	141099	15	0	0
T23	984	0	0	0
T25	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3166994	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3166994	0	0
T1	17320	75	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	794	0	0
T5	15015	189	0	0
T17	125703	2103	0	0
T18	0	12	0	0
T20	2935	50	0	0
T21	186671	760	0	0
T22	141099	996	0	0
T23	984	0	0	0
T25	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1413528	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1413528	0	0
T1	17320	185	0	0
T2	5630	0	0	0
T3	781	5	0	0
T4	335230	3070	0	0
T5	15015	332	0	0
T17	125703	50	0	0
T18	0	13	0	0
T20	2935	56	0	0
T21	186671	2338	0	0
T22	141099	12	0	0
T23	984	0	0	0
T25	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	4029778	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	4029778	0	0
T1	17320	73	0	0
T2	5630	0	0	0
T3	781	5	0	0
T4	335230	1206	0	0
T5	15015	332	0	0
T17	125703	3423	0	0
T18	0	13	0	0
T20	2935	56	0	0
T21	186671	917	0	0
T22	141099	2291	0	0
T23	984	0	0	0
T25	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1412206	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1412206	0	0
T1	17320	166	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	4998	0	0
T5	15015	193	0	0
T17	125703	18	0	0
T18	0	11	0	0
T20	2935	67	0	0
T21	186671	201	0	0
T22	141099	10	0	0
T23	984	0	0	0
T25	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	3879247	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	3879247	0	0
T1	17320	85	0	0
T2	5630	0	0	0
T3	781	3	0	0
T4	335230	3645	0	0
T5	15015	193	0	0
T17	125703	1291	0	0
T18	0	11	0	0
T20	2935	67	0	0
T21	186671	827	0	0
T22	141099	1336	0	0
T23	984	0	0	0
T25	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	1374901	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	1374901	0	0
T1	17320	232	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	8644	0	0
T5	15015	186	0	0
T17	125703	30	0	0
T18	0	17	0	0
T20	2935	59	0	0
T21	186671	2035	0	0
T22	141099	11	0	0
T23	984	0	0	0
T24	0	1452	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304723356	2818267	0	0
DepthKnown_A	304723356	304603396	0	0
RvalidKnown_A	304723356	304603396	0	0
WreadyKnown_A	304723356	304603396	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	2818267	0	0
T1	17320	129	0	0
T2	5630	0	0	0
T3	781	4	0	0
T4	335230	4142	0	0
T5	15015	186	0	0
T17	125703	800	0	0
T18	0	17	0	0
T20	2935	59	0	0
T21	186671	323	0	0
T22	141099	724	0	0
T23	984	0	0	0
T24	0	1969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304723356	304603396	0	0
T1	17320	17277	0	0
T2	5630	5587	0	0
T3	781	695	0	0
T4	335230	335119	0	0
T5	15015	14831	0	0
T17	125703	125668	0	0
T20	2935	2909	0	0
T21	186671	186651	0	0
T22	141099	141083	0	0
T23	984	941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0