Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1611855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252952

1

T4

66

T1

262

T2

277

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	630835	1			T4	178		T1	570		T2	728
values[0x0]	600633	1			T4	158		T1	549		T2	666
values[0x1]	633339	1			T4	169		T1	538		T2	725

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615760

1

T4

186

T1

584

T2

721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7440	1			T1	2		T2	8		T3	97
valid_sources[0x01]	7230	1			T2	9		T3	5		T21	3
valid_sources[0x02]	7219	1			T2	12		T21	1		T17	14
valid_sources[0x03]	7553	1			T2	14		T5	1		T21	8
valid_sources[0x04]	6491	1			T4	19		T1	10		T2	11
valid_sources[0x05]	7022	1			T1	1		T2	6		T6	3
valid_sources[0x06]	7082	1			T2	9		T21	6		T17	16
valid_sources[0x07]	7147	1			T1	2		T2	2		T5	1
valid_sources[0x08]	7519	1			T1	14		T2	9		T21	7
valid_sources[0x09]	7432	1			T1	6		T2	13		T5	2
valid_sources[0x0a]	6994	1			T1	22		T2	5		T21	16
valid_sources[0x0b]	7379	1			T1	13		T2	13		T5	1
valid_sources[0x0c]	7555	1			T1	1		T2	8		T21	4
valid_sources[0x0d]	6893	1			T1	12		T2	6		T21	5
valid_sources[0x0e]	6346	1			T1	6		T2	9		T21	15
valid_sources[0x0f]	7983	1			T2	7		T5	2		T21	5
valid_sources[0x10]	7580	1			T1	19		T2	7		T21	6
valid_sources[0x11]	6760	1			T4	6		T2	5		T182	12
valid_sources[0x12]	7485	1			T2	6		T22	3		T17	2
valid_sources[0x13]	9177	1			T4	18		T2	9		T17	32
valid_sources[0x14]	7580	1			T2	11		T5	1		T21	3
valid_sources[0x15]	6735	1			T1	4		T2	4		T6	2
valid_sources[0x16]	6910	1			T1	9		T2	5		T5	1
valid_sources[0x17]	6721	1			T1	15		T2	18		T6	3
valid_sources[0x18]	6689	1			T1	15		T2	4		T21	8
valid_sources[0x19]	8251	1			T1	5		T2	4		T21	10
valid_sources[0x1a]	6627	1			T2	13		T5	1		T6	2
valid_sources[0x1b]	7560	1			T1	34		T2	4		T5	2
valid_sources[0x1c]	7402	1			T2	4		T5	1		T6	2
valid_sources[0x1d]	6566	1			T4	14		T1	17		T2	9
valid_sources[0x1e]	7855	1			T1	21		T2	15		T5	1
valid_sources[0x1f]	6485	1			T1	15		T2	9		T6	1
valid_sources[0x20]	7287	1			T1	3		T2	8		T5	1
valid_sources[0x21]	7109	1			T1	17		T2	5		T5	1
valid_sources[0x22]	7477	1			T1	5		T2	9		T5	1
valid_sources[0x23]	6810	1			T1	3		T2	11		T5	1
valid_sources[0x24]	7626	1			T1	10		T2	5		T5	2
valid_sources[0x25]	6770	1			T4	11		T2	12		T21	10
valid_sources[0x26]	7077	1			T4	19		T1	1		T2	10
valid_sources[0x27]	6888	1			T4	19		T1	7		T2	10
valid_sources[0x28]	6928	1			T1	12		T2	4		T21	5
valid_sources[0x29]	7395	1			T1	2		T2	8		T5	1
valid_sources[0x2a]	7627	1			T2	4		T5	1		T21	5
valid_sources[0x2b]	6837	1			T2	9		T3	156		T21	8
valid_sources[0x2c]	6697	1			T1	3		T2	5		T5	1
valid_sources[0x2d]	7152	1			T4	19		T1	10		T2	3
valid_sources[0x2e]	9097	1			T4	15		T1	15		T2	7
valid_sources[0x2f]	6723	1			T1	12		T2	12		T21	10
valid_sources[0x30]	6644	1			T1	1		T2	7		T21	5
valid_sources[0x31]	7656	1			T1	5		T2	8		T5	2
valid_sources[0x32]	6832	1			T1	2		T2	3		T6	7
valid_sources[0x33]	7017	1			T1	6		T2	11		T5	1
valid_sources[0x34]	6714	1			T1	1		T2	7		T17	24
valid_sources[0x35]	6734	1			T1	1		T2	3		T5	1
valid_sources[0x36]	6840	1			T1	6		T2	4		T5	3
valid_sources[0x37]	6888	1			T1	7		T2	7		T21	2
valid_sources[0x38]	7532	1			T1	1		T2	11		T17	26
valid_sources[0x39]	6506	1			T1	4		T2	12		T21	7
valid_sources[0x3a]	7918	1			T4	7		T1	6		T2	6
valid_sources[0x3b]	6984	1			T2	8		T5	3		T21	16
valid_sources[0x3c]	7396	1			T1	2		T2	10		T21	3
valid_sources[0x3d]	6287	1			T4	6		T1	4		T2	9
valid_sources[0x3e]	7478	1			T1	2		T2	5		T5	1
valid_sources[0x3f]	7878	1			T2	8		T5	1		T6	2
valid_sources[0x40]	7461	1			T1	7		T2	3		T6	5
valid_sources[0x41]	7175	1			T2	5		T21	8		T22	9
valid_sources[0x42]	7301	1			T2	12		T5	2		T21	3
valid_sources[0x43]	7062	1			T1	4		T2	5		T5	1
valid_sources[0x44]	8509	1			T1	17		T2	6		T3	32
valid_sources[0x45]	6882	1			T1	8		T2	8		T5	1
valid_sources[0x46]	6780	1			T1	10		T2	14		T21	6
valid_sources[0x47]	7399	1			T4	13		T1	7		T2	3
valid_sources[0x48]	6520	1			T1	6		T2	7		T5	3
valid_sources[0x49]	7643	1			T1	6		T2	6		T5	2
valid_sources[0x4a]	7289	1			T1	12		T2	8		T5	2
valid_sources[0x4b]	7901	1			T1	9		T2	8		T6	5
valid_sources[0x4c]	7359	1			T4	14		T2	7		T5	1
valid_sources[0x4d]	7440	1			T1	8		T2	9		T21	1
valid_sources[0x4e]	6897	1			T1	4		T2	6		T21	2
valid_sources[0x4f]	7962	1			T1	3		T2	12		T5	2
valid_sources[0x50]	6799	1			T1	3		T2	9		T21	3
valid_sources[0x51]	7252	1			T1	12		T2	11		T21	8
valid_sources[0x52]	7408	1			T4	12		T2	4		T5	1
valid_sources[0x53]	6626	1			T2	10		T21	6		T22	2
valid_sources[0x54]	7264	1			T2	8		T21	2		T17	28
valid_sources[0x55]	8377	1			T1	2		T2	12		T5	2
valid_sources[0x56]	7343	1			T2	7		T5	1		T21	1
valid_sources[0x57]	7974	1			T2	8		T5	1		T21	7
valid_sources[0x58]	8396	1			T1	17		T2	8		T5	3
valid_sources[0x59]	7586	1			T1	4		T2	15		T21	12
valid_sources[0x5a]	7544	1			T1	2		T2	7		T5	2
valid_sources[0x5b]	6656	1			T4	9		T2	10		T21	12
valid_sources[0x5c]	7008	1			T2	7		T6	1		T21	7
valid_sources[0x5d]	7572	1			T1	8		T2	11		T5	1
valid_sources[0x5e]	6180	1			T1	16		T2	5		T5	2
valid_sources[0x5f]	7412	1			T1	13		T2	7		T5	2
valid_sources[0x60]	7603	1			T1	30		T2	6		T21	3
valid_sources[0x61]	6974	1			T4	5		T1	11		T2	14
valid_sources[0x62]	6190	1			T4	20		T1	1		T2	5
valid_sources[0x63]	7665	1			T1	5		T2	8		T21	2
valid_sources[0x64]	6947	1			T1	5		T2	20		T21	2
valid_sources[0x65]	6728	1			T1	2		T2	9		T21	5
valid_sources[0x66]	6845	1			T2	7		T5	1		T21	5
valid_sources[0x67]	7297	1			T2	5		T5	1		T21	5
valid_sources[0x68]	6895	1			T1	4		T2	5		T5	1
valid_sources[0x69]	7545	1			T1	9		T2	5		T21	2
valid_sources[0x6a]	6694	1			T1	10		T2	6		T5	2
valid_sources[0x6b]	8147	1			T1	13		T2	14		T5	1
valid_sources[0x6c]	6973	1			T1	4		T2	13		T5	3
valid_sources[0x6d]	7831	1			T1	8		T2	16		T5	2
valid_sources[0x6e]	7198	1			T1	22		T2	8		T5	2
valid_sources[0x6f]	7442	1			T4	28		T1	7		T2	6
valid_sources[0x70]	7520	1			T1	5		T2	4		T21	4
valid_sources[0x71]	7239	1			T1	12		T2	10		T5	2
valid_sources[0x72]	6374	1			T4	8		T1	9		T2	15
valid_sources[0x73]	7049	1			T1	2		T2	10		T21	3
valid_sources[0x74]	7548	1			T1	8		T2	7		T5	1
valid_sources[0x75]	6553	1			T1	3		T2	6		T5	3
valid_sources[0x76]	6900	1			T1	6		T2	1		T21	10
valid_sources[0x77]	6886	1			T2	5		T5	2		T21	10
valid_sources[0x78]	8741	1			T2	4		T5	1		T21	4
valid_sources[0x79]	7234	1			T1	4		T2	9		T5	2
valid_sources[0x7a]	6702	1			T1	12		T2	3		T21	4
valid_sources[0x7b]	7666	1			T2	9		T21	7		T24	1
valid_sources[0x7c]	6693	1			T1	12		T2	10		T21	6
valid_sources[0x7d]	7542	1			T1	1		T2	5		T6	1
valid_sources[0x7e]	9071	1			T4	20		T1	3		T2	3
valid_sources[0x7f]	6735	1			T4	16		T1	54		T2	8
valid_sources[0x80]	7544	1			T1	2		T2	13		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26868

1

T4

7

T1

36

T2

26

values[0x0]

all_enables

biggest_size

199144

1

T4

55

T1

196

T2

217

values[0x1]

all_enables

biggest_size

26940

1

T4

4

T1

30

T2

34