Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	351329763	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351329763	0	0
T1	9657648	1762659	0	0
T2	204288	7779	0	0
T3	130424	5196	0	0
T4	80416	2018	0	0
T5	8674456	278768	0	0
T6	3539704	62374	0	0
T17	6461000	136964	0	0
T21	1752352	36774	0	0
T22	8749048	174979	0	0
T23	3059168	43672	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9657648	9657424	0	0
T2	204288	203784	0	0
T3	130424	127624	0	0
T4	80416	77616	0	0
T5	8674456	8669976	0	0
T6	3539704	3536904	0	0
T17	6461000	6460608	0	0
T21	1752352	1751736	0	0
T22	8749048	8745632	0	0
T23	3059168	3056312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9657648	9657424	0	0
T2	204288	203784	0	0
T3	130424	127624	0	0
T4	80416	77616	0	0
T5	8674456	8669976	0	0
T6	3539704	3536904	0	0
T17	6461000	6460608	0	0
T21	1752352	1751736	0	0
T22	8749048	8745632	0	0
T23	3059168	3056312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9657648	9657424	0	0
T2	204288	203784	0	0
T3	130424	127624	0	0
T4	80416	77616	0	0
T5	8674456	8669976	0	0
T6	3539704	3536904	0	0
T17	6461000	6460608	0	0
T21	1752352	1751736	0	0
T22	8749048	8745632	0	0
T23	3059168	3056312	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T17	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	130492152	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	130492152	0	0
T1	172458	822664	0	0
T2	3648	3566	0	0
T3	2329	2019	0	0
T4	1436	505	0	0
T5	154901	152474	0	0
T6	63209	61284	0	0
T17	115375	112547	0	0
T21	31292	16495	0	0
T22	156233	75364	0	0
T23	54628	11170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	91040426	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	91040426	0	0
T1	172458	193386	0	0
T2	3648	2119	0	0
T3	2329	1059	0	0
T4	1436	505	0	0
T5	154901	62751	0	0
T6	63209	287	0	0
T17	115375	7253	0	0
T21	31292	4622	0	0
T22	156233	22316	0	0
T23	54628	10698	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1510743	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1510743	0	0
T1	172458	18060	0	0
T2	3648	34	0	0
T3	2329	40	0	0
T4	1436	11	0	0
T5	154901	33	0	0
T6	63209	22	0	0
T17	115375	346	0	0
T21	31292	405	0	0
T22	156233	1773	0	0
T23	54628	276	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3374463	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3374463	0	0
T1	172458	5997	0	0
T2	3648	34	0	0
T3	2329	40	0	0
T4	1436	11	0	0
T5	154901	3251	0	0
T6	63209	7	0	0
T17	115375	80	0	0
T21	31292	147	0	0
T22	156233	78	0	0
T23	54628	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1449120	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1449120	0	0
T1	172458	16253	0	0
T2	3648	25	0	0
T3	2329	31	0	0
T4	1436	14	0	0
T5	154901	22	0	0
T6	63209	33	0	0
T17	115375	363	0	0
T21	31292	527	0	0
T22	156233	2052	0	0
T23	54628	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3790391	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3790391	0	0
T1	172458	7504	0	0
T2	3648	25	0	0
T3	2329	31	0	0
T4	1436	14	0	0
T5	154901	1728	0	0
T6	63209	7	0	0
T17	115375	612	0	0
T21	31292	209	0	0
T22	156233	699	0	0
T23	54628	433	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1480950	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1480950	0	0
T1	172458	18199	0	0
T2	3648	30	0	0
T3	2329	41	0	0
T4	1436	19	0	0
T5	154901	50	0	0
T6	63209	18	0	0
T17	115375	337	0	0
T21	31292	465	0	0
T22	156233	2233	0	0
T23	54628	522	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	2952966	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	2952966	0	0
T1	172458	6963	0	0
T2	3648	30	0	0
T3	2329	41	0	0
T4	1436	19	0	0
T5	154901	2605	0	0
T6	63209	7	0	0
T17	115375	512	0	0
T21	31292	161	0	0
T22	156233	940	0	0
T23	54628	448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1458464	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1458464	0	0
T1	172458	24837	0	0
T2	3648	35	0	0
T3	2329	36	0	0
T4	1436	24	0	0
T5	154901	48	0	0
T6	63209	26	0	0
T17	115375	402	0	0
T21	31292	508	0	0
T22	156233	1690	0	0
T23	54628	389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3058079	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3058079	0	0
T1	172458	7218	0	0
T2	3648	35	0	0
T3	2329	36	0	0
T4	1436	24	0	0
T5	154901	3906	0	0
T6	63209	5	0	0
T17	115375	87	0	0
T21	31292	169	0	0
T22	156233	659	0	0
T23	54628	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1467632	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1467632	0	0
T1	172458	26363	0	0
T2	3648	31	0	0
T3	2329	29	0	0
T4	1436	13	0	0
T5	154901	26	0	0
T6	63209	25	0	0
T17	115375	407	0	0
T21	31292	398	0	0
T22	156233	1295	0	0
T23	54628	447	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3166210	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3166210	0	0
T1	172458	9957	0	0
T2	3648	31	0	0
T3	2329	29	0	0
T4	1436	13	0	0
T5	154901	2068	0	0
T6	63209	4	0	0
T17	115375	311	0	0
T21	31292	162	0	0
T22	156233	778	0	0
T23	54628	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1487749	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1487749	0	0
T1	172458	21050	0	0
T2	3648	46	0	0
T3	2329	35	0	0
T4	1436	23	0	0
T5	154901	44	0	0
T6	63209	24	0	0
T17	115375	367	0	0
T21	31292	427	0	0
T22	156233	2614	0	0
T23	54628	329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	4226347	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	4226347	0	0
T1	172458	6874	0	0
T2	3648	46	0	0
T3	2329	35	0	0
T4	1436	23	0	0
T5	154901	3085	0	0
T6	63209	5	0	0
T17	115375	191	0	0
T21	31292	194	0	0
T22	156233	1311	0	0
T23	54628	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1450139	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1450139	0	0
T1	172458	17433	0	0
T2	3648	49	0	0
T3	2329	59	0	0
T4	1436	8	0	0
T5	154901	52	0	0
T6	63209	29	0	0
T17	115375	380	0	0
T21	31292	400	0	0
T22	156233	2982	0	0
T23	54628	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	2930909	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	2930909	0	0
T1	172458	5936	0	0
T2	3648	49	0	0
T3	2329	59	0	0
T4	1436	8	0	0
T5	154901	4051	0	0
T6	63209	9	0	0
T17	115375	87	0	0
T21	31292	198	0	0
T22	156233	1006	0	0
T23	54628	311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1447574	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1447574	0	0
T1	172458	18073	0	0
T2	3648	42	0	0
T3	2329	33	0	0
T4	1436	19	0	0
T5	154901	16	0	0
T6	63209	6	0	0
T17	115375	332	0	0
T21	31292	425	0	0
T22	156233	3798	0	0
T23	54628	371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3413943	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3413943	0	0
T1	172458	5172	0	0
T2	3648	42	0	0
T3	2329	33	0	0
T4	1436	19	0	0
T5	154901	2958	0	0
T6	63209	2	0	0
T17	115375	79	0	0
T21	31292	159	0	0
T22	156233	460	0	0
T23	54628	313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1449584	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1449584	0	0
T1	172458	23060	0	0
T2	3648	33	0	0
T3	2329	42	0	0
T4	1436	23	0	0
T5	154901	39	0	0
T6	63209	37	0	0
T17	115375	390	0	0
T21	31292	402	0	0
T22	156233	4432	0	0
T23	54628	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3137990	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3137990	0	0
T1	172458	5255	0	0
T2	3648	33	0	0
T3	2329	42	0	0
T4	1436	23	0	0
T5	154901	4556	0	0
T6	63209	6	0	0
T17	115375	412	0	0
T21	31292	148	0	0
T22	156233	2068	0	0
T23	54628	522	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1421171	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1421171	0	0
T1	172458	23597	0	0
T2	3648	39	0	0
T3	2329	40	0	0
T4	1436	22	0	0
T5	154901	28	0	0
T6	63209	42	0	0
T17	115375	437	0	0
T21	31292	477	0	0
T22	156233	1722	0	0
T23	54628	443	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3266639	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3266639	0	0
T1	172458	8434	0	0
T2	3648	39	0	0
T3	2329	40	0	0
T4	1436	22	0	0
T5	154901	1711	0	0
T6	63209	175	0	0
T17	115375	106	0	0
T21	31292	183	0	0
T22	156233	639	0	0
T23	54628	392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1470290	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1470290	0	0
T1	172458	19381	0	0
T2	3648	43	0	0
T3	2329	36	0	0
T4	1436	14	0	0
T5	154901	15	0	0
T6	63209	9	0	0
T17	115375	371	0	0
T21	31292	347	0	0
T22	156233	1925	0	0
T23	54628	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3100840	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3100840	0	0
T1	172458	9211	0	0
T2	3648	43	0	0
T3	2329	36	0	0
T4	1436	14	0	0
T5	154901	408	0	0
T6	63209	3	0	0
T17	115375	91	0	0
T21	31292	167	0	0
T22	156233	1041	0	0
T23	54628	310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1490144	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1490144	0	0
T1	172458	21942	0	0
T2	3648	40	0	0
T3	2329	41	0	0
T4	1436	16	0	0
T5	154901	36	0	0
T6	63209	14	0	0
T17	115375	371	0	0
T21	31292	437	0	0
T22	156233	1110	0	0
T23	54628	385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3049384	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3049384	0	0
T1	172458	7032	0	0
T2	3648	40	0	0
T3	2329	41	0	0
T4	1436	16	0	0
T5	154901	1977	0	0
T6	63209	3	0	0
T17	115375	90	0	0
T21	31292	211	0	0
T22	156233	1294	0	0
T23	54628	345	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1437806	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1437806	0	0
T1	172458	24659	0	0
T2	3648	40	0	0
T3	2329	29	0	0
T4	1436	25	0	0
T5	154901	37	0	0
T6	63209	34	0	0
T17	115375	412	0	0
T21	31292	307	0	0
T22	156233	387	0	0
T23	54628	358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	2713895	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	2713895	0	0
T1	172458	7615	0	0
T2	3648	40	0	0
T3	2329	29	0	0
T4	1436	25	0	0
T5	154901	3473	0	0
T6	63209	5	0	0
T17	115375	84	0	0
T21	31292	118	0	0
T22	156233	2	0	0
T23	54628	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1499089	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1499089	0	0
T1	172458	17908	0	0
T2	3648	42	0	0
T3	2329	40	0	0
T4	1436	27	0	0
T5	154901	19	0	0
T6	63209	7	0	0
T17	115375	382	0	0
T21	31292	327	0	0
T22	156233	693	0	0
T23	54628	315	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3325913	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3325913	0	0
T1	172458	6602	0	0
T2	3648	42	0	0
T3	2329	40	0	0
T4	1436	27	0	0
T5	154901	2642	0	0
T6	63209	2	0	0
T17	115375	803	0	0
T21	31292	151	0	0
T22	156233	1	0	0
T23	54628	321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1526360	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1526360	0	0
T1	172458	21565	0	0
T2	3648	36	0	0
T3	2329	40	0	0
T4	1436	19	0	0
T5	154901	40	0	0
T6	63209	12	0	0
T17	115375	411	0	0
T21	31292	347	0	0
T22	156233	1933	0	0
T23	54628	553	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3689445	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3689445	0	0
T1	172458	5200	0	0
T2	3648	36	0	0
T3	2329	40	0	0
T4	1436	19	0	0
T5	154901	2032	0	0
T6	63209	4	0	0
T17	115375	335	0	0
T21	31292	136	0	0
T22	156233	1007	0	0
T23	54628	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1480404	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1480404	0	0
T1	172458	21484	0	0
T2	3648	37	0	0
T3	2329	40	0	0
T4	1436	26	0	0
T5	154901	4	0	0
T6	63209	9	0	0
T17	115375	330	0	0
T21	31292	405	0	0
T22	156233	2644	0	0
T23	54628	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	2849545	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	2849545	0	0
T1	172458	6575	0	0
T2	3648	37	0	0
T3	2329	40	0	0
T4	1436	26	0	0
T5	154901	990	0	0
T6	63209	2	0	0
T17	115375	303	0	0
T21	31292	183	0	0
T22	156233	1217	0	0
T23	54628	490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1480258	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1480258	0	0
T1	172458	21757	0	0
T2	3648	46	0	0
T3	2329	47	0	0
T4	1436	14	0	0
T5	154901	43	0	0
T6	63209	19	0	0
T17	115375	361	0	0
T21	31292	425	0	0
T22	156233	1811	0	0
T23	54628	512	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3014361	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3014361	0	0
T1	172458	6138	0	0
T2	3648	46	0	0
T3	2329	47	0	0
T4	1436	14	0	0
T5	154901	2990	0	0
T6	63209	3	0	0
T17	115375	860	0	0
T21	31292	151	0	0
T22	156233	572	0	0
T23	54628	463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1483061	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1483061	0	0
T1	172458	17407	0	0
T2	3648	40	0	0
T3	2329	36	0	0
T4	1436	19	0	0
T5	154901	35	0	0
T6	63209	14	0	0
T17	115375	332	0	0
T21	31292	413	0	0
T22	156233	725	0	0
T23	54628	464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3464187	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3464187	0	0
T1	172458	8451	0	0
T2	3648	40	0	0
T3	2329	36	0	0
T4	1436	19	0	0
T5	154901	1916	0	0
T6	63209	6	0	0
T17	115375	810	0	0
T21	31292	162	0	0
T22	156233	587	0	0
T23	54628	327	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1483033	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1483033	0	0
T1	172458	21554	0	0
T2	3648	45	0	0
T3	2329	32	0	0
T4	1436	24	0	0
T5	154901	30	0	0
T6	63209	14	0	0
T17	115375	307	0	0
T21	31292	373	0	0
T22	156233	2167	0	0
T23	54628	433	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3567498	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3567498	0	0
T1	172458	6619	0	0
T2	3648	45	0	0
T3	2329	32	0	0
T4	1436	24	0	0
T5	154901	1666	0	0
T6	63209	3	0	0
T17	115375	63	0	0
T21	31292	185	0	0
T22	156233	1151	0	0
T23	54628	437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1443874	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1443874	0	0
T1	172458	22360	0	0
T2	3648	44	0	0
T3	2329	28	0	0
T4	1436	23	0	0
T5	154901	5	0	0
T6	63209	16	0	0
T17	115375	340	0	0
T21	31292	444	0	0
T22	156233	3657	0	0
T23	54628	393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3693073	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3693073	0	0
T1	172458	9795	0	0
T2	3648	44	0	0
T3	2329	28	0	0
T4	1436	23	0	0
T5	154901	809	0	0
T6	63209	3	0	0
T17	115375	81	0	0
T21	31292	252	0	0
T22	156233	186	0	0
T23	54628	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1523147	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1523147	0	0
T1	172458	18094	0	0
T2	3648	28	0	0
T3	2329	52	0	0
T4	1436	22	0	0
T5	154901	16	0	0
T6	63209	7	0	0
T17	115375	409	0	0
T21	31292	283	0	0
T22	156233	1798	0	0
T23	54628	400	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3300637	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3300637	0	0
T1	172458	9196	0	0
T2	3648	28	0	0
T3	2329	52	0	0
T4	1436	22	0	0
T5	154901	2008	0	0
T6	63209	2	0	0
T17	115375	81	0	0
T21	31292	118	0	0
T22	156233	923	0	0
T23	54628	369	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1495402	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1495402	0	0
T1	172458	17280	0	0
T2	3648	48	0	0
T3	2329	33	0	0
T4	1436	10	0	0
T5	154901	48	0	0
T6	63209	20	0	0
T17	115375	365	0	0
T21	31292	432	0	0
T22	156233	946	0	0
T23	54628	318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3494838	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3494838	0	0
T1	172458	6325	0	0
T2	3648	48	0	0
T3	2329	33	0	0
T4	1436	10	0	0
T5	154901	2406	0	0
T6	63209	7	0	0
T17	115375	84	0	0
T21	31292	160	0	0
T22	156233	162	0	0
T23	54628	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1408644	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1408644	0	0
T1	172458	20758	0	0
T2	3648	34	0	0
T3	2329	42	0	0
T4	1436	15	0	0
T5	154901	18	0	0
T6	63209	2	0	0
T17	115375	323	0	0
T21	31292	434	0	0
T22	156233	1310	0	0
T23	54628	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	2809086	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	2809086	0	0
T1	172458	6370	0	0
T2	3648	34	0	0
T3	2329	42	0	0
T4	1436	15	0	0
T5	154901	1245	0	0
T6	63209	1	0	0
T17	115375	83	0	0
T21	31292	168	0	0
T22	156233	753	0	0
T23	54628	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1454029	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1454029	0	0
T1	172458	22311	0	0
T2	3648	50	0	0
T3	2329	38	0	0
T4	1436	12	0	0
T5	154901	13	0	0
T6	63209	11	0	0
T17	115375	352	0	0
T21	31292	433	0	0
T22	156233	4108	0	0
T23	54628	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3979777	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3979777	0	0
T1	172458	8147	0	0
T2	3648	50	0	0
T3	2329	38	0	0
T4	1436	12	0	0
T5	154901	1561	0	0
T6	63209	3	0	0
T17	115375	92	0	0
T21	31292	188	0	0
T22	156233	1986	0	0
T23	54628	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1473735	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1473735	0	0
T1	172458	23493	0	0
T2	3648	38	0	0
T3	2329	50	0	0
T4	1436	28	0	0
T5	154901	37	0	0
T6	63209	30	0	0
T17	115375	435	0	0
T21	31292	379	0	0
T22	156233	1652	0	0
T23	54628	599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3917553	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3917553	0	0
T1	172458	6359	0	0
T2	3648	38	0	0
T3	2329	50	0	0
T4	1436	28	0	0
T5	154901	2950	0	0
T6	63209	6	0	0
T17	115375	684	0	0
T21	31292	183	0	0
T22	156233	1062	0	0
T23	54628	564	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1464975	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1464975	0	0
T1	172458	16698	0	0
T2	3648	32	0	0
T3	2329	47	0	0
T4	1436	20	0	0
T5	154901	20	0	0
T6	63209	26	0	0
T17	115375	313	0	0
T21	31292	458	0	0
T22	156233	1197	0	0
T23	54628	477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3302350	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3302350	0	0
T1	172458	6820	0	0
T2	3648	32	0	0
T3	2329	47	0	0
T4	1436	20	0	0
T5	154901	1631	0	0
T6	63209	4	0	0
T17	115375	147	0	0
T21	31292	196	0	0
T22	156233	861	0	0
T23	54628	518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	1464264	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	1464264	0	0
T1	172458	17647	0	0
T2	3648	40	0	0
T3	2329	42	0	0
T4	1436	14	0	0
T5	154901	18	0	0
T6	63209	10	0	0
T17	115375	337	0	0
T21	31292	357	0	0
T22	156233	2329	0	0
T23	54628	398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313829169	3505225	0	0
DepthKnown_A	313829169	313704873	0	0
RvalidKnown_A	313829169	313704873	0	0
WreadyKnown_A	313829169	313704873	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	3505225	0	0
T1	172458	7621	0	0
T2	3648	40	0	0
T3	2329	42	0	0
T4	1436	14	0	0
T5	154901	2128	0	0
T6	63209	3	0	0
T17	115375	84	0	0
T21	31292	163	0	0
T22	156233	873	0	0
T23	54628	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313829169	313704873	0	0
T1	172458	172454	0	0
T2	3648	3639	0	0
T3	2329	2279	0	0
T4	1436	1386	0	0
T5	154901	154821	0	0
T6	63209	63159	0	0
T17	115375	115368	0	0
T21	31292	31281	0	0
T22	156233	156172	0	0
T23	54628	54577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0