Module Definition
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Module : tlul_err_resp
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_s1n_28.gen_err_resp.err_resp 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_s1n_28.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.54 100.00 100.00 u_s1n_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL2626100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6455100.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 1 1
69 1 1
75 1 1


Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT4,T1,T2
10CoveredT27,T170,T141
11CoveredT4,T2,T17

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01CoveredT23,T27,T19
10CoveredT17,T23,T18
11CoveredT4,T1,T2

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT4,T1,T2
10CoveredT4,T2,T17
11CoveredT17,T23,T18

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT4,T1,T2
01CoveredT23,T27,T19
10CoveredT4,T2,T17

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT4,T2,T17
1CoveredT4,T1,T2

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT4,T1,T2
1CoveredT4,T1,T2

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT4,T1,T2
10CoveredT4,T2,T17
11CoveredT23,T27,T19

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT4,T1,T2
01CoveredT23,T27,T19
10CoveredT4,T2,T17

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00
IF 64 3 3 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T4,T2,T17


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T2
0 1 - Covered T4,T2,T17
0 0 1 Covered T4,T1,T2
0 0 0 Covered T22,T23,T27


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T2
0 1 Covered T22,T23,T27
0 0 Covered T4,T1,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%