Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1733140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

272646

1

T1

222

T2

14

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	678564	1			T1	535		T2	35		T3	50
values[0x0]	647339	1			T1	546		T2	38		T3	55
values[0x1]	679883	1			T1	528		T2	29		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1343889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

661897

1

T1

491

T2

26

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7292	1			T1	6		T18	21		T14	6
valid_sources[0x01]	7979	1			T1	4		T18	19		T21	4
valid_sources[0x02]	8048	1			T1	3		T3	2		T18	18
valid_sources[0x03]	7108	1			T1	7		T2	1		T3	6
valid_sources[0x04]	8317	1			T1	2		T3	3		T5	2
valid_sources[0x05]	6872	1			T1	17		T18	17		T14	8
valid_sources[0x06]	7828	1			T1	10		T18	10		T14	9
valid_sources[0x07]	8622	1			T1	18		T2	4		T18	13
valid_sources[0x08]	7304	1			T1	5		T2	2		T5	1
valid_sources[0x09]	7424	1			T1	5		T5	1		T13	1
valid_sources[0x0a]	8381	1			T1	5		T18	12		T21	7
valid_sources[0x0b]	7824	1			T1	7		T13	1		T18	18
valid_sources[0x0c]	7629	1			T1	11		T13	1		T18	19
valid_sources[0x0d]	7375	1			T1	5		T18	21		T21	18
valid_sources[0x0e]	8043	1			T1	10		T2	2		T13	1
valid_sources[0x0f]	7752	1			T1	13		T13	1		T18	13
valid_sources[0x10]	7830	1			T1	5		T13	1		T18	15
valid_sources[0x11]	7460	1			T1	3		T5	3		T18	12
valid_sources[0x12]	7098	1			T1	6		T3	2		T18	17
valid_sources[0x13]	7603	1			T1	1		T2	1		T18	20
valid_sources[0x14]	8043	1			T18	10		T19	10		T14	7
valid_sources[0x15]	7449	1			T1	5		T2	6		T5	1
valid_sources[0x16]	7883	1			T1	6		T18	21		T21	5
valid_sources[0x17]	7255	1			T1	2		T18	17		T19	11
valid_sources[0x18]	7586	1			T13	1		T18	22		T15	1
valid_sources[0x19]	7456	1			T1	9		T2	1		T3	2
valid_sources[0x1a]	8351	1			T1	3		T2	1		T5	2
valid_sources[0x1b]	8109	1			T1	3		T13	1		T18	22
valid_sources[0x1c]	7558	1			T1	4		T13	1		T18	18
valid_sources[0x1d]	8008	1			T1	3		T5	1		T13	1
valid_sources[0x1e]	7739	1			T1	3		T13	1		T18	16
valid_sources[0x1f]	7412	1			T1	5		T5	1		T18	19
valid_sources[0x20]	8430	1			T1	8		T3	3		T5	1
valid_sources[0x21]	7231	1			T1	1		T2	1		T3	3
valid_sources[0x22]	8196	1			T1	2		T5	1		T20	76
valid_sources[0x23]	7539	1			T1	4		T2	1		T3	3
valid_sources[0x24]	7764	1			T1	5		T3	4		T13	1
valid_sources[0x25]	7325	1			T1	8		T2	2		T5	1
valid_sources[0x26]	6934	1			T1	1		T18	11		T15	2
valid_sources[0x27]	8332	1			T1	2		T3	3		T13	1
valid_sources[0x28]	7283	1			T1	6		T3	3		T18	20
valid_sources[0x29]	8182	1			T1	8		T3	1		T5	1
valid_sources[0x2a]	7869	1			T1	20		T13	1		T18	22
valid_sources[0x2b]	7012	1			T3	2		T5	2		T13	2
valid_sources[0x2c]	7711	1			T1	3		T2	1		T18	16
valid_sources[0x2d]	7361	1			T1	9		T2	2		T3	3
valid_sources[0x2e]	7559	1			T5	1		T18	16		T14	9
valid_sources[0x2f]	7715	1			T1	2		T3	1		T13	1
valid_sources[0x30]	7692	1			T1	2		T18	14		T14	7
valid_sources[0x31]	7644	1			T1	2		T5	3		T13	1
valid_sources[0x32]	8063	1			T1	11		T5	2		T18	15
valid_sources[0x33]	7517	1			T1	6		T2	1		T13	1
valid_sources[0x34]	7737	1			T2	1		T3	1		T5	1
valid_sources[0x35]	8052	1			T1	23		T2	3		T18	15
valid_sources[0x36]	9085	1			T18	25		T21	1		T14	9
valid_sources[0x37]	7377	1			T1	3		T2	1		T3	4
valid_sources[0x38]	9170	1			T1	6		T3	6		T5	1
valid_sources[0x39]	8645	1			T1	15		T13	2		T18	19
valid_sources[0x3a]	7198	1			T1	6		T18	13		T14	8
valid_sources[0x3b]	7687	1			T1	4		T18	21		T15	1
valid_sources[0x3c]	7856	1			T1	1		T18	20		T15	1
valid_sources[0x3d]	7637	1			T3	2		T5	1		T18	15
valid_sources[0x3e]	7921	1			T1	2		T13	2		T18	19
valid_sources[0x3f]	7753	1			T1	4		T2	2		T18	24
valid_sources[0x40]	7936	1			T5	1		T13	1		T18	16
valid_sources[0x41]	8070	1			T1	13		T5	1		T18	13
valid_sources[0x42]	7830	1			T1	1		T3	4		T5	1
valid_sources[0x43]	8090	1			T1	3		T3	2		T5	1
valid_sources[0x44]	7662	1			T1	11		T18	24		T21	15
valid_sources[0x45]	7710	1			T1	5		T5	1		T18	17
valid_sources[0x46]	7571	1			T1	3		T3	2		T18	26
valid_sources[0x47]	7748	1			T1	26		T13	1		T18	10
valid_sources[0x48]	8240	1			T1	25		T5	3		T18	25
valid_sources[0x49]	7993	1			T1	7		T2	1		T3	1
valid_sources[0x4a]	8015	1			T1	9		T2	1		T3	1
valid_sources[0x4b]	7659	1			T1	15		T2	1		T3	1
valid_sources[0x4c]	8846	1			T1	5		T13	1		T18	28
valid_sources[0x4d]	7113	1			T1	8		T2	1		T18	15
valid_sources[0x4e]	6837	1			T1	8		T3	2		T5	1
valid_sources[0x4f]	7503	1			T1	6		T2	2		T18	17
valid_sources[0x50]	8078	1			T1	13		T18	24		T14	8
valid_sources[0x51]	7629	1			T1	5		T3	2		T18	24
valid_sources[0x52]	7779	1			T1	12		T3	5		T18	11
valid_sources[0x53]	7561	1			T1	7		T3	1		T13	1
valid_sources[0x54]	7518	1			T1	12		T5	1		T18	23
valid_sources[0x55]	7717	1			T1	6		T18	23		T19	20
valid_sources[0x56]	7716	1			T1	4		T2	1		T13	2
valid_sources[0x57]	7621	1			T1	17		T5	1		T18	15
valid_sources[0x58]	7420	1			T1	3		T2	1		T18	19
valid_sources[0x59]	7570	1			T1	2		T3	5		T13	1
valid_sources[0x5a]	7736	1			T1	8		T3	4		T5	2
valid_sources[0x5b]	7262	1			T1	1		T3	2		T18	15
valid_sources[0x5c]	7865	1			T2	1		T18	16		T15	1
valid_sources[0x5d]	8283	1			T1	5		T2	1		T13	1
valid_sources[0x5e]	7392	1			T1	33		T18	23		T15	1
valid_sources[0x5f]	6980	1			T1	1		T18	24		T14	8
valid_sources[0x60]	7738	1			T1	4		T5	1		T18	25
valid_sources[0x61]	7388	1			T1	7		T5	2		T18	15
valid_sources[0x62]	7512	1			T1	11		T5	2		T13	2
valid_sources[0x63]	7980	1			T1	4		T18	16		T15	2
valid_sources[0x64]	8158	1			T1	7		T5	2		T18	29
valid_sources[0x65]	8005	1			T1	10		T13	2		T18	22
valid_sources[0x66]	7641	1			T1	6		T2	2		T5	1
valid_sources[0x67]	7983	1			T1	1		T2	1		T18	16
valid_sources[0x68]	7051	1			T1	7		T18	21		T19	20
valid_sources[0x69]	7540	1			T1	2		T2	1		T13	1
valid_sources[0x6a]	7529	1			T1	1		T5	1		T18	15
valid_sources[0x6b]	8537	1			T1	8		T13	2		T18	23
valid_sources[0x6c]	6828	1			T1	3		T3	3		T5	1
valid_sources[0x6d]	7636	1			T1	8		T2	1		T5	1
valid_sources[0x6e]	8136	1			T3	5		T4	12		T18	14
valid_sources[0x6f]	7649	1			T1	8		T13	1		T18	20
valid_sources[0x70]	7317	1			T1	5		T2	1		T5	1
valid_sources[0x71]	8008	1			T1	5		T3	1		T5	1
valid_sources[0x72]	8374	1			T1	4		T2	1		T13	2
valid_sources[0x73]	7901	1			T1	11		T18	19		T21	14
valid_sources[0x74]	8351	1			T1	3		T18	10		T14	8
valid_sources[0x75]	7447	1			T1	7		T2	3		T18	18
valid_sources[0x76]	8051	1			T1	1		T3	2		T18	20
valid_sources[0x77]	7640	1			T1	3		T2	1		T18	16
valid_sources[0x78]	8014	1			T1	4		T18	17		T14	8
valid_sources[0x79]	7555	1			T1	3		T18	15		T15	1
valid_sources[0x7a]	8814	1			T1	7		T4	21		T18	13
valid_sources[0x7b]	7799	1			T1	5		T2	1		T18	25
valid_sources[0x7c]	7498	1			T1	12		T5	1		T4	11
valid_sources[0x7d]	7230	1			T1	8		T5	1		T4	5
valid_sources[0x7e]	8498	1			T1	6		T3	2		T13	3
valid_sources[0x7f]	8228	1			T1	5		T2	1		T5	1
valid_sources[0x80]	7275	1			T1	6		T5	1		T18	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28946

1

T1

22

T2

2

T3

1

values[0x0]

all_enables

biggest_size

214631

1

T1

182

T2

11

T3

19

values[0x1]

all_enables

biggest_size

29069

1

T1

18

T2

1

T3

5