Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	321112926	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321112926	0	0
T1	11642456	1771553	0	0
T2	2914744	51376	0	0
T3	25200	829	0	0
T4	732088	17432	0	0
T5	38696	703	0	0
T13	259728	11700	0	0
T15	149184	5213	0	0
T18	277592	18663	0	0
T19	2410016	33961	0	0
T20	55608	2342	0	0
T21	0	4722	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11642456	11642008	0	0
T2	2914744	2912784	0	0
T3	25200	24416	0	0
T4	732088	711032	0	0
T5	38696	35952	0	0
T13	259728	259224	0	0
T15	149184	146832	0	0
T18	277592	275072	0	0
T19	2410016	2406096	0	0
T20	55608	55216	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11642456	11642008	0	0
T2	2914744	2912784	0	0
T3	25200	24416	0	0
T4	732088	711032	0	0
T5	38696	35952	0	0
T13	259728	259224	0	0
T15	149184	146832	0	0
T18	277592	275072	0	0
T19	2410016	2406096	0	0
T20	55608	55216	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11642456	11642008	0	0
T2	2914744	2912784	0	0
T3	25200	24416	0	0
T4	732088	711032	0	0
T5	38696	35952	0	0
T13	259728	259224	0	0
T15	149184	146832	0	0
T18	277592	275072	0	0
T19	2410016	2406096	0	0
T20	55608	55216	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T13	56	56	0	0
T15	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	117862317	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	117862317	0	0
T1	207901	119316	0	0
T2	52049	50461	0	0
T3	450	325	0	0
T4	13073	7408	0	0
T5	691	271	0	0
T13	4638	4548	0	0
T15	2664	2385	0	0
T18	4957	4667	0	0
T19	43036	8459	0	0
T20	993	917	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	83649646	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	83649646	0	0
T1	207901	556606	0	0
T2	52049	249	0	0
T3	450	168	0	0
T4	13073	3359	0	0
T5	691	144	0	0
T13	4638	2384	0	0
T15	2664	1408	0	0
T18	4957	4666	0	0
T19	43036	8551	0	0
T20	993	475	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1375866	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1375866	0	0
T1	207901	20845	0	0
T2	52049	15	0	0
T3	450	9	0	0
T4	13073	34	0	0
T5	691	4	0	0
T13	4638	88	0	0
T15	2664	29	0	0
T18	4957	209	0	0
T19	43036	226	0	0
T20	993	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2998150	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2998150	0	0
T1	207901	20586	0	0
T2	52049	4	0	0
T3	450	9	0	0
T4	13073	44	0	0
T5	691	4	0	0
T13	4638	88	0	0
T15	2664	29	0	0
T18	4957	209	0	0
T19	43036	229	0	0
T20	993	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1314797	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1314797	0	0
T1	207901	16104	0	0
T2	52049	8	0	0
T3	450	13	0	0
T4	13073	75	0	0
T5	691	4	0	0
T13	4638	87	0	0
T15	2664	25	0	0
T18	4957	0	0	0
T19	43036	368	0	0
T20	993	21	0	0
T21	0	208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2554559	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2554559	0	0
T1	207901	14439	0	0
T2	52049	3	0	0
T3	450	13	0	0
T4	13073	58	0	0
T5	691	4	0	0
T13	4638	87	0	0
T15	2664	25	0	0
T18	4957	0	0	0
T19	43036	366	0	0
T20	993	21	0	0
T21	0	853	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1357246	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1357246	0	0
T1	207901	19491	0	0
T2	52049	7	0	0
T3	450	8	0	0
T4	13073	78	0	0
T5	691	6	0	0
T13	4638	84	0	0
T15	2664	29	0	0
T18	4957	0	0	0
T19	43036	247	0	0
T20	993	17	0	0
T21	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3371843	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3371843	0	0
T1	207901	19788	0	0
T2	52049	2	0	0
T3	450	8	0	0
T4	13073	66	0	0
T5	691	6	0	0
T13	4638	84	0	0
T15	2664	29	0	0
T18	4957	0	0	0
T19	43036	270	0	0
T20	993	17	0	0
T21	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1341284	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1341284	0	0
T1	207901	19085	0	0
T2	52049	5	0	0
T3	450	6	0	0
T4	13073	49	0	0
T5	691	7	0	0
T13	4638	82	0	0
T15	2664	19	0	0
T18	4957	0	0	0
T19	43036	225	0	0
T20	993	21	0	0
T21	0	207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3062967	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3062967	0	0
T1	207901	17577	0	0
T2	52049	2	0	0
T3	450	6	0	0
T4	13073	85	0	0
T5	691	7	0	0
T13	4638	82	0	0
T15	2664	19	0	0
T18	4957	0	0	0
T19	43036	172	0	0
T20	993	21	0	0
T21	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1333626	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1333626	0	0
T1	207901	20601	0	0
T2	52049	12	0	0
T3	450	7	0	0
T4	13073	48	0	0
T5	691	6	0	0
T13	4638	72	0	0
T15	2664	23	0	0
T18	4957	259	0	0
T19	43036	351	0	0
T20	993	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3007558	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3007558	0	0
T1	207901	21152	0	0
T2	52049	2	0	0
T3	450	7	0	0
T4	13073	39	0	0
T5	691	6	0	0
T13	4638	72	0	0
T15	2664	23	0	0
T18	4957	259	0	0
T19	43036	386	0	0
T20	993	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1365580	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1365580	0	0
T1	207901	18226	0	0
T2	52049	28	0	0
T3	450	7	0	0
T4	13073	59	0	0
T5	691	9	0	0
T13	4638	103	0	0
T15	2664	29	0	0
T18	4957	651	0	0
T19	43036	405	0	0
T20	993	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3237445	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3237445	0	0
T1	207901	16186	0	0
T2	52049	6	0	0
T3	450	7	0	0
T4	13073	71	0	0
T5	691	9	0	0
T13	4638	103	0	0
T15	2664	29	0	0
T18	4957	651	0	0
T19	43036	388	0	0
T20	993	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1367845	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1367845	0	0
T1	207901	21940	0	0
T2	52049	40	0	0
T3	450	8	0	0
T4	13073	46	0	0
T5	691	4	0	0
T13	4638	79	0	0
T15	2664	20	0	0
T18	4957	0	0	0
T19	43036	279	0	0
T20	993	23	0	0
T21	0	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3542351	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3542351	0	0
T1	207901	24128	0	0
T2	52049	9	0	0
T3	450	8	0	0
T4	13073	50	0	0
T5	691	4	0	0
T13	4638	79	0	0
T15	2664	20	0	0
T18	4957	0	0	0
T19	43036	261	0	0
T20	993	23	0	0
T21	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1358696	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1358696	0	0
T1	207901	19753	0	0
T2	52049	7	0	0
T3	450	8	0	0
T4	13073	54	0	0
T5	691	3	0	0
T13	4638	89	0	0
T15	2664	26	0	0
T18	4957	0	0	0
T19	43036	296	0	0
T20	993	22	0	0
T21	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2928938	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2928938	0	0
T1	207901	20008	0	0
T2	52049	1	0	0
T3	450	8	0	0
T4	13073	96	0	0
T5	691	3	0	0
T13	4638	89	0	0
T15	2664	26	0	0
T18	4957	0	0	0
T19	43036	297	0	0
T20	993	22	0	0
T21	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1397505	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1397505	0	0
T1	207901	23277	0	0
T2	52049	15	0	0
T3	450	4	0	0
T4	13073	73	0	0
T5	691	2	0	0
T13	4638	85	0	0
T15	2664	22	0	0
T18	4957	0	0	0
T19	43036	340	0	0
T20	993	14	0	0
T21	0	150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3250815	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3250815	0	0
T1	207901	24656	0	0
T2	52049	4	0	0
T3	450	4	0	0
T4	13073	88	0	0
T5	691	2	0	0
T13	4638	85	0	0
T15	2664	22	0	0
T18	4957	0	0	0
T19	43036	339	0	0
T20	993	14	0	0
T21	0	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1338231	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1338231	0	0
T1	207901	22648	0	0
T2	52049	8	0	0
T3	450	7	0	0
T4	13073	130	0	0
T5	691	4	0	0
T13	4638	92	0	0
T15	2664	32	0	0
T18	4957	0	0	0
T19	43036	319	0	0
T20	993	17	0	0
T21	0	127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2575729	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2575729	0	0
T1	207901	20052	0	0
T2	52049	3	0	0
T3	450	7	0	0
T4	13073	86	0	0
T5	691	4	0	0
T13	4638	92	0	0
T15	2664	32	0	0
T18	4957	0	0	0
T19	43036	343	0	0
T20	993	17	0	0
T21	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1417329	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1417329	0	0
T1	207901	23916	0	0
T2	52049	34	0	0
T3	450	8	0	0
T4	13073	825	0	0
T5	691	6	0	0
T13	4638	82	0	0
T15	2664	30	0	0
T18	4957	242	0	0
T19	43036	242	0	0
T20	993	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2917094	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2917094	0	0
T1	207901	30637	0	0
T2	52049	9	0	0
T3	450	8	0	0
T4	13073	885	0	0
T5	691	6	0	0
T13	4638	82	0	0
T15	2664	30	0	0
T18	4957	242	0	0
T19	43036	301	0	0
T20	993	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1347532	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1347532	0	0
T1	207901	23438	0	0
T2	52049	4	0	0
T3	450	1	0	0
T4	13073	48	0	0
T5	691	4	0	0
T13	4638	99	0	0
T15	2664	15	0	0
T18	4957	0	0	0
T19	43036	338	0	0
T20	993	14	0	0
T21	0	174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3117927	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3117927	0	0
T1	207901	23557	0	0
T2	52049	2	0	0
T3	450	1	0	0
T4	13073	76	0	0
T5	691	4	0	0
T13	4638	99	0	0
T15	2664	15	0	0
T18	4957	0	0	0
T19	43036	371	0	0
T20	993	14	0	0
T21	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1342567	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1342567	0	0
T1	207901	20593	0	0
T2	52049	11	0	0
T3	450	6	0	0
T4	13073	41	0	0
T5	691	10	0	0
T13	4638	89	0	0
T15	2664	26	0	0
T18	4957	0	0	0
T19	43036	310	0	0
T20	993	14	0	0
T21	0	156	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3149425	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3149425	0	0
T1	207901	23870	0	0
T2	52049	2	0	0
T3	450	6	0	0
T4	13073	65	0	0
T5	691	10	0	0
T13	4638	89	0	0
T15	2664	26	0	0
T18	4957	0	0	0
T19	43036	296	0	0
T20	993	14	0	0
T21	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1430896	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1430896	0	0
T1	207901	19479	0	0
T2	52049	21	0	0
T3	450	5	0	0
T4	13073	76	0	0
T5	691	3	0	0
T13	4638	94	0	0
T15	2664	24	0	0
T18	4957	298	0	0
T19	43036	335	0	0
T20	993	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2904149	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2904149	0	0
T1	207901	22765	0	0
T2	52049	4	0	0
T3	450	5	0	0
T4	13073	55	0	0
T5	691	3	0	0
T13	4638	94	0	0
T15	2664	24	0	0
T18	4957	298	0	0
T19	43036	283	0	0
T20	993	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1402433	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1402433	0	0
T1	207901	21534	0	0
T2	52049	27	0	0
T3	450	5	0	0
T4	13073	102	0	0
T5	691	8	0	0
T13	4638	101	0	0
T15	2664	15	0	0
T18	4957	272	0	0
T19	43036	356	0	0
T20	993	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2775653	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2775653	0	0
T1	207901	19711	0	0
T2	52049	6	0	0
T3	450	5	0	0
T4	13073	68	0	0
T5	691	8	0	0
T13	4638	101	0	0
T15	2664	15	0	0
T18	4957	272	0	0
T19	43036	399	0	0
T20	993	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1348172	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1348172	0	0
T1	207901	20242	0	0
T2	52049	8	0	0
T3	450	7	0	0
T4	13073	60	0	0
T5	691	4	0	0
T13	4638	93	0	0
T15	2664	30	0	0
T18	4957	482	0	0
T19	43036	266	0	0
T20	993	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3147660	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3147660	0	0
T1	207901	20161	0	0
T2	52049	2	0	0
T3	450	7	0	0
T4	13073	85	0	0
T5	691	4	0	0
T13	4638	93	0	0
T15	2664	30	0	0
T18	4957	482	0	0
T19	43036	298	0	0
T20	993	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1387823	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1387823	0	0
T1	207901	21236	0	0
T2	52049	24	0	0
T3	450	3	0	0
T4	13073	100	0	0
T5	691	7	0	0
T13	4638	86	0	0
T15	2664	34	0	0
T18	4957	0	0	0
T19	43036	354	0	0
T20	993	17	0	0
T21	0	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2999523	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2999523	0	0
T1	207901	21676	0	0
T2	52049	4	0	0
T3	450	3	0	0
T4	13073	77	0	0
T5	691	7	0	0
T13	4638	86	0	0
T15	2664	34	0	0
T18	4957	0	0	0
T19	43036	412	0	0
T20	993	17	0	0
T21	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1368729	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1368729	0	0
T1	207901	14120	0	0
T2	52049	14	0	0
T3	450	4	0	0
T4	13073	21	0	0
T5	691	6	0	0
T13	4638	80	0	0
T15	2664	33	0	0
T18	4957	578	0	0
T19	43036	287	0	0
T20	993	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2153919	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2153919	0	0
T1	207901	18332	0	0
T2	52049	3	0	0
T3	450	4	0	0
T4	13073	36	0	0
T5	691	6	0	0
T13	4638	80	0	0
T15	2664	33	0	0
T18	4957	578	0	0
T19	43036	296	0	0
T20	993	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1401608	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1401608	0	0
T1	207901	19721	0	0
T2	52049	4	0	0
T3	450	5	0	0
T4	13073	28	0	0
T5	691	5	0	0
T13	4638	79	0	0
T15	2664	24	0	0
T18	4957	247	0	0
T19	43036	295	0	0
T20	993	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3402882	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3402882	0	0
T1	207901	21090	0	0
T2	52049	150	0	0
T3	450	5	0	0
T4	13073	36	0	0
T5	691	5	0	0
T13	4638	79	0	0
T15	2664	24	0	0
T18	4957	247	0	0
T19	43036	358	0	0
T20	993	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1357228	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1357228	0	0
T1	207901	22356	0	0
T2	52049	17	0	0
T3	450	9	0	0
T4	13073	38	0	0
T5	691	6	0	0
T13	4638	76	0	0
T15	2664	14	0	0
T18	4957	0	0	0
T19	43036	305	0	0
T20	993	21	0	0
T21	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3066954	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3066954	0	0
T1	207901	17538	0	0
T2	52049	3	0	0
T3	450	9	0	0
T4	13073	42	0	0
T5	691	6	0	0
T13	4638	76	0	0
T15	2664	14	0	0
T18	4957	0	0	0
T19	43036	303	0	0
T20	993	21	0	0
T21	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1404877	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1404877	0	0
T1	207901	21013	0	0
T2	52049	17	0	0
T3	450	7	0	0
T4	13073	880	0	0
T5	691	5	0	0
T13	4638	75	0	0
T15	2664	38	0	0
T18	4957	250	0	0
T19	43036	276	0	0
T20	993	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	4153795	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	4153795	0	0
T1	207901	22345	0	0
T2	52049	5	0	0
T3	450	7	0	0
T4	13073	788	0	0
T5	691	5	0	0
T13	4638	75	0	0
T15	2664	38	0	0
T18	4957	250	0	0
T19	43036	247	0	0
T20	993	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1347373	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1347373	0	0
T1	207901	18065	0	0
T2	52049	19	0	0
T3	450	12	0	0
T4	13073	24	0	0
T5	691	6	0	0
T13	4638	104	0	0
T15	2664	28	0	0
T18	4957	226	0	0
T19	43036	410	0	0
T20	993	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2819602	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2819602	0	0
T1	207901	18547	0	0
T2	52049	5	0	0
T3	450	12	0	0
T4	13073	16	0	0
T5	691	6	0	0
T13	4638	104	0	0
T15	2664	28	0	0
T18	4957	226	0	0
T19	43036	384	0	0
T20	993	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1362194	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1362194	0	0
T1	207901	16393	0	0
T2	52049	12	0	0
T3	450	0	0	0
T4	13073	36	0	0
T5	691	6	0	0
T13	4638	77	0	0
T15	2664	27	0	0
T18	4957	277	0	0
T19	43036	402	0	0
T20	993	19	0	0
T21	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3631513	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3631513	0	0
T1	207901	18417	0	0
T2	52049	4	0	0
T3	450	0	0	0
T4	13073	21	0	0
T5	691	6	0	0
T13	4638	77	0	0
T15	2664	27	0	0
T18	4957	277	0	0
T19	43036	265	0	0
T20	993	19	0	0
T21	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1314223	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1314223	0	0
T1	207901	15605	0	0
T2	52049	10	0	0
T3	450	8	0	0
T4	13073	109	0	0
T5	691	4	0	0
T13	4638	82	0	0
T15	2664	23	0	0
T18	4957	249	0	0
T19	43036	255	0	0
T20	993	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3370365	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3370365	0	0
T1	207901	16022	0	0
T2	52049	2	0	0
T3	450	8	0	0
T4	13073	110	0	0
T5	691	4	0	0
T13	4638	82	0	0
T15	2664	23	0	0
T18	4957	249	0	0
T19	43036	270	0	0
T20	993	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1334671	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1334671	0	0
T1	207901	18501	0	0
T2	52049	16	0	0
T3	450	5	0	0
T4	13073	127	0	0
T5	691	3	0	0
T13	4638	113	0	0
T15	2664	35	0	0
T18	4957	0	0	0
T19	43036	355	0	0
T20	993	18	0	0
T21	0	155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2478290	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2478290	0	0
T1	207901	17153	0	0
T2	52049	3	0	0
T3	450	5	0	0
T4	13073	79	0	0
T5	691	3	0	0
T13	4638	113	0	0
T15	2664	35	0	0
T18	4957	0	0	0
T19	43036	323	0	0
T20	993	18	0	0
T21	0	785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1368661	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1368661	0	0
T1	207901	21162	0	0
T2	52049	12	0	0
T3	450	3	0	0
T4	13073	102	0	0
T5	691	3	0	0
T13	4638	110	0	0
T15	2664	26	0	0
T18	4957	425	0	0
T19	43036	261	0	0
T20	993	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	2563636	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	2563636	0	0
T1	207901	22376	0	0
T2	52049	4	0	0
T3	450	3	0	0
T4	13073	135	0	0
T5	691	3	0	0
T13	4638	110	0	0
T15	2664	26	0	0
T18	4957	425	0	0
T19	43036	326	0	0
T20	993	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	1379569	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	1379569	0	0
T1	207901	19681	0	0
T2	52049	22	0	0
T3	450	3	0	0
T4	13073	61	0	0
T5	691	9	0	0
T13	4638	83	0	0
T15	2664	34	0	0
T18	4957	0	0	0
T19	43036	352	0	0
T20	993	19	0	0
T21	0	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294275832	3551660	0	0
DepthKnown_A	294275832	294141534	0	0
RvalidKnown_A	294275832	294141534	0	0
WreadyKnown_A	294275832	294141534	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	3551660	0	0
T1	207901	23837	0	0
T2	52049	5	0	0
T3	450	3	0	0
T4	13073	84	0	0
T5	691	9	0	0
T13	4638	83	0	0
T15	2664	34	0	0
T18	4957	0	0	0
T19	43036	313	0	0
T20	993	19	0	0
T21	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294275832	294141534	0	0
T1	207901	207893	0	0
T2	52049	52014	0	0
T3	450	436	0	0
T4	13073	12697	0	0
T5	691	642	0	0
T13	4638	4629	0	0
T15	2664	2622	0	0
T18	4957	4912	0	0
T19	43036	42966	0	0
T20	993	986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0