Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1690029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266149

1

T1

13

T2

20

T3

190

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	662570	1			T1	36		T2	96		T3	478
values[0x0]	629667	1			T1	45		T2	20		T3	478
values[0x1]	663941	1			T1	43		T2	102		T3	496

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1309087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

647091

1

T1

43

T2

87

T3

451

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7486	1			T2	1		T14	40		T16	8
valid_sources[0x01]	8391	1			T5	1		T14	38		T16	6
valid_sources[0x02]	7889	1			T4	1		T5	2		T14	37
valid_sources[0x03]	6778	1			T1	2		T4	1		T14	85
valid_sources[0x04]	7559	1			T4	1		T5	4		T14	52
valid_sources[0x05]	7615	1			T1	1		T2	2		T4	1
valid_sources[0x06]	7924	1			T2	1		T14	69		T16	7
valid_sources[0x07]	7932	1			T1	2		T2	2		T5	2
valid_sources[0x08]	7282	1			T2	1		T14	46		T16	7
valid_sources[0x09]	7619	1			T4	1		T5	4		T14	33
valid_sources[0x0a]	8035	1			T1	1		T5	2		T14	45
valid_sources[0x0b]	7265	1			T2	1		T3	4		T14	34
valid_sources[0x0c]	8289	1			T3	32		T4	3		T14	46
valid_sources[0x0d]	8070	1			T5	3		T14	77		T16	8
valid_sources[0x0e]	9213	1			T1	1		T2	1		T3	42
valid_sources[0x0f]	7833	1			T14	59		T16	7		T17	33
valid_sources[0x10]	7410	1			T14	50		T16	11		T17	29
valid_sources[0x11]	7796	1			T14	36		T16	4		T17	38
valid_sources[0x12]	8560	1			T2	2		T4	4		T14	66
valid_sources[0x13]	9430	1			T5	16		T14	43		T16	10
valid_sources[0x14]	7694	1			T2	2		T4	1		T14	34
valid_sources[0x15]	7964	1			T2	2		T14	56		T16	9
valid_sources[0x16]	7460	1			T1	2		T2	1		T4	2
valid_sources[0x17]	7314	1			T14	38		T16	6		T17	24
valid_sources[0x18]	7610	1			T1	2		T2	3		T3	51
valid_sources[0x19]	8479	1			T1	1		T2	2		T14	44
valid_sources[0x1a]	7823	1			T2	1		T14	36		T16	7
valid_sources[0x1b]	8402	1			T2	1		T4	1		T5	2
valid_sources[0x1c]	7078	1			T2	1		T5	6		T14	52
valid_sources[0x1d]	8090	1			T5	2		T14	56		T16	6
valid_sources[0x1e]	8588	1			T5	8		T14	54		T16	4
valid_sources[0x1f]	6839	1			T1	1		T5	1		T14	33
valid_sources[0x20]	9016	1			T1	1		T2	4		T3	8
valid_sources[0x21]	8319	1			T2	1		T14	56		T16	2
valid_sources[0x22]	8111	1			T2	1		T14	62		T16	8
valid_sources[0x23]	9144	1			T4	1		T14	24		T16	7
valid_sources[0x24]	7941	1			T2	3		T3	10		T4	1
valid_sources[0x25]	7940	1			T1	1		T14	36		T16	6
valid_sources[0x26]	7399	1			T1	1		T2	1		T14	58
valid_sources[0x27]	6528	1			T3	12		T4	1		T14	53
valid_sources[0x28]	7234	1			T2	4		T5	4		T14	42
valid_sources[0x29]	7893	1			T1	1		T4	1		T14	35
valid_sources[0x2a]	7982	1			T1	1		T2	1		T14	64
valid_sources[0x2b]	6999	1			T2	1		T14	30		T16	12
valid_sources[0x2c]	7029	1			T1	1		T2	2		T4	1
valid_sources[0x2d]	6881	1			T4	2		T14	54		T16	9
valid_sources[0x2e]	7487	1			T5	7		T14	63		T16	11
valid_sources[0x2f]	9262	1			T1	1		T2	1		T14	77
valid_sources[0x30]	7889	1			T2	1		T4	1		T14	59
valid_sources[0x31]	6886	1			T14	44		T16	7		T17	32
valid_sources[0x32]	7745	1			T2	2		T14	39		T16	8
valid_sources[0x33]	7768	1			T14	63		T16	5		T17	27
valid_sources[0x34]	7570	1			T2	1		T3	60		T4	2
valid_sources[0x35]	7821	1			T1	1		T2	1		T14	51
valid_sources[0x36]	7402	1			T3	69		T14	37		T16	7
valid_sources[0x37]	8465	1			T2	2		T14	31		T16	7
valid_sources[0x38]	7287	1			T14	78		T16	15		T17	35
valid_sources[0x39]	8796	1			T14	59		T16	7		T17	21
valid_sources[0x3a]	7488	1			T2	1		T4	1		T14	38
valid_sources[0x3b]	6999	1			T1	3		T2	1		T3	34
valid_sources[0x3c]	7178	1			T5	3		T14	50		T16	5
valid_sources[0x3d]	7780	1			T14	52		T16	6		T17	30
valid_sources[0x3e]	8672	1			T1	1		T14	64		T16	10
valid_sources[0x3f]	6677	1			T1	1		T5	1		T14	46
valid_sources[0x40]	7546	1			T1	1		T3	47		T14	102
valid_sources[0x41]	6814	1			T1	1		T2	1		T14	52
valid_sources[0x42]	7521	1			T1	1		T2	2		T4	1
valid_sources[0x43]	7081	1			T1	1		T2	2		T14	38
valid_sources[0x44]	7107	1			T1	3		T14	47		T16	4
valid_sources[0x45]	7274	1			T1	2		T14	43		T16	5
valid_sources[0x46]	7670	1			T2	1		T14	60		T16	8
valid_sources[0x47]	6970	1			T2	1		T4	1		T5	3
valid_sources[0x48]	6790	1			T2	1		T3	7		T14	40
valid_sources[0x49]	7227	1			T2	1		T4	1		T5	4
valid_sources[0x4a]	9014	1			T1	1		T2	2		T4	1
valid_sources[0x4b]	7322	1			T3	15		T4	1		T14	33
valid_sources[0x4c]	7048	1			T4	1		T14	58		T16	7
valid_sources[0x4d]	8135	1			T1	1		T2	1		T3	2
valid_sources[0x4e]	7339	1			T1	1		T2	3		T14	68
valid_sources[0x4f]	7655	1			T5	2		T14	67		T16	7
valid_sources[0x50]	7713	1			T4	2		T14	42		T16	7
valid_sources[0x51]	7647	1			T3	51		T14	96		T16	10
valid_sources[0x52]	7204	1			T14	63		T16	10		T17	42
valid_sources[0x53]	7514	1			T1	1		T5	7		T14	45
valid_sources[0x54]	7006	1			T3	14		T14	44		T16	6
valid_sources[0x55]	7209	1			T2	1		T4	1		T14	90
valid_sources[0x56]	7892	1			T1	1		T14	35		T16	8
valid_sources[0x57]	7396	1			T1	1		T14	68		T16	11
valid_sources[0x58]	6747	1			T2	4		T14	31		T16	7
valid_sources[0x59]	7133	1			T5	1		T14	51		T16	6
valid_sources[0x5a]	6932	1			T5	5		T14	69		T16	8
valid_sources[0x5b]	7832	1			T2	1		T14	38		T16	4
valid_sources[0x5c]	8287	1			T1	2		T2	1		T14	46
valid_sources[0x5d]	7666	1			T2	3		T3	22		T4	1
valid_sources[0x5e]	7799	1			T3	81		T4	1		T5	2
valid_sources[0x5f]	7980	1			T1	2		T2	2		T3	33
valid_sources[0x60]	7857	1			T2	1		T5	2		T14	74
valid_sources[0x61]	8149	1			T1	1		T5	4		T14	56
valid_sources[0x62]	6852	1			T1	1		T4	1		T14	44
valid_sources[0x63]	7929	1			T1	2		T2	1		T14	28
valid_sources[0x64]	8083	1			T4	2		T14	49		T16	8
valid_sources[0x65]	7268	1			T4	1		T14	51		T16	11
valid_sources[0x66]	7875	1			T1	1		T2	2		T14	70
valid_sources[0x67]	7867	1			T1	1		T2	5		T14	53
valid_sources[0x68]	7671	1			T2	1		T4	1		T14	35
valid_sources[0x69]	7090	1			T1	2		T2	1		T4	1
valid_sources[0x6a]	7517	1			T15	72		T14	40		T16	12
valid_sources[0x6b]	7711	1			T1	2		T3	2		T14	52
valid_sources[0x6c]	7033	1			T14	43		T16	8		T17	25
valid_sources[0x6d]	7876	1			T1	2		T3	39		T4	1
valid_sources[0x6e]	7155	1			T4	1		T14	58		T16	4
valid_sources[0x6f]	6295	1			T1	1		T2	1		T4	1
valid_sources[0x70]	6962	1			T1	1		T14	56		T16	3
valid_sources[0x71]	8466	1			T2	1		T5	2		T14	31
valid_sources[0x72]	8150	1			T2	1		T5	1		T14	31
valid_sources[0x73]	7856	1			T2	1		T4	1		T14	54
valid_sources[0x74]	6951	1			T2	2		T14	54		T16	5
valid_sources[0x75]	7140	1			T3	19		T4	2		T5	6
valid_sources[0x76]	7667	1			T1	1		T3	24		T14	45
valid_sources[0x77]	7105	1			T1	1		T14	37		T16	9
valid_sources[0x78]	7130	1			T4	1		T14	29		T16	2
valid_sources[0x79]	6841	1			T3	30		T4	1		T5	5
valid_sources[0x7a]	8133	1			T4	1		T14	44		T16	7
valid_sources[0x7b]	7371	1			T1	2		T2	3		T4	1
valid_sources[0x7c]	8472	1			T2	1		T5	1		T14	43
valid_sources[0x7d]	7043	1			T1	2		T2	1		T14	106
valid_sources[0x7e]	7294	1			T2	3		T14	30		T16	4
valid_sources[0x7f]	7405	1			T2	1		T4	1		T14	54
valid_sources[0x80]	7133	1			T2	1		T4	2		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28441

1

T1

2

T2

6

T3

26

values[0x0]

all_enables

biggest_size

209379

1

T1

10

T2

11

T3

152

values[0x1]

all_enables

biggest_size

28329

1

T1

1

T2

3

T3

12