Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	340790504	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	340790504	0	0
T1	35840	612	0	0
T2	560056	21783	0	0
T3	1459920	20329	0	0
T4	4163544	73873	0	0
T5	43120	952	0	0
T14	14620872	273659	0	0
T15	28280	713	0	0
T16	49275576	874857	0	0
T17	11823336	203875	0	0
T18	130704	2559	0	0
T19	0	1030	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	35840	32312	0	0
T2	560056	558712	0	0
T3	1459920	1455720	0	0
T4	4163544	4161304	0	0
T5	43120	39984	0	0
T14	14620872	14611576	0	0
T15	28280	26432	0	0
T16	49275576	49272160	0	0
T17	11823336	11751880	0	0
T18	130704	129304	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	35840	32312	0	0
T2	560056	558712	0	0
T3	1459920	1455720	0	0
T4	4163544	4161304	0	0
T5	43120	39984	0	0
T14	14620872	14611576	0	0
T15	28280	26432	0	0
T16	49275576	49272160	0	0
T17	11823336	11751880	0	0
T18	130704	129304	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	35840	32312	0	0
T2	560056	558712	0	0
T3	1459920	1455720	0	0
T4	4163544	4161304	0	0
T5	43120	39984	0	0
T14	14620872	14611576	0	0
T15	28280	26432	0	0
T16	49275576	49272160	0	0
T17	11823336	11751880	0	0
T18	130704	129304	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	127276326	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	127276326	0	0
T1	640	240	0	0
T2	10001	8516	0	0
T3	26070	9348	0	0
T4	74349	72430	0	0
T5	770	373	0	0
T14	261087	126681	0	0
T15	505	281	0	0
T16	879921	854946	0	0
T17	211131	78730	0	0
T18	2334	950	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	87266436	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	87266436	0	0
T1	640	124	0	0
T2	10001	5037	0	0
T3	26070	3075	0	0
T4	74349	408	0	0
T5	770	193	0	0
T14	261087	34782	0	0
T15	505	144	0	0
T16	879921	6209	0	0
T17	211131	34920	0	0
T18	2334	875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1423909	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1423909	0	0
T1	640	2	0	0
T2	10001	163	0	0
T3	26070	205	0	0
T4	74349	18	0	0
T5	770	11	0	0
T14	261087	4730	0	0
T15	505	4	0	0
T16	879921	265	0	0
T17	211131	3189	0	0
T18	2334	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	2958875	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	2958875	0	0
T1	640	2	0	0
T2	10001	163	0	0
T3	26070	65	0	0
T4	74349	4	0	0
T5	770	11	0	0
T14	261087	1835	0	0
T15	505	4	0	0
T16	879921	58	0	0
T17	211131	1701	0	0
T18	2334	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1478761	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1478761	0	0
T1	640	6	0	0
T2	10001	162	0	0
T3	26070	213	0	0
T4	74349	3	0	0
T5	770	5	0	0
T14	261087	2333	0	0
T15	505	5	0	0
T16	879921	210	0	0
T17	211131	1950	0	0
T18	2334	0	0	0
T19	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3029738	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3029738	0	0
T1	640	6	0	0
T2	10001	162	0	0
T3	26070	69	0	0
T4	74349	1	0	0
T5	770	5	0	0
T14	261087	1009	0	0
T15	505	5	0	0
T16	879921	64	0	0
T17	211131	1112	0	0
T18	2334	0	0	0
T19	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1524509	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1524509	0	0
T1	640	8	0	0
T2	10001	131	0	0
T3	26070	241	0	0
T4	74349	32	0	0
T5	770	6	0	0
T14	261087	2392	0	0
T15	505	4	0	0
T16	879921	235	0	0
T17	211131	2282	0	0
T18	2334	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3393359	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3393359	0	0
T1	640	8	0	0
T2	10001	131	0	0
T3	26070	108	0	0
T4	74349	7	0	0
T5	770	6	0	0
T14	261087	1086	0	0
T15	505	4	0	0
T16	879921	58	0	0
T17	211131	1384	0	0
T18	2334	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1459596	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1459596	0	0
T1	640	8	0	0
T2	10001	163	0	0
T3	26070	181	0	0
T4	74349	29	0	0
T5	770	8	0	0
T14	261087	2620	0	0
T15	505	3	0	0
T16	879921	237	0	0
T17	211131	1956	0	0
T18	2334	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3588232	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3588232	0	0
T1	640	8	0	0
T2	10001	163	0	0
T3	26070	61	0	0
T4	74349	5	0	0
T5	770	8	0	0
T14	261087	1010	0	0
T15	505	3	0	0
T16	879921	136	0	0
T17	211131	1081	0	0
T18	2334	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1484193	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1484193	0	0
T1	640	5	0	0
T2	10001	148	0	0
T3	26070	261	0	0
T4	74349	31	0	0
T5	770	7	0	0
T14	261087	2466	0	0
T15	505	14	0	0
T16	879921	313	0	0
T17	211131	2134	0	0
T18	2334	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	2746431	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	2746431	0	0
T1	640	5	0	0
T2	10001	148	0	0
T3	26070	87	0	0
T4	74349	7	0	0
T5	770	7	0	0
T14	261087	994	0	0
T15	505	14	0	0
T16	879921	925	0	0
T17	211131	1392	0	0
T18	2334	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1448764	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1448764	0	0
T1	640	8	0	0
T2	10001	157	0	0
T3	26070	275	0	0
T4	74349	41	0	0
T5	770	8	0	0
T14	261087	2357	0	0
T15	505	3	0	0
T16	879921	319	0	0
T17	211131	1597	0	0
T18	2334	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3003374	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3003374	0	0
T1	640	8	0	0
T2	10001	157	0	0
T3	26070	91	0	0
T4	74349	9	0	0
T5	770	8	0	0
T14	261087	862	0	0
T15	505	3	0	0
T16	879921	69	0	0
T17	211131	875	0	0
T18	2334	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1486342	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1486342	0	0
T1	640	6	0	0
T2	10001	162	0	0
T3	26070	218	0	0
T4	74349	30	0	0
T5	770	8	0	0
T14	261087	2382	0	0
T15	505	3	0	0
T16	879921	406	0	0
T17	211131	1990	0	0
T18	2334	0	0	0
T19	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3541623	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3541623	0	0
T1	640	6	0	0
T2	10001	162	0	0
T3	26070	120	0	0
T4	74349	7	0	0
T5	770	8	0	0
T14	261087	1034	0	0
T15	505	3	0	0
T16	879921	1027	0	0
T17	211131	1143	0	0
T18	2334	0	0	0
T19	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1456870	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1456870	0	0
T1	640	3	0	0
T2	10001	138	0	0
T3	26070	138	0	0
T4	74349	21	0	0
T5	770	5	0	0
T14	261087	4368	0	0
T15	505	5	0	0
T16	879921	268	0	0
T17	211131	2377	0	0
T18	2334	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3185517	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3185517	0	0
T1	640	3	0	0
T2	10001	138	0	0
T3	26070	74	0	0
T4	74349	6	0	0
T5	770	5	0	0
T14	261087	1824	0	0
T15	505	5	0	0
T16	879921	62	0	0
T17	211131	1312	0	0
T18	2334	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1463924	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1463924	0	0
T1	640	4	0	0
T2	10001	166	0	0
T3	26070	298	0	0
T4	74349	36	0	0
T5	770	3	0	0
T14	261087	2163	0	0
T15	505	4	0	0
T16	879921	339	0	0
T17	211131	1922	0	0
T18	2334	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3774663	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3774663	0	0
T1	640	4	0	0
T2	10001	166	0	0
T3	26070	99	0	0
T4	74349	7	0	0
T5	770	3	0	0
T14	261087	867	0	0
T15	505	4	0	0
T16	879921	74	0	0
T17	211131	1138	0	0
T18	2334	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1442206	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1442206	0	0
T1	640	4	0	0
T2	10001	155	0	0
T3	26070	295	0	0
T4	74349	24	0	0
T5	770	3	0	0
T14	261087	2220	0	0
T15	505	5	0	0
T16	879921	222	0	0
T17	211131	1849	0	0
T18	2334	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3037231	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3037231	0	0
T1	640	4	0	0
T2	10001	155	0	0
T3	26070	97	0	0
T4	74349	7	0	0
T5	770	3	0	0
T14	261087	941	0	0
T15	505	5	0	0
T16	879921	57	0	0
T17	211131	1021	0	0
T18	2334	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1438611	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1438611	0	0
T1	640	4	0	0
T2	10001	143	0	0
T3	26070	240	0	0
T4	74349	5	0	0
T5	770	6	0	0
T14	261087	5033	0	0
T15	505	3	0	0
T16	879921	275	0	0
T17	211131	2166	0	0
T18	2334	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3028917	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3028917	0	0
T1	640	4	0	0
T2	10001	143	0	0
T3	26070	98	0	0
T4	74349	1	0	0
T5	770	6	0	0
T14	261087	1810	0	0
T15	505	3	0	0
T16	879921	59	0	0
T17	211131	1302	0	0
T18	2334	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1487326	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1487326	0	0
T1	640	5	0	0
T2	10001	144	0	0
T3	26070	188	0	0
T4	74349	8	0	0
T5	770	7	0	0
T14	261087	3910	0	0
T15	505	6	0	0
T16	879921	344	0	0
T17	211131	2023	0	0
T18	2334	0	0	0
T19	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3494742	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3494742	0	0
T1	640	5	0	0
T2	10001	144	0	0
T3	26070	76	0	0
T4	74349	1	0	0
T5	770	7	0	0
T14	261087	1666	0	0
T15	505	6	0	0
T16	879921	261	0	0
T17	211131	1172	0	0
T18	2334	0	0	0
T19	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1500041	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1500041	0	0
T1	640	5	0	0
T2	10001	143	0	0
T3	26070	243	0	0
T4	74349	4	0	0
T5	770	8	0	0
T14	261087	2510	0	0
T15	505	5	0	0
T16	879921	259	0	0
T17	211131	2024	0	0
T18	2334	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3272937	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3272937	0	0
T1	640	5	0	0
T2	10001	143	0	0
T3	26070	108	0	0
T4	74349	2	0	0
T5	770	8	0	0
T14	261087	961	0	0
T15	505	5	0	0
T16	879921	60	0	0
T17	211131	1118	0	0
T18	2334	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1487451	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1487451	0	0
T1	640	2	0	0
T2	10001	149	0	0
T3	26070	172	0	0
T4	74349	21	0	0
T5	770	7	0	0
T14	261087	2628	0	0
T15	505	4	0	0
T16	879921	294	0	0
T17	211131	1796	0	0
T18	2334	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3423168	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3423168	0	0
T1	640	2	0	0
T2	10001	149	0	0
T3	26070	96	0	0
T4	74349	8	0	0
T5	770	7	0	0
T14	261087	1030	0	0
T15	505	4	0	0
T16	879921	70	0	0
T17	211131	1025	0	0
T18	2334	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1462792	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1462792	0	0
T1	640	4	0	0
T2	10001	147	0	0
T3	26070	125	0	0
T4	74349	23	0	0
T5	770	16	0	0
T14	261087	2351	0	0
T15	505	8	0	0
T16	879921	249	0	0
T17	211131	1728	0	0
T18	2334	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3251237	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3251237	0	0
T1	640	4	0	0
T2	10001	147	0	0
T3	26070	63	0	0
T4	74349	5	0	0
T5	770	16	0	0
T14	261087	993	0	0
T15	505	8	0	0
T16	879921	57	0	0
T17	211131	1217	0	0
T18	2334	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1413958	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1413958	0	0
T1	640	8	0	0
T2	10001	145	0	0
T3	26070	185	0	0
T4	74349	18	0	0
T5	770	14	0	0
T14	261087	2270	0	0
T15	505	7	0	0
T16	879921	290	0	0
T17	211131	1760	0	0
T18	2334	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	2971334	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	2971334	0	0
T1	640	8	0	0
T2	10001	145	0	0
T3	26070	69	0	0
T4	74349	4	0	0
T5	770	14	0	0
T14	261087	1004	0	0
T15	505	7	0	0
T16	879921	67	0	0
T17	211131	1125	0	0
T18	2334	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1503005	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1503005	0	0
T1	640	4	0	0
T2	10001	133	0	0
T3	26070	159	0	0
T4	74349	36	0	0
T5	770	6	0	0
T14	261087	3907	0	0
T15	505	7	0	0
T16	879921	327	0	0
T17	211131	1969	0	0
T18	2334	0	0	0
T19	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	2481962	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	2481962	0	0
T1	640	4	0	0
T2	10001	133	0	0
T3	26070	98	0	0
T4	74349	7	0	0
T5	770	6	0	0
T14	261087	1616	0	0
T15	505	7	0	0
T16	879921	259	0	0
T17	211131	1230	0	0
T18	2334	0	0	0
T19	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1506502	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1506502	0	0
T1	640	1	0	0
T2	10001	153	0	0
T3	26070	111	0	0
T4	74349	23	0	0
T5	770	2	0	0
T14	261087	1976	0	0
T15	505	1	0	0
T16	879921	287	0	0
T17	211131	2001	0	0
T18	2334	0	0	0
T19	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3097999	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3097999	0	0
T1	640	1	0	0
T2	10001	153	0	0
T3	26070	66	0	0
T4	74349	5	0	0
T5	770	2	0	0
T14	261087	933	0	0
T15	505	1	0	0
T16	879921	61	0	0
T17	211131	1226	0	0
T18	2334	0	0	0
T19	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1513561	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1513561	0	0
T1	640	4	0	0
T2	10001	153	0	0
T3	26070	270	0	0
T4	74349	9	0	0
T5	770	9	0	0
T14	261087	2684	0	0
T15	505	6	0	0
T16	879921	285	0	0
T17	211131	2239	0	0
T18	2334	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3029537	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3029537	0	0
T1	640	4	0	0
T2	10001	153	0	0
T3	26070	133	0	0
T4	74349	2	0	0
T5	770	9	0	0
T14	261087	963	0	0
T15	505	6	0	0
T16	879921	812	0	0
T17	211131	1263	0	0
T18	2334	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1507395	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1507395	0	0
T1	640	2	0	0
T2	10001	159	0	0
T3	26070	219	0	0
T4	74349	17	0	0
T5	770	6	0	0
T14	261087	2428	0	0
T15	505	5	0	0
T16	879921	229	0	0
T17	211131	2141	0	0
T18	2334	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3040461	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3040461	0	0
T1	640	2	0	0
T2	10001	159	0	0
T3	26070	88	0	0
T4	74349	4	0	0
T5	770	6	0	0
T14	261087	907	0	0
T15	505	5	0	0
T16	879921	48	0	0
T17	211131	1264	0	0
T18	2334	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1434026	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1434026	0	0
T1	640	5	0	0
T2	10001	142	0	0
T3	26070	259	0	0
T4	74349	35	0	0
T5	770	6	0	0
T14	261087	4067	0	0
T15	505	5	0	0
T16	879921	250	0	0
T17	211131	2236	0	0
T18	2334	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3820118	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3820118	0	0
T1	640	5	0	0
T2	10001	142	0	0
T3	26070	135	0	0
T4	74349	6	0	0
T5	770	6	0	0
T14	261087	1662	0	0
T15	505	5	0	0
T16	879921	740	0	0
T17	211131	1366	0	0
T18	2334	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1479624	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1479624	0	0
T1	640	7	0	0
T2	10001	156	0	0
T3	26070	147	0	0
T4	74349	49	0	0
T5	770	4	0	0
T14	261087	4019	0	0
T15	505	6	0	0
T16	879921	266	0	0
T17	211131	2250	0	0
T18	2334	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3136625	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3136625	0	0
T1	640	7	0	0
T2	10001	156	0	0
T3	26070	57	0	0
T4	74349	11	0	0
T5	770	4	0	0
T14	261087	1550	0	0
T15	505	6	0	0
T16	879921	70	0	0
T17	211131	1256	0	0
T18	2334	0	0	0
T19	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1490209	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1490209	0	0
T1	640	8	0	0
T2	10001	150	0	0
T3	26070	202	0	0
T4	74349	17	0	0
T5	770	7	0	0
T14	261087	2594	0	0
T15	505	7	0	0
T16	879921	240	0	0
T17	211131	1965	0	0
T18	2334	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3220312	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3220312	0	0
T1	640	8	0	0
T2	10001	150	0	0
T3	26070	77	0	0
T4	74349	3	0	0
T5	770	7	0	0
T14	261087	1043	0	0
T15	505	7	0	0
T16	879921	62	0	0
T17	211131	1187	0	0
T18	2334	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1472288	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1472288	0	0
T1	640	2	0	0
T2	10001	152	0	0
T3	26070	260	0	0
T4	74349	35	0	0
T5	770	7	0	0
T14	261087	2611	0	0
T15	505	7	0	0
T16	879921	220	0	0
T17	211131	1845	0	0
T18	2334	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3060951	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3060951	0	0
T1	640	2	0	0
T2	10001	152	0	0
T3	26070	72	0	0
T4	74349	6	0	0
T5	770	7	0	0
T14	261087	1199	0	0
T15	505	7	0	0
T16	879921	52	0	0
T17	211131	1116	0	0
T18	2334	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1491773	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1491773	0	0
T1	640	1	0	0
T2	10001	173	0	0
T3	26070	140	0	0
T4	74349	14	0	0
T5	770	12	0	0
T14	261087	4060	0	0
T15	505	7	0	0
T16	879921	289	0	0
T17	211131	1858	0	0
T18	2334	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	2989511	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	2989511	0	0
T1	640	1	0	0
T2	10001	173	0	0
T3	26070	78	0	0
T4	74349	4	0	0
T5	770	12	0	0
T14	261087	1691	0	0
T15	505	7	0	0
T16	879921	587	0	0
T17	211131	1221	0	0
T18	2334	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1451337	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1451337	0	0
T1	640	3	0	0
T2	10001	166	0	0
T3	26070	174	0	0
T4	74349	21	0	0
T5	770	7	0	0
T14	261087	2610	0	0
T15	505	3	0	0
T16	879921	327	0	0
T17	211131	2906	0	0
T18	2334	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3079150	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3079150	0	0
T1	640	3	0	0
T2	10001	166	0	0
T3	26070	90	0	0
T4	74349	271	0	0
T5	770	7	0	0
T14	261087	1084	0	0
T15	505	3	0	0
T16	879921	358	0	0
T17	211131	1485	0	0
T18	2334	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	1499732	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	1499732	0	0
T1	640	5	0	0
T2	10001	162	0	0
T3	26070	139	0	0
T4	74349	27	0	0
T5	770	5	0	0
T14	261087	2122	0	0
T15	505	7	0	0
T16	879921	249	0	0
T17	211131	2474	0	0
T18	2334	0	0	0
T19	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	309955590	3781033	0	0
DepthKnown_A	309955590	309824554	0	0
RvalidKnown_A	309955590	309824554	0	0
WreadyKnown_A	309955590	309824554	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	3781033	0	0
T1	640	5	0	0
T2	10001	162	0	0
T3	26070	73	0	0
T4	74349	8	0	0
T5	770	5	0	0
T14	261087	811	0	0
T15	505	7	0	0
T16	879921	55	0	0
T17	211131	1866	0	0
T18	2334	0	0	0
T19	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309955590	309824554	0	0
T1	640	577	0	0
T2	10001	9977	0	0
T3	26070	25995	0	0
T4	74349	74309	0	0
T5	770	714	0	0
T14	261087	260921	0	0
T15	505	472	0	0
T16	879921	879860	0	0
T17	211131	209855	0	0
T18	2334	2309	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0