Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1684188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265645

1

T1

3435

T2

353

T3

523

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	657673	1			T1	8484		T2	921		T3	1380
values[0x0]	634972	1			T1	8277		T2	877		T3	1373
values[0x1]	657188	1			T1	8591		T2	896		T3	1375

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1306133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

643700

1

T1

8269

T2

865

T3

1341

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7342	1			T1	61		T2	9		T3	18
valid_sources[0x01]	7257	1			T1	75		T2	7		T3	12
valid_sources[0x02]	7407	1			T1	120		T2	12		T3	24
valid_sources[0x03]	7975	1			T1	97		T2	7		T3	14
valid_sources[0x04]	7768	1			T1	114		T2	11		T3	12
valid_sources[0x05]	7334	1			T1	110		T2	19		T3	9
valid_sources[0x06]	7427	1			T1	78		T2	8		T3	19
valid_sources[0x07]	7292	1			T1	69		T2	11		T3	12
valid_sources[0x08]	7703	1			T1	98		T2	10		T3	7
valid_sources[0x09]	7633	1			T1	128		T2	17		T3	13
valid_sources[0x0a]	6971	1			T1	103		T2	7		T3	10
valid_sources[0x0b]	7294	1			T1	91		T2	10		T3	24
valid_sources[0x0c]	6863	1			T1	136		T2	5		T3	13
valid_sources[0x0d]	8048	1			T1	153		T2	3		T3	7
valid_sources[0x0e]	7521	1			T1	79		T2	12		T3	13
valid_sources[0x0f]	7410	1			T1	112		T2	13		T3	11
valid_sources[0x10]	7494	1			T1	116		T2	4		T3	8
valid_sources[0x11]	7220	1			T1	109		T2	6		T3	20
valid_sources[0x12]	8049	1			T1	114		T2	6		T3	11
valid_sources[0x13]	7179	1			T1	143		T2	15		T3	15
valid_sources[0x14]	6723	1			T1	111		T2	7		T3	18
valid_sources[0x15]	7678	1			T1	78		T2	13		T3	9
valid_sources[0x16]	8068	1			T1	88		T2	21		T3	15
valid_sources[0x17]	7196	1			T1	136		T2	6		T3	10
valid_sources[0x18]	8296	1			T1	115		T2	9		T3	11
valid_sources[0x19]	7305	1			T1	74		T2	20		T3	17
valid_sources[0x1a]	6619	1			T1	88		T2	18		T3	9
valid_sources[0x1b]	7165	1			T1	70		T2	14		T3	7
valid_sources[0x1c]	7124	1			T1	102		T2	11		T3	16
valid_sources[0x1d]	7502	1			T1	45		T2	9		T3	28
valid_sources[0x1e]	7728	1			T1	134		T2	13		T3	19
valid_sources[0x1f]	7941	1			T1	103		T2	12		T3	22
valid_sources[0x20]	6900	1			T1	116		T2	14		T3	15
valid_sources[0x21]	7592	1			T1	123		T2	10		T3	16
valid_sources[0x22]	7324	1			T1	86		T2	8		T3	19
valid_sources[0x23]	8175	1			T1	88		T2	9		T3	11
valid_sources[0x24]	6937	1			T1	58		T2	12		T3	23
valid_sources[0x25]	8058	1			T1	101		T2	9		T3	8
valid_sources[0x26]	6932	1			T1	104		T2	8		T3	22
valid_sources[0x27]	7302	1			T1	111		T2	1		T3	10
valid_sources[0x28]	7253	1			T1	100		T2	21		T3	13
valid_sources[0x29]	7128	1			T1	83		T2	13		T3	21
valid_sources[0x2a]	7323	1			T1	82		T2	5		T3	15
valid_sources[0x2b]	6943	1			T1	99		T2	16		T3	18
valid_sources[0x2c]	6898	1			T1	88		T2	12		T3	25
valid_sources[0x2d]	7968	1			T1	88		T2	7		T3	13
valid_sources[0x2e]	7617	1			T1	96		T2	6		T3	24
valid_sources[0x2f]	7351	1			T1	111		T2	9		T3	21
valid_sources[0x30]	7465	1			T1	96		T2	9		T3	8
valid_sources[0x31]	7763	1			T1	91		T2	28		T3	24
valid_sources[0x32]	7590	1			T1	115		T2	11		T3	9
valid_sources[0x33]	7517	1			T1	93		T2	11		T3	13
valid_sources[0x34]	7637	1			T1	74		T2	14		T3	16
valid_sources[0x35]	8077	1			T1	101		T2	14		T3	19
valid_sources[0x36]	7580	1			T1	87		T2	11		T3	12
valid_sources[0x37]	8078	1			T1	102		T2	6		T3	13
valid_sources[0x38]	7795	1			T1	113		T2	13		T3	16
valid_sources[0x39]	6914	1			T1	82		T2	6		T3	16
valid_sources[0x3a]	8610	1			T1	59		T2	10		T3	13
valid_sources[0x3b]	7321	1			T1	81		T2	4		T3	9
valid_sources[0x3c]	7938	1			T1	102		T2	19		T3	16
valid_sources[0x3d]	8924	1			T1	128		T2	3		T3	8
valid_sources[0x3e]	7463	1			T1	145		T2	3		T3	17
valid_sources[0x3f]	6986	1			T1	113		T2	14		T3	23
valid_sources[0x40]	8492	1			T1	79		T2	11		T3	17
valid_sources[0x41]	6846	1			T1	98		T2	10		T3	11
valid_sources[0x42]	7625	1			T1	111		T2	7		T3	14
valid_sources[0x43]	7131	1			T1	88		T2	8		T3	20
valid_sources[0x44]	8037	1			T1	76		T2	15		T3	16
valid_sources[0x45]	7137	1			T1	104		T2	9		T3	24
valid_sources[0x46]	7388	1			T1	128		T2	14		T3	15
valid_sources[0x47]	7838	1			T1	108		T2	7		T3	16
valid_sources[0x48]	6894	1			T1	119		T2	9		T3	16
valid_sources[0x49]	7209	1			T1	116		T2	4		T3	32
valid_sources[0x4a]	9033	1			T1	67		T2	14		T3	26
valid_sources[0x4b]	7161	1			T1	84		T2	6		T3	15
valid_sources[0x4c]	6753	1			T1	71		T2	14		T3	22
valid_sources[0x4d]	8500	1			T1	117		T2	20		T3	12
valid_sources[0x4e]	7739	1			T1	164		T2	16		T3	20
valid_sources[0x4f]	7667	1			T1	100		T2	21		T3	11
valid_sources[0x50]	7793	1			T1	109		T2	6		T3	20
valid_sources[0x51]	7804	1			T1	83		T2	5		T3	9
valid_sources[0x52]	8197	1			T1	104		T2	10		T3	25
valid_sources[0x53]	7249	1			T1	100		T2	6		T3	9
valid_sources[0x54]	8012	1			T1	62		T2	9		T3	14
valid_sources[0x55]	7683	1			T1	71		T2	18		T3	9
valid_sources[0x56]	7040	1			T1	81		T2	7		T3	13
valid_sources[0x57]	7510	1			T1	96		T2	20		T3	15
valid_sources[0x58]	6961	1			T1	103		T2	8		T3	21
valid_sources[0x59]	8641	1			T1	69		T2	10		T3	16
valid_sources[0x5a]	6888	1			T1	71		T2	14		T3	11
valid_sources[0x5b]	8746	1			T1	109		T2	12		T3	13
valid_sources[0x5c]	7591	1			T1	112		T2	11		T3	7
valid_sources[0x5d]	8202	1			T1	79		T2	14		T3	14
valid_sources[0x5e]	7401	1			T1	122		T2	7		T3	16
valid_sources[0x5f]	7046	1			T1	132		T2	14		T3	19
valid_sources[0x60]	6969	1			T1	81		T2	3		T3	13
valid_sources[0x61]	7731	1			T1	96		T2	14		T3	21
valid_sources[0x62]	7181	1			T1	86		T2	12		T3	19
valid_sources[0x63]	7399	1			T1	104		T2	14		T3	19
valid_sources[0x64]	7370	1			T1	98		T2	7		T3	8
valid_sources[0x65]	7323	1			T1	106		T2	6		T3	19
valid_sources[0x66]	8489	1			T1	125		T2	11		T3	15
valid_sources[0x67]	7840	1			T1	108		T2	9		T3	27
valid_sources[0x68]	7609	1			T1	95		T2	4		T3	15
valid_sources[0x69]	7736	1			T1	106		T2	7		T3	11
valid_sources[0x6a]	8666	1			T1	85		T2	3		T3	12
valid_sources[0x6b]	7390	1			T1	79		T2	21		T3	21
valid_sources[0x6c]	7513	1			T1	113		T2	9		T3	21
valid_sources[0x6d]	10583	1			T1	82		T2	8		T3	14
valid_sources[0x6e]	7636	1			T1	99		T2	4		T3	14
valid_sources[0x6f]	7124	1			T1	135		T2	6		T3	11
valid_sources[0x70]	8658	1			T1	95		T2	1		T3	15
valid_sources[0x71]	7714	1			T1	100		T2	12		T3	16
valid_sources[0x72]	8057	1			T1	123		T2	8		T3	13
valid_sources[0x73]	8887	1			T1	97		T2	11		T3	21
valid_sources[0x74]	7532	1			T1	87		T2	5		T3	15
valid_sources[0x75]	8268	1			T1	73		T2	4		T3	18
valid_sources[0x76]	7381	1			T1	50		T2	10		T3	24
valid_sources[0x77]	7607	1			T1	77		T2	20		T3	11
valid_sources[0x78]	7092	1			T1	68		T2	26		T3	7
valid_sources[0x79]	7111	1			T1	140		T2	4		T3	25
valid_sources[0x7a]	8452	1			T1	68		T2	7		T3	19
valid_sources[0x7b]	7736	1			T1	102		T2	9		T3	15
valid_sources[0x7c]	7509	1			T1	59		T2	7		T3	14
valid_sources[0x7d]	7645	1			T1	166		T2	10		T3	17
valid_sources[0x7e]	7056	1			T1	118		T2	9		T3	10
valid_sources[0x7f]	8244	1			T1	100		T2	15		T3	19
valid_sources[0x80]	7948	1			T1	87		T2	6		T3	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27732

1

T1

337

T2

32

T3

47

values[0x0]

all_enables

biggest_size

210140

1

T1

2752

T2

280

T3

421

values[0x1]

all_enables

biggest_size

27773

1

T1

346

T2

41

T3

55