Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	335842611	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335842611	0	0
T1	41657896	886478	0	0
T2	295232	13225	0	0
T3	4479776	126795	0	0
T4	2271752	48478	0	0
T5	12752096	228065	0	0
T14	4365536	76939	0	0
T15	31964184	725086	0	0
T16	0	60978	0	0
T17	74760	1776	0	0
T18	11976608	272576	0	0
T19	7948920	1126414	0	0
T20	0	12114	0	0
T21	0	2355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41657896	41553848	0	0
T2	295232	294392	0	0
T3	4479776	4477312	0	0
T4	2271752	2270016	0	0
T5	12752096	12667984	0	0
T14	4365536	4362848	0	0
T15	31964184	31961720	0	0
T17	74760	69552	0	0
T18	11976608	11975880	0	0
T19	7948920	7948696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41657896	41553848	0	0
T2	295232	294392	0	0
T3	4479776	4477312	0	0
T4	2271752	2270016	0	0
T5	12752096	12667984	0	0
T14	4365536	4362848	0	0
T15	31964184	31961720	0	0
T17	74760	69552	0	0
T18	11976608	11975880	0	0
T19	7948920	7948696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41657896	41553848	0	0
T2	295232	294392	0	0
T3	4479776	4477312	0	0
T4	2271752	2270016	0	0
T5	12752096	12667984	0	0
T14	4365536	4362848	0	0
T15	31964184	31961720	0	0
T17	74760	69552	0	0
T18	11976608	11975880	0	0
T19	7948920	7948696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	120906292	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	120906292	0	0
T1	743891	316571	0	0
T2	5272	5145	0	0
T3	79996	29414	0	0
T4	40567	16733	0	0
T5	227716	99103	0	0
T14	77956	74251	0	0
T15	570789	301578	0	0
T17	1335	445	0	0
T18	213868	111587	0	0
T19	141945	7028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	88356316	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	88356316	0	0
T1	743891	208735	0	0
T2	5272	2694	0	0
T3	79996	33989	0	0
T4	40567	7506	0	0
T5	227716	32641	0	0
T14	77956	1016	0	0
T15	570789	144651	0	0
T17	1335	445	0	0
T18	213868	53790	0	0
T19	141945	556179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1442138	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1442138	0	0
T1	743891	6057	0	0
T2	5272	93	0	0
T3	79996	0	0	0
T4	40567	2123	0	0
T5	227716	2400	0	0
T14	77956	0	0	0
T15	570789	5615	0	0
T16	0	2232	0	0
T17	1335	10	0	0
T18	213868	946	0	0
T19	141945	1212	0	0
T20	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2503613	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2503613	0	0
T1	743891	5976	0	0
T2	5272	93	0	0
T3	79996	0	0	0
T4	40567	882	0	0
T5	227716	1061	0	0
T14	77956	0	0	0
T15	570789	5070	0	0
T16	0	2226	0	0
T17	1335	10	0	0
T18	213868	235	0	0
T19	141945	90231	0	0
T20	0	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1445572	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1445572	0	0
T1	743891	7713	0	0
T2	5272	94	0	0
T3	79996	2177	0	0
T4	40567	0	0	0
T5	227716	2363	0	0
T14	77956	17	0	0
T15	570789	7868	0	0
T16	0	584	0	0
T17	1335	13	0	0
T18	213868	1733	0	0
T19	141945	0	0	0
T20	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3573606	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3573606	0	0
T1	743891	7666	0	0
T2	5272	94	0	0
T3	79996	2044	0	0
T4	40567	0	0	0
T5	227716	1043	0	0
T14	77956	6	0	0
T15	570789	6352	0	0
T16	0	455	0	0
T17	1335	13	0	0
T18	213868	1088	0	0
T19	141945	0	0	0
T20	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1426159	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1426159	0	0
T1	743891	7264	0	0
T2	5272	107	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2320	0	0
T14	77956	30	0	0
T15	570789	3837	0	0
T16	0	3087	0	0
T17	1335	15	0	0
T18	213868	2389	0	0
T19	141945	0	0	0
T20	0	130	0	0
T21	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3811605	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3811605	0	0
T1	743891	7744	0	0
T2	5272	107	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1044	0	0
T14	77956	6	0	0
T15	570789	3458	0	0
T16	0	2163	0	0
T17	1335	15	0	0
T18	213868	1688	0	0
T19	141945	0	0	0
T20	0	158	0	0
T21	0	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1450364	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1450364	0	0
T1	743891	5548	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2373	0	0
T14	77956	21	0	0
T15	570789	3756	0	0
T16	0	585	0	0
T17	1335	23	0	0
T18	213868	3307	0	0
T19	141945	1121	0	0
T20	0	533	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3567411	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3567411	0	0
T1	743891	5830	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1214	0	0
T14	77956	4	0	0
T15	570789	3483	0	0
T16	0	519	0	0
T17	1335	23	0	0
T18	213868	2202	0	0
T19	141945	87832	0	0
T20	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1480367	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1480367	0	0
T1	743891	5577	0	0
T2	5272	114	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2294	0	0
T14	77956	33	0	0
T15	570789	7475	0	0
T16	0	537	0	0
T17	1335	20	0	0
T18	213868	2353	0	0
T19	141945	999	0	0
T20	0	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3614020	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3614020	0	0
T1	743891	5797	0	0
T2	5272	114	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1001	0	0
T14	77956	7	0	0
T15	570789	6473	0	0
T16	0	408	0	0
T17	1335	20	0	0
T18	213868	2239	0	0
T19	141945	88695	0	0
T20	0	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1460204	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1460204	0	0
T1	743891	3718	0	0
T2	5272	110	0	0
T3	79996	2220	0	0
T4	40567	0	0	0
T5	227716	2552	0	0
T14	77956	38	0	0
T15	570789	5304	0	0
T16	0	671	0	0
T17	1335	21	0	0
T18	213868	1385	0	0
T19	141945	0	0	0
T20	0	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2894935	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2894935	0	0
T1	743891	3525	0	0
T2	5272	110	0	0
T3	79996	2339	0	0
T4	40567	0	0	0
T5	227716	1132	0	0
T14	77956	7	0	0
T15	570789	5050	0	0
T16	0	558	0	0
T17	1335	21	0	0
T18	213868	2830	0	0
T19	141945	0	0	0
T20	0	482	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1446523	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1446523	0	0
T1	743891	5931	0	0
T2	5272	97	0	0
T3	79996	2000	0	0
T4	40567	1865	0	0
T5	227716	2128	0	0
T14	77956	36	0	0
T15	570789	5471	0	0
T17	1335	21	0	0
T18	213868	2162	0	0
T19	141945	0	0	0
T20	0	259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2726927	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2726927	0	0
T1	743891	5754	0	0
T2	5272	97	0	0
T3	79996	1930	0	0
T4	40567	992	0	0
T5	227716	1170	0	0
T14	77956	9	0	0
T15	570789	5420	0	0
T17	1335	21	0	0
T18	213868	1602	0	0
T19	141945	0	0	0
T20	0	226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1474026	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1474026	0	0
T1	743891	12253	0	0
T2	5272	102	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1995	0	0
T14	77956	23	0	0
T15	570789	3719	0	0
T16	0	1951	0	0
T17	1335	17	0	0
T18	213868	1547	0	0
T19	141945	0	0	0
T20	0	148	0	0
T21	0	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3110027	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3110027	0	0
T1	743891	12490	0	0
T2	5272	102	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	893	0	0
T14	77956	6	0	0
T15	570789	3212	0	0
T16	0	1582	0	0
T17	1335	17	0	0
T18	213868	2044	0	0
T19	141945	0	0	0
T20	0	143	0	0
T21	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1423630	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1423630	0	0
T1	743891	3657	0	0
T2	5272	121	0	0
T3	79996	2168	0	0
T4	40567	1814	0	0
T5	227716	2194	0	0
T14	77956	26	0	0
T15	570789	6213	0	0
T17	1335	12	0	0
T18	213868	3553	0	0
T19	141945	0	0	0
T20	0	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2728135	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2728135	0	0
T1	743891	3535	0	0
T2	5272	121	0	0
T3	79996	2179	0	0
T4	40567	787	0	0
T5	227716	1033	0	0
T14	77956	6	0	0
T15	570789	5809	0	0
T17	1335	12	0	0
T18	213868	2314	0	0
T19	141945	0	0	0
T20	0	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1462327	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1462327	0	0
T1	743891	4091	0	0
T2	5272	108	0	0
T3	79996	2146	0	0
T4	40567	2155	0	0
T5	227716	2393	0	0
T14	77956	20	0	0
T15	570789	3619	0	0
T17	1335	28	0	0
T18	213868	1599	0	0
T19	141945	0	0	0
T20	0	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3313002	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3313002	0	0
T1	743891	3788	0	0
T2	5272	108	0	0
T3	79996	1943	0	0
T4	40567	988	0	0
T5	227716	1107	0	0
T14	77956	5	0	0
T15	570789	3508	0	0
T17	1335	28	0	0
T18	213868	1010	0	0
T19	141945	0	0	0
T20	0	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1414612	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1414612	0	0
T1	743891	5817	0	0
T2	5272	89	0	0
T3	79996	1941	0	0
T4	40567	0	0	0
T5	227716	2577	0	0
T14	77956	9	0	0
T15	570789	3827	0	0
T17	1335	13	0	0
T18	213868	1373	0	0
T19	141945	1422	0	0
T20	0	165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2955018	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2955018	0	0
T1	743891	5945	0	0
T2	5272	89	0	0
T3	79996	1960	0	0
T4	40567	0	0	0
T5	227716	1272	0	0
T14	77956	2	0	0
T15	570789	3521	0	0
T17	1335	13	0	0
T18	213868	3078	0	0
T19	141945	99668	0	0
T20	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1425926	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1425926	0	0
T1	743891	7629	0	0
T2	5272	85	0	0
T3	79996	2061	0	0
T4	40567	0	0	0
T5	227716	2334	0	0
T14	77956	38	0	0
T15	570789	5448	0	0
T17	1335	20	0	0
T18	213868	1869	0	0
T19	141945	1024	0	0
T20	0	231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3733544	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3733544	0	0
T1	743891	7503	0	0
T2	5272	85	0	0
T3	79996	1975	0	0
T4	40567	0	0	0
T5	227716	1094	0	0
T14	77956	10	0	0
T15	570789	4787	0	0
T17	1335	20	0	0
T18	213868	2596	0	0
T19	141945	81445	0	0
T20	0	195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1449390	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1449390	0	0
T1	743891	9331	0	0
T2	5272	100	0	0
T3	79996	1585	0	0
T4	40567	0	0	0
T5	227716	3212	0	0
T14	77956	36	0	0
T15	570789	5480	0	0
T16	0	2655	0	0
T17	1335	14	0	0
T18	213868	997	0	0
T19	141945	0	0	0
T20	0	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3009064	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3009064	0	0
T1	743891	9072	0	0
T2	5272	100	0	0
T3	79996	2094	0	0
T4	40567	0	0	0
T5	227716	1521	0	0
T14	77956	9	0	0
T15	570789	5390	0	0
T16	0	1900	0	0
T17	1335	14	0	0
T18	213868	1369	0	0
T19	141945	0	0	0
T20	0	163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1463455	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1463455	0	0
T1	743891	11580	0	0
T2	5272	90	0	0
T3	79996	1491	0	0
T4	40567	0	0	0
T5	227716	2264	0	0
T14	77956	30	0	0
T15	570789	3930	0	0
T16	0	3313	0	0
T17	1335	16	0	0
T18	213868	1631	0	0
T19	141945	0	0	0
T20	0	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3262750	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3262750	0	0
T1	743891	11698	0	0
T2	5272	90	0	0
T3	79996	1938	0	0
T4	40567	0	0	0
T5	227716	1140	0	0
T14	77956	6	0	0
T15	570789	3341	0	0
T16	0	3162	0	0
T17	1335	16	0	0
T18	213868	1403	0	0
T19	141945	0	0	0
T20	0	165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1427510	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1427510	0	0
T1	743891	8252	0	0
T2	5272	104	0	0
T3	79996	0	0	0
T4	40567	2105	0	0
T5	227716	3163	0	0
T14	77956	23	0	0
T15	570789	3897	0	0
T16	0	2551	0	0
T17	1335	8	0	0
T18	213868	937	0	0
T19	141945	0	0	0
T20	0	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3663053	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3663053	0	0
T1	743891	8670	0	0
T2	5272	104	0	0
T3	79996	0	0	0
T4	40567	966	0	0
T5	227716	1354	0	0
T14	77956	4	0	0
T15	570789	3393	0	0
T16	0	2150	0	0
T17	1335	8	0	0
T18	213868	493	0	0
T19	141945	0	0	0
T20	0	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1455168	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1455168	0	0
T1	743891	3890	0	0
T2	5272	90	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2003	0	0
T14	77956	21	0	0
T15	570789	6371	0	0
T16	0	522	0	0
T17	1335	11	0	0
T18	213868	1514	0	0
T19	141945	1250	0	0
T20	0	200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2841895	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2841895	0	0
T1	743891	3956	0	0
T2	5272	90	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	991	0	0
T14	77956	4	0	0
T15	570789	5485	0	0
T16	0	480	0	0
T17	1335	11	0	0
T18	213868	1359	0	0
T19	141945	108308	0	0
T20	0	263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1428159	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1428159	0	0
T1	743891	5549	0	0
T2	5272	102	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2259	0	0
T14	77956	13	0	0
T15	570789	6633	0	0
T16	0	722	0	0
T17	1335	19	0	0
T18	213868	2935	0	0
T19	141945	0	0	0
T20	0	199	0	0
T21	0	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3689708	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3689708	0	0
T1	743891	5572	0	0
T2	5272	102	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1181	0	0
T14	77956	3	0	0
T15	570789	6234	0	0
T16	0	563	0	0
T17	1335	19	0	0
T18	213868	2411	0	0
T19	141945	0	0	0
T20	0	185	0	0
T21	0	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1426378	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1426378	0	0
T1	743891	5468	0	0
T2	5272	91	0	0
T3	79996	5055	0	0
T4	40567	0	0	0
T5	227716	2290	0	0
T14	77956	38	0	0
T15	570789	5449	0	0
T16	0	551	0	0
T17	1335	13	0	0
T18	213868	713	0	0
T19	141945	0	0	0
T20	0	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2912798	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2912798	0	0
T1	743891	5243	0	0
T2	5272	91	0	0
T3	79996	6939	0	0
T4	40567	0	0	0
T5	227716	1079	0	0
T14	77956	7	0	0
T15	570789	5159	0	0
T16	0	447	0	0
T17	1335	13	0	0
T18	213868	1910	0	0
T19	141945	0	0	0
T20	0	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1472468	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1472468	0	0
T1	743891	7768	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2268	0	0
T14	77956	13	0	0
T15	570789	5736	0	0
T16	0	663	0	0
T17	1335	16	0	0
T18	213868	1233	0	0
T19	141945	0	0	0
T20	0	187	0	0
T21	0	174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3139607	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3139607	0	0
T1	743891	7824	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1019	0	0
T14	77956	3	0	0
T15	570789	5420	0	0
T16	0	697	0	0
T17	1335	16	0	0
T18	213868	1836	0	0
T19	141945	0	0	0
T20	0	143	0	0
T21	0	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1496680	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1496680	0	0
T1	743891	11569	0	0
T2	5272	92	0	0
T3	79996	0	0	0
T4	40567	2529	0	0
T5	227716	2171	0	0
T14	77956	48	0	0
T15	570789	3825	0	0
T16	0	534	0	0
T17	1335	15	0	0
T18	213868	3096	0	0
T19	141945	0	0	0
T20	0	135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3406167	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3406167	0	0
T1	743891	11133	0	0
T2	5272	92	0	0
T3	79996	0	0	0
T4	40567	1063	0	0
T5	227716	997	0	0
T14	77956	872	0	0
T15	570789	3441	0	0
T16	0	379	0	0
T17	1335	15	0	0
T18	213868	2779	0	0
T19	141945	0	0	0
T20	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1482420	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1482420	0	0
T1	743891	5270	0	0
T2	5272	99	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2498	0	0
T14	77956	31	0	0
T15	570789	9844	0	0
T16	0	545	0	0
T17	1335	24	0	0
T18	213868	1042	0	0
T19	141945	0	0	0
T20	0	661	0	0
T21	0	153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3733741	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3733741	0	0
T1	743891	5969	0	0
T2	5272	99	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1340	0	0
T14	77956	9	0	0
T15	570789	8606	0	0
T16	0	449	0	0
T17	1335	24	0	0
T18	213868	1325	0	0
T19	141945	0	0	0
T20	0	571	0	0
T21	0	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1442591	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1442591	0	0
T1	743891	7317	0	0
T2	5272	83	0	0
T3	79996	1764	0	0
T4	40567	0	0	0
T5	227716	2358	0	0
T14	77956	9	0	0
T15	570789	3688	0	0
T16	0	1892	0	0
T17	1335	13	0	0
T18	213868	3663	0	0
T19	141945	0	0	0
T20	0	330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3539120	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3539120	0	0
T1	743891	7272	0	0
T2	5272	83	0	0
T3	79996	2413	0	0
T4	40567	0	0	0
T5	227716	1290	0	0
T14	77956	4	0	0
T15	570789	3696	0	0
T16	0	1784	0	0
T17	1335	13	0	0
T18	213868	4863	0	0
T19	141945	0	0	0
T20	0	451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1413218	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1413218	0	0
T1	743891	3728	0	0
T2	5272	116	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2482	0	0
T14	77956	6	0	0
T15	570789	7701	0	0
T16	0	4324	0	0
T17	1335	15	0	0
T18	213868	1460	0	0
T19	141945	0	0	0
T20	0	151	0	0
T21	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	2378641	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	2378641	0	0
T1	743891	3640	0	0
T2	5272	116	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1217	0	0
T14	77956	1	0	0
T15	570789	7375	0	0
T16	0	3362	0	0
T17	1335	15	0	0
T18	213868	2822	0	0
T19	141945	0	0	0
T20	0	161	0	0
T21	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1444651	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1444651	0	0
T1	743891	9392	0	0
T2	5272	92	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	2410	0	0
T14	77956	28	0	0
T15	570789	4116	0	0
T16	0	1637	0	0
T17	1335	20	0	0
T18	213868	3080	0	0
T19	141945	0	0	0
T20	0	276	0	0
T21	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3837137	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3837137	0	0
T1	743891	9904	0	0
T2	5272	92	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1047	0	0
T14	77956	8	0	0
T15	570789	3793	0	0
T16	0	1655	0	0
T17	1335	20	0	0
T18	213868	3570	0	0
T19	141945	0	0	0
T20	0	208	0	0
T21	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1418023	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1418023	0	0
T1	743891	3854	0	0
T2	5272	105	0	0
T3	79996	4805	0	0
T4	40567	0	0	0
T5	227716	2365	0	0
T14	77956	38	0	0
T15	570789	9585	0	0
T16	0	510	0	0
T17	1335	15	0	0
T18	213868	2094	0	0
T19	141945	0	0	0
T20	0	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3112722	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3112722	0	0
T1	743891	3988	0	0
T2	5272	105	0	0
T3	79996	6225	0	0
T4	40567	0	0	0
T5	227716	1071	0	0
T14	77956	10	0	0
T15	570789	8577	0	0
T16	0	373	0	0
T17	1335	15	0	0
T18	213868	1184	0	0
T19	141945	0	0	0
T20	0	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1425410	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1425410	0	0
T1	743891	7441	0	0
T2	5272	106	0	0
T3	79996	0	0	0
T4	40567	4142	0	0
T5	227716	2407	0	0
T14	77956	14	0	0
T15	570789	3609	0	0
T16	0	635	0	0
T17	1335	15	0	0
T18	213868	1448	0	0
T19	141945	0	0	0
T20	0	195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3245779	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3245779	0	0
T1	743891	8259	0	0
T2	5272	106	0	0
T3	79996	0	0	0
T4	40567	1828	0	0
T5	227716	1231	0	0
T14	77956	3	0	0
T15	570789	3170	0	0
T16	0	503	0	0
T17	1335	15	0	0
T18	213868	1200	0	0
T19	141945	0	0	0
T20	0	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	1444138	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	1444138	0	0
T1	743891	3921	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	3198	0	0
T14	77956	17	0	0
T15	570789	3871	0	0
T16	0	2387	0	0
T17	1335	16	0	0
T18	213868	3350	0	0
T19	141945	0	0	0
T20	0	260	0	0
T21	0	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306645882	3234471	0	0
DepthKnown_A	306645882	306529460	0	0
RvalidKnown_A	306645882	306529460	0	0
WreadyKnown_A	306645882	306529460	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	3234471	0	0
T1	743891	3834	0	0
T2	5272	101	0	0
T3	79996	0	0	0
T4	40567	0	0	0
T5	227716	1508	0	0
T14	77956	5	0	0
T15	570789	3747	0	0
T16	0	2075	0	0
T17	1335	16	0	0
T18	213868	2340	0	0
T19	141945	0	0	0
T20	0	268	0	0
T21	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306645882	306529460	0	0
T1	743891	742033	0	0
T2	5272	5257	0	0
T3	79996	79952	0	0
T4	40567	40536	0	0
T5	227716	226214	0	0
T14	77956	77908	0	0
T15	570789	570745	0	0
T17	1335	1242	0	0
T18	213868	213855	0	0
T19	141945	141941	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0