Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1625081	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255352

1

T1

249

T2

415

T3

344

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	637971	1			T1	684		T2	1028		T3	788
values[0x0]	607146	1			T1	644		T2	1001		T3	805
values[0x1]	635316	1			T1	670		T2	1021		T3	822

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1259363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

621070

1

T1

624

T2

1028

T3

795

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7342	1			T1	6		T2	116		T3	20
valid_sources[0x01]	7115	1			T1	9		T2	18		T3	2
valid_sources[0x02]	6752	1			T1	13		T2	13		T3	19
valid_sources[0x03]	6827	1			T1	8		T2	20		T3	6
valid_sources[0x04]	8696	1			T1	6		T2	17		T3	6
valid_sources[0x05]	6550	1			T1	8		T3	19		T13	5
valid_sources[0x06]	7299	1			T1	8		T3	4		T13	14
valid_sources[0x07]	7070	1			T1	14		T2	45		T3	21
valid_sources[0x08]	7695	1			T1	7		T2	3		T3	10
valid_sources[0x09]	8014	1			T1	11		T2	2		T3	24
valid_sources[0x0a]	7106	1			T1	7		T3	8		T13	2
valid_sources[0x0b]	7114	1			T1	11		T2	2		T3	1
valid_sources[0x0c]	7392	1			T1	13		T3	9		T13	3
valid_sources[0x0d]	7255	1			T1	3		T2	12		T3	18
valid_sources[0x0e]	6799	1			T1	4		T3	9		T18	11
valid_sources[0x0f]	6589	1			T1	14		T2	45		T3	13
valid_sources[0x10]	9488	1			T1	8		T3	14		T13	14
valid_sources[0x11]	7229	1			T1	8		T3	10		T13	7
valid_sources[0x12]	7171	1			T1	10		T2	9		T3	14
valid_sources[0x13]	7433	1			T1	7		T2	1		T3	11
valid_sources[0x14]	9171	1			T1	12		T3	3		T13	5
valid_sources[0x15]	7116	1			T1	5		T2	21		T3	26
valid_sources[0x16]	7440	1			T1	12		T3	14		T13	14
valid_sources[0x17]	8028	1			T1	7		T3	6		T13	1
valid_sources[0x18]	6875	1			T1	1		T3	11		T13	5
valid_sources[0x19]	6512	1			T1	11		T3	16		T13	8
valid_sources[0x1a]	7297	1			T1	10		T13	6		T18	7
valid_sources[0x1b]	7125	1			T1	6		T2	34		T3	3
valid_sources[0x1c]	7289	1			T1	16		T2	28		T3	4
valid_sources[0x1d]	7862	1			T1	9		T2	6		T3	2
valid_sources[0x1e]	7028	1			T1	6		T2	21		T3	4
valid_sources[0x1f]	7215	1			T1	1		T3	9		T13	7
valid_sources[0x20]	7812	1			T1	9		T2	1		T3	7
valid_sources[0x21]	6947	1			T1	7		T2	4		T3	6
valid_sources[0x22]	6545	1			T1	4		T3	6		T13	3
valid_sources[0x23]	7351	1			T1	5		T2	18		T3	5
valid_sources[0x24]	7152	1			T1	18		T2	1		T3	5
valid_sources[0x25]	7649	1			T1	4		T2	12		T3	5
valid_sources[0x26]	8329	1			T1	7		T3	4		T13	7
valid_sources[0x27]	7746	1			T1	15		T2	35		T3	11
valid_sources[0x28]	8567	1			T1	12		T3	11		T13	12
valid_sources[0x29]	7223	1			T1	9		T2	1		T3	8
valid_sources[0x2a]	6914	1			T1	4		T2	120		T3	4
valid_sources[0x2b]	7380	1			T1	15		T2	5		T13	1
valid_sources[0x2c]	7439	1			T1	2		T2	1		T3	10
valid_sources[0x2d]	7193	1			T1	5		T2	17		T3	11
valid_sources[0x2e]	7534	1			T1	6		T2	1		T13	8
valid_sources[0x2f]	7478	1			T1	5		T3	10		T13	8
valid_sources[0x30]	6934	1			T1	11		T2	5		T3	25
valid_sources[0x31]	6782	1			T1	4		T2	1		T3	14
valid_sources[0x32]	7386	1			T1	5		T3	10		T13	5
valid_sources[0x33]	7372	1			T1	7		T2	13		T3	4
valid_sources[0x34]	7834	1			T1	16		T2	7		T3	8
valid_sources[0x35]	6697	1			T1	7		T2	1		T3	1
valid_sources[0x36]	8351	1			T1	16		T2	24		T3	1
valid_sources[0x37]	7825	1			T1	10		T2	12		T3	5
valid_sources[0x38]	7318	1			T1	7		T13	13		T20	70
valid_sources[0x39]	6704	1			T1	5		T2	6		T13	3
valid_sources[0x3a]	7076	1			T1	12		T3	2		T13	11
valid_sources[0x3b]	8645	1			T1	7		T2	27		T3	17
valid_sources[0x3c]	6881	1			T1	5		T2	19		T3	18
valid_sources[0x3d]	9256	1			T1	11		T2	39		T3	7
valid_sources[0x3e]	6724	1			T1	6		T3	20		T13	4
valid_sources[0x3f]	7631	1			T1	9		T2	1		T3	9
valid_sources[0x40]	6703	1			T1	5		T3	40		T13	3
valid_sources[0x41]	7152	1			T1	6		T3	4		T16	143
valid_sources[0x42]	7903	1			T1	8		T2	103		T3	5
valid_sources[0x43]	7457	1			T1	8		T3	23		T13	6
valid_sources[0x44]	7650	1			T1	16		T2	1		T3	16
valid_sources[0x45]	6294	1			T1	12		T3	17		T13	15
valid_sources[0x46]	7776	1			T1	20		T2	18		T3	6
valid_sources[0x47]	6846	1			T1	4		T3	5		T13	14
valid_sources[0x48]	8308	1			T1	9		T3	3		T13	9
valid_sources[0x49]	7265	1			T1	12		T2	7		T3	7
valid_sources[0x4a]	7016	1			T1	1		T2	9		T3	9
valid_sources[0x4b]	7841	1			T1	2		T2	2		T3	8
valid_sources[0x4c]	6683	1			T1	6		T2	13		T3	9
valid_sources[0x4d]	8257	1			T1	6		T3	17		T13	1
valid_sources[0x4e]	7352	1			T1	19		T2	13		T3	11
valid_sources[0x4f]	7898	1			T1	6		T2	2		T13	14
valid_sources[0x50]	7805	1			T1	8		T3	8		T13	9
valid_sources[0x51]	6654	1			T1	5		T3	5		T13	6
valid_sources[0x52]	7317	1			T1	5		T2	8		T3	16
valid_sources[0x53]	7241	1			T1	6		T2	10		T13	5
valid_sources[0x54]	6797	1			T1	11		T2	1		T3	6
valid_sources[0x55]	7005	1			T1	8		T2	29		T3	4
valid_sources[0x56]	7098	1			T1	8		T3	4		T13	3
valid_sources[0x57]	6455	1			T1	19		T3	3		T13	7
valid_sources[0x58]	6638	1			T1	2		T3	5		T13	1
valid_sources[0x59]	7922	1			T1	9		T3	13		T13	13
valid_sources[0x5a]	6755	1			T1	10		T2	1		T3	3
valid_sources[0x5b]	8076	1			T1	5		T3	9		T13	6
valid_sources[0x5c]	8674	1			T1	6		T2	3		T3	3
valid_sources[0x5d]	7669	1			T1	5		T2	11		T3	5
valid_sources[0x5e]	6559	1			T1	12		T3	30		T13	4
valid_sources[0x5f]	7030	1			T1	6		T2	36		T13	6
valid_sources[0x60]	8012	1			T1	5		T2	8		T3	13
valid_sources[0x61]	6859	1			T1	4		T3	1		T13	14
valid_sources[0x62]	6598	1			T1	8		T2	2		T3	10
valid_sources[0x63]	6866	1			T1	8		T3	14		T13	3
valid_sources[0x64]	6953	1			T1	13		T2	1		T3	6
valid_sources[0x65]	8047	1			T1	6		T2	1		T3	12
valid_sources[0x66]	7694	1			T1	9		T2	1		T3	10
valid_sources[0x67]	7930	1			T1	3		T3	14		T13	7
valid_sources[0x68]	7970	1			T1	6		T2	99		T3	4
valid_sources[0x69]	9209	1			T1	12		T2	3		T3	7
valid_sources[0x6a]	7549	1			T1	6		T2	18		T3	11
valid_sources[0x6b]	6561	1			T1	5		T2	1		T3	8
valid_sources[0x6c]	7326	1			T1	9		T2	1		T3	14
valid_sources[0x6d]	7772	1			T1	7		T2	30		T3	13
valid_sources[0x6e]	7513	1			T1	5		T3	8		T13	6
valid_sources[0x6f]	6978	1			T1	1		T2	4		T3	5
valid_sources[0x70]	7135	1			T1	9		T3	13		T13	2
valid_sources[0x71]	8154	1			T1	6		T2	3		T3	17
valid_sources[0x72]	7203	1			T1	15		T2	9		T3	5
valid_sources[0x73]	7107	1			T1	7		T3	6		T13	3
valid_sources[0x74]	7151	1			T1	13		T2	4		T3	15
valid_sources[0x75]	7368	1			T1	8		T2	1		T3	10
valid_sources[0x76]	7597	1			T1	9		T2	4		T3	19
valid_sources[0x77]	7291	1			T1	6		T13	5		T18	17
valid_sources[0x78]	8208	1			T1	5		T3	20		T13	9
valid_sources[0x79]	7352	1			T1	8		T3	19		T13	14
valid_sources[0x7a]	7403	1			T1	13		T2	12		T3	5
valid_sources[0x7b]	6699	1			T1	5		T3	13		T13	5
valid_sources[0x7c]	7001	1			T1	7		T2	3		T3	15
valid_sources[0x7d]	7270	1			T1	7		T2	16		T3	8
valid_sources[0x7e]	6587	1			T1	6		T2	27		T3	18
valid_sources[0x7f]	7009	1			T1	7		T3	2		T13	7
valid_sources[0x80]	7274	1			T1	9		T2	12		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27028

1

T1

28

T2

37

T3

28

values[0x0]

all_enables

biggest_size

201188

1

T1

202

T2

336

T3

280

values[0x1]

all_enables

biggest_size

27136

1

T1

19

T2

42

T3

36