Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	324036911	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	324036911	0	0
T1	13576472	1950846	0	0
T2	4585616	97117	0	0
T3	2751896	54573	0	0
T13	208320	6413	0	0
T14	93688	5776	0	0
T15	80024	1954	0	0
T16	101752	3274	0	0
T17	42336	858	0	0
T18	273224	8908	0	0
T19	3045672	62620	0	0
T20	0	163415	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13576472	13576080	0	0
T2	4585616	4529448	0	0
T3	2751896	2748256	0	0
T13	208320	204736	0	0
T14	93688	91616	0	0
T15	80024	77168	0	0
T16	101752	98952	0	0
T17	42336	38976	0	0
T18	273224	270144	0	0
T19	3045672	3043600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13576472	13576080	0	0
T2	4585616	4529448	0	0
T3	2751896	2748256	0	0
T13	208320	204736	0	0
T14	93688	91616	0	0
T15	80024	77168	0	0
T16	101752	98952	0	0
T17	42336	38976	0	0
T18	273224	270144	0	0
T19	3045672	3043600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13576472	13576080	0	0
T2	4585616	4529448	0	0
T3	2751896	2748256	0	0
T13	208320	204736	0	0
T14	93688	91616	0	0
T15	80024	77168	0	0
T16	101752	98952	0	0
T17	42336	38976	0	0
T18	273224	270144	0	0
T19	3045672	3043600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	113520304	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	113520304	0	0
T1	242437	139331	0	0
T2	81886	38011	0	0
T3	49141	22999	0	0
T13	3720	3158	0	0
T14	1673	1444	0	0
T15	1429	489	0	0
T16	1817	1270	0	0
T17	756	335	0	0
T18	4879	2232	0	0
T19	54387	28646	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	85922019	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	85922019	0	0
T1	242437	578733	0	0
T2	81886	25871	0	0
T3	49141	14818	0	0
T13	3720	1617	0	0
T14	1673	1444	0	0
T15	1429	489	0	0
T16	1817	668	0	0
T17	756	175	0	0
T18	4879	2232	0	0
T19	54387	7677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1554546	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1554546	0	0
T1	242437	26872	0	0
T2	81886	600	0	0
T3	49141	250	0	0
T13	3720	19	0	0
T14	1673	0	0	0
T15	1429	14	0	0
T16	1817	24	0	0
T17	756	7	0	0
T18	4879	82	0	0
T19	54387	709	0	0
T20	0	4253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3870696	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3870696	0	0
T1	242437	22234	0	0
T2	81886	629	0	0
T3	49141	224	0	0
T13	3720	19	0	0
T14	1673	0	0	0
T15	1429	14	0	0
T16	1817	24	0	0
T17	756	7	0	0
T18	4879	82	0	0
T19	54387	250	0	0
T20	0	3373	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1460484	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1460484	0	0
T1	242437	24820	0	0
T2	81886	660	0	0
T3	49141	147	0	0
T13	3720	24	0	0
T14	1673	0	0	0
T15	1429	14	0	0
T16	1817	27	0	0
T17	756	6	0	0
T18	4879	80	0	0
T19	54387	743	0	0
T20	0	4435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2351149	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2351149	0	0
T1	242437	22015	0	0
T2	81886	633	0	0
T3	49141	145	0	0
T13	3720	24	0	0
T14	1673	0	0	0
T15	1429	14	0	0
T16	1817	27	0	0
T17	756	6	0	0
T18	4879	80	0	0
T19	54387	365	0	0
T20	0	4106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1492696	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1492696	0	0
T1	242437	25883	0	0
T2	81886	515	0	0
T3	49141	311	0	0
T13	3720	32	0	0
T14	1673	246	0	0
T15	1429	15	0	0
T16	1817	21	0	0
T17	756	3	0	0
T18	4879	72	0	0
T19	54387	619	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3354680	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3354680	0	0
T1	242437	23523	0	0
T2	81886	531	0	0
T3	49141	309	0	0
T13	3720	32	0	0
T14	1673	246	0	0
T15	1429	15	0	0
T16	1817	21	0	0
T17	756	3	0	0
T18	4879	72	0	0
T19	54387	297	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1468286	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1468286	0	0
T1	242437	18751	0	0
T2	81886	541	0	0
T3	49141	377	0	0
T13	3720	26	0	0
T14	1673	211	0	0
T15	1429	17	0	0
T16	1817	16	0	0
T17	756	11	0	0
T18	4879	92	0	0
T19	54387	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3337321	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3337321	0	0
T1	242437	22915	0	0
T2	81886	522	0	0
T3	49141	250	0	0
T13	3720	26	0	0
T14	1673	211	0	0
T15	1429	17	0	0
T16	1817	16	0	0
T17	756	11	0	0
T18	4879	92	0	0
T19	54387	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1447761	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1447761	0	0
T1	242437	24031	0	0
T2	81886	591	0	0
T3	49141	272	0	0
T13	3720	41	0	0
T14	1673	0	0	0
T15	1429	19	0	0
T16	1817	21	0	0
T17	756	10	0	0
T18	4879	77	0	0
T19	54387	704	0	0
T20	0	2199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3154552	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3154552	0	0
T1	242437	19873	0	0
T2	81886	698	0	0
T3	49141	245	0	0
T13	3720	41	0	0
T14	1673	0	0	0
T15	1429	19	0	0
T16	1817	21	0	0
T17	756	10	0	0
T18	4879	77	0	0
T19	54387	328	0	0
T20	0	1882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1443809	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1443809	0	0
T1	242437	25481	0	0
T2	81886	496	0	0
T3	49141	316	0	0
T13	3720	46	0	0
T14	1673	0	0	0
T15	1429	19	0	0
T16	1817	21	0	0
T17	756	8	0	0
T18	4879	71	0	0
T19	54387	787	0	0
T20	0	5409	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3180852	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3180852	0	0
T1	242437	24716	0	0
T2	81886	432	0	0
T3	49141	277	0	0
T13	3720	46	0	0
T14	1673	0	0	0
T15	1429	19	0	0
T16	1817	21	0	0
T17	756	8	0	0
T18	4879	71	0	0
T19	54387	288	0	0
T20	0	5496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1450330	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1450330	0	0
T1	242437	23929	0	0
T2	81886	524	0	0
T3	49141	369	0	0
T13	3720	28	0	0
T14	1673	0	0	0
T15	1429	16	0	0
T16	1817	21	0	0
T17	756	4	0	0
T18	4879	82	0	0
T19	54387	593	0	0
T20	0	4560	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2925560	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2925560	0	0
T1	242437	21204	0	0
T2	81886	537	0	0
T3	49141	313	0	0
T13	3720	28	0	0
T14	1673	0	0	0
T15	1429	16	0	0
T16	1817	21	0	0
T17	756	4	0	0
T18	4879	82	0	0
T19	54387	297	0	0
T20	0	3558	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1459981	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1459981	0	0
T1	242437	19201	0	0
T2	81886	769	0	0
T3	49141	281	0	0
T13	3720	36	0	0
T14	1673	0	0	0
T15	1429	15	0	0
T16	1817	22	0	0
T17	756	11	0	0
T18	4879	81	0	0
T19	54387	692	0	0
T20	0	3246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2735418	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2735418	0	0
T1	242437	15902	0	0
T2	81886	693	0	0
T3	49141	278	0	0
T13	3720	36	0	0
T14	1673	0	0	0
T15	1429	15	0	0
T16	1817	22	0	0
T17	756	11	0	0
T18	4879	81	0	0
T19	54387	272	0	0
T20	0	3300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1474948	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1474948	0	0
T1	242437	30651	0	0
T2	81886	674	0	0
T3	49141	378	0	0
T13	3720	31	0	0
T14	1673	0	0	0
T15	1429	15	0	0
T16	1817	34	0	0
T17	756	6	0	0
T18	4879	73	0	0
T19	54387	666	0	0
T20	0	4077	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2972832	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2972832	0	0
T1	242437	27229	0	0
T2	81886	588	0	0
T3	49141	353	0	0
T13	3720	31	0	0
T14	1673	0	0	0
T15	1429	15	0	0
T16	1817	34	0	0
T17	756	6	0	0
T18	4879	73	0	0
T19	54387	252	0	0
T20	0	4027	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1389655	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1389655	0	0
T1	242437	20426	0	0
T2	81886	1012	0	0
T3	49141	363	0	0
T13	3720	29	0	0
T14	1673	0	0	0
T15	1429	13	0	0
T16	1817	19	0	0
T17	756	13	0	0
T18	4879	87	0	0
T19	54387	668	0	0
T20	0	2316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2945047	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2945047	0	0
T1	242437	19056	0	0
T2	81886	908	0	0
T3	49141	397	0	0
T13	3720	29	0	0
T14	1673	0	0	0
T15	1429	13	0	0
T16	1817	19	0	0
T17	756	13	0	0
T18	4879	87	0	0
T19	54387	277	0	0
T20	0	1877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1447686	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1447686	0	0
T1	242437	27562	0	0
T2	81886	526	0	0
T3	49141	331	0	0
T13	3720	35	0	0
T14	1673	0	0	0
T15	1429	16	0	0
T16	1817	19	0	0
T17	756	7	0	0
T18	4879	65	0	0
T19	54387	707	0	0
T20	0	5767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3372643	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3372643	0	0
T1	242437	22253	0	0
T2	81886	520	0	0
T3	49141	222	0	0
T13	3720	35	0	0
T14	1673	0	0	0
T15	1429	16	0	0
T16	1817	19	0	0
T17	756	7	0	0
T18	4879	65	0	0
T19	54387	287	0	0
T20	0	5930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1446693	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1446693	0	0
T1	242437	20473	0	0
T2	81886	545	0	0
T3	49141	317	0	0
T13	3720	32	0	0
T14	1673	221	0	0
T15	1429	17	0	0
T16	1817	36	0	0
T17	756	7	0	0
T18	4879	86	0	0
T19	54387	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2996311	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2996311	0	0
T1	242437	18824	0	0
T2	81886	582	0	0
T3	49141	402	0	0
T13	3720	32	0	0
T14	1673	221	0	0
T15	1429	17	0	0
T16	1817	36	0	0
T17	756	7	0	0
T18	4879	86	0	0
T19	54387	263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1419535	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1419535	0	0
T1	242437	22986	0	0
T2	81886	698	0	0
T3	49141	313	0	0
T13	3720	22	0	0
T14	1673	0	0	0
T15	1429	22	0	0
T16	1817	18	0	0
T17	756	4	0	0
T18	4879	90	0	0
T19	54387	802	0	0
T20	0	2294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2942113	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2942113	0	0
T1	242437	22879	0	0
T2	81886	755	0	0
T3	49141	315	0	0
T13	3720	22	0	0
T14	1673	0	0	0
T15	1429	22	0	0
T16	1817	18	0	0
T17	756	4	0	0
T18	4879	90	0	0
T19	54387	253	0	0
T20	0	1994	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1497991	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1497991	0	0
T1	242437	20227	0	0
T2	81886	589	0	0
T3	49141	311	0	0
T13	3720	39	0	0
T14	1673	0	0	0
T15	1429	20	0	0
T16	1817	30	0	0
T17	756	3	0	0
T18	4879	69	0	0
T19	54387	678	0	0
T20	0	5392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3213516	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3213516	0	0
T1	242437	16233	0	0
T2	81886	569	0	0
T3	49141	281	0	0
T13	3720	39	0	0
T14	1673	0	0	0
T15	1429	20	0	0
T16	1817	30	0	0
T17	756	3	0	0
T18	4879	69	0	0
T19	54387	255	0	0
T20	0	5167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1424855	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1424855	0	0
T1	242437	27265	0	0
T2	81886	701	0	0
T3	49141	328	0	0
T13	3720	21	0	0
T14	1673	0	0	0
T15	1429	17	0	0
T16	1817	32	0	0
T17	756	6	0	0
T18	4879	94	0	0
T19	54387	627	0	0
T20	0	5645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2833283	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2833283	0	0
T1	242437	23802	0	0
T2	81886	783	0	0
T3	49141	288	0	0
T13	3720	21	0	0
T14	1673	0	0	0
T15	1429	17	0	0
T16	1817	32	0	0
T17	756	6	0	0
T18	4879	94	0	0
T19	54387	282	0	0
T20	0	5185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1500830	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1500830	0	0
T1	242437	23651	0	0
T2	81886	524	0	0
T3	49141	437	0	0
T13	3720	21	0	0
T14	1673	275	0	0
T15	1429	25	0	0
T16	1817	25	0	0
T17	756	4	0	0
T18	4879	82	0	0
T19	54387	680	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3243401	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3243401	0	0
T1	242437	19165	0	0
T2	81886	673	0	0
T3	49141	458	0	0
T13	3720	21	0	0
T14	1673	275	0	0
T15	1429	25	0	0
T16	1817	25	0	0
T17	756	4	0	0
T18	4879	82	0	0
T19	54387	306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1473009	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1473009	0	0
T1	242437	27749	0	0
T2	81886	536	0	0
T3	49141	305	0	0
T13	3720	25	0	0
T14	1673	0	0	0
T15	1429	25	0	0
T16	1817	22	0	0
T17	756	6	0	0
T18	4879	76	0	0
T19	54387	840	0	0
T20	0	4283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3087737	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3087737	0	0
T1	242437	23427	0	0
T2	81886	439	0	0
T3	49141	239	0	0
T13	3720	25	0	0
T14	1673	0	0	0
T15	1429	25	0	0
T16	1817	22	0	0
T17	756	6	0	0
T18	4879	76	0	0
T19	54387	312	0	0
T20	0	3768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1492698	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1492698	0	0
T1	242437	21832	0	0
T2	81886	645	0	0
T3	49141	327	0	0
T13	3720	31	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	37	0	0
T17	756	2	0	0
T18	4879	91	0	0
T19	54387	575	0	0
T20	0	4410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2714751	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2714751	0	0
T1	242437	21106	0	0
T2	81886	514	0	0
T3	49141	316	0	0
T13	3720	31	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	37	0	0
T17	756	2	0	0
T18	4879	91	0	0
T19	54387	186	0	0
T20	0	3656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1494383	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1494383	0	0
T1	242437	20303	0	0
T2	81886	543	0	0
T3	49141	249	0	0
T13	3720	31	0	0
T14	1673	210	0	0
T15	1429	18	0	0
T16	1817	27	0	0
T17	756	5	0	0
T18	4879	83	0	0
T19	54387	663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3144917	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3144917	0	0
T1	242437	17373	0	0
T2	81886	459	0	0
T3	49141	293	0	0
T13	3720	31	0	0
T14	1673	210	0	0
T15	1429	18	0	0
T16	1817	27	0	0
T17	756	5	0	0
T18	4879	83	0	0
T19	54387	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1478941	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1478941	0	0
T1	242437	21617	0	0
T2	81886	444	0	0
T3	49141	372	0	0
T13	3720	38	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	27	0	0
T17	756	7	0	0
T18	4879	65	0	0
T19	54387	713	0	0
T20	0	2484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3408617	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3408617	0	0
T1	242437	19240	0	0
T2	81886	452	0	0
T3	49141	314	0	0
T13	3720	38	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	27	0	0
T17	756	7	0	0
T18	4879	65	0	0
T19	54387	310	0	0
T20	0	2243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1442098	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1442098	0	0
T1	242437	23742	0	0
T2	81886	559	0	0
T3	49141	301	0	0
T13	3720	24	0	0
T14	1673	0	0	0
T15	1429	13	0	0
T16	1817	21	0	0
T17	756	8	0	0
T18	4879	101	0	0
T19	54387	652	0	0
T20	0	5942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3286659	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3286659	0	0
T1	242437	21763	0	0
T2	81886	550	0	0
T3	49141	342	0	0
T13	3720	24	0	0
T14	1673	0	0	0
T15	1429	13	0	0
T16	1817	21	0	0
T17	756	8	0	0
T18	4879	101	0	0
T19	54387	264	0	0
T20	0	5070	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1477390	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1477390	0	0
T1	242437	22841	0	0
T2	81886	751	0	0
T3	49141	440	0	0
T13	3720	30	0	0
T14	1673	0	0	0
T15	1429	22	0	0
T16	1817	23	0	0
T17	756	5	0	0
T18	4879	95	0	0
T19	54387	509	0	0
T20	0	4001	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	2932076	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	2932076	0	0
T1	242437	20452	0	0
T2	81886	626	0	0
T3	49141	409	0	0
T13	3720	30	0	0
T14	1673	0	0	0
T15	1429	22	0	0
T16	1817	23	0	0
T17	756	5	0	0
T18	4879	95	0	0
T19	54387	239	0	0
T20	0	3014	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1514191	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1514191	0	0
T1	242437	20961	0	0
T2	81886	512	0	0
T3	49141	281	0	0
T13	3720	28	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	29	0	0
T17	756	5	0	0
T18	4879	80	0	0
T19	54387	796	0	0
T20	0	2057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3715022	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3715022	0	0
T1	242437	16658	0	0
T2	81886	601	0	0
T3	49141	296	0	0
T13	3720	28	0	0
T14	1673	0	0	0
T15	1429	18	0	0
T16	1817	29	0	0
T17	756	5	0	0
T18	4879	80	0	0
T19	54387	288	0	0
T20	0	2016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1420945	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1420945	0	0
T1	242437	31045	0	0
T2	81886	995	0	0
T3	49141	377	0	0
T13	3720	29	0	0
T14	1673	0	0	0
T15	1429	26	0	0
T16	1817	27	0	0
T17	756	3	0	0
T18	4879	79	0	0
T19	54387	632	0	0
T20	0	4571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3104637	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3104637	0	0
T1	242437	30197	0	0
T2	81886	988	0	0
T3	49141	308	0	0
T13	3720	29	0	0
T14	1673	0	0	0
T15	1429	26	0	0
T16	1817	27	0	0
T17	756	3	0	0
T18	4879	79	0	0
T19	54387	342	0	0
T20	0	4233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1529690	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1529690	0	0
T1	242437	26027	0	0
T2	81886	448	0	0
T3	49141	370	0	0
T13	3720	35	0	0
T14	1673	281	0	0
T15	1429	24	0	0
T16	1817	27	0	0
T17	756	9	0	0
T18	4879	92	0	0
T19	54387	659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3458786	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3458786	0	0
T1	242437	19909	0	0
T2	81886	528	0	0
T3	49141	337	0	0
T13	3720	35	0	0
T14	1673	281	0	0
T15	1429	24	0	0
T16	1817	27	0	0
T17	756	9	0	0
T18	4879	92	0	0
T19	54387	278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1490963	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1490963	0	0
T1	242437	31386	0	0
T2	81886	725	0	0
T3	49141	245	0	0
T13	3720	26	0	0
T14	1673	0	0	0
T15	1429	23	0	0
T16	1817	21	0	0
T17	756	4	0	0
T18	4879	88	0	0
T19	54387	650	0	0
T20	0	6329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3387084	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3387084	0	0
T1	242437	23438	0	0
T2	81886	706	0	0
T3	49141	175	0	0
T13	3720	26	0	0
T14	1673	0	0	0
T15	1429	23	0	0
T16	1817	21	0	0
T17	756	4	0	0
T18	4879	88	0	0
T19	54387	320	0	0
T20	0	5194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	1467860	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	1467860	0	0
T1	242437	24337	0	0
T2	81886	583	0	0
T3	49141	308	0	0
T13	3720	40	0	0
T14	1673	0	0	0
T15	1429	9	0	0
T16	1817	21	0	0
T17	756	10	0	0
T18	4879	89	0	0
T19	54387	721	0	0
T20	0	2487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301797620	3262674	0	0
DepthKnown_A	301797620	301668467	0	0
RvalidKnown_A	301797620	301668467	0	0
WreadyKnown_A	301797620	301668467	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	3262674	0	0
T1	242437	23347	0	0
T2	81886	613	0	0
T3	49141	294	0	0
T13	3720	40	0	0
T14	1673	0	0	0
T15	1429	9	0	0
T16	1817	21	0	0
T17	756	10	0	0
T18	4879	89	0	0
T19	54387	315	0	0
T20	0	2169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301797620	301668467	0	0
T1	242437	242430	0	0
T2	81886	80883	0	0
T3	49141	49076	0	0
T13	3720	3656	0	0
T14	1673	1636	0	0
T15	1429	1378	0	0
T16	1817	1767	0	0
T17	756	696	0	0
T18	4879	4824	0	0
T19	54387	54350	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0