Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1661875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261144

1

T1

99

T2

12

T3

3628

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650045	1			T1	218		T2	38		T3	9051
values[0x0]	621743	1			T1	260		T2	7		T3	8908
values[0x1]	651231	1			T1	259		T2	30		T3	9134

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1288474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634545

1

T1

236

T2

29

T3

8884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7460	1			T3	76		T4	11		T14	2
valid_sources[0x01]	7289	1			T3	172		T4	12		T15	114
valid_sources[0x02]	7049	1			T2	1		T3	91		T4	11
valid_sources[0x03]	8077	1			T3	89		T4	10		T14	2
valid_sources[0x04]	6932	1			T3	94		T4	11		T5	3
valid_sources[0x05]	8510	1			T2	1		T3	141		T4	11
valid_sources[0x06]	7491	1			T1	7		T3	122		T4	10
valid_sources[0x07]	6945	1			T3	64		T4	10		T15	77
valid_sources[0x08]	6974	1			T3	106		T4	9		T15	94
valid_sources[0x09]	7113	1			T1	8		T3	118		T4	10
valid_sources[0x0a]	7297	1			T3	120		T4	10		T5	1
valid_sources[0x0b]	7140	1			T3	105		T4	13		T14	1
valid_sources[0x0c]	7429	1			T3	86		T4	11		T15	63
valid_sources[0x0d]	7387	1			T1	3		T3	116		T4	11
valid_sources[0x0e]	7489	1			T3	160		T4	10		T14	1
valid_sources[0x0f]	8234	1			T1	10		T3	131		T4	10
valid_sources[0x10]	7231	1			T3	98		T4	11		T5	1
valid_sources[0x11]	9165	1			T1	7		T3	89		T4	9
valid_sources[0x12]	7203	1			T3	76		T4	10		T14	1
valid_sources[0x13]	7285	1			T3	63		T4	10		T14	1
valid_sources[0x14]	7676	1			T3	106		T4	11		T14	3
valid_sources[0x15]	7477	1			T3	110		T4	10		T14	1
valid_sources[0x16]	8241	1			T1	9		T3	95		T4	11
valid_sources[0x17]	7916	1			T1	8		T2	1		T3	123
valid_sources[0x18]	7837	1			T1	1		T3	90		T4	10
valid_sources[0x19]	6595	1			T1	4		T2	1		T3	78
valid_sources[0x1a]	7444	1			T3	101		T4	9		T5	2
valid_sources[0x1b]	8503	1			T3	92		T4	10		T14	1
valid_sources[0x1c]	7513	1			T3	48		T4	11		T14	2
valid_sources[0x1d]	7388	1			T1	1		T3	87		T4	10
valid_sources[0x1e]	7206	1			T1	2		T3	97		T4	9
valid_sources[0x1f]	7383	1			T1	1		T3	93		T4	11
valid_sources[0x20]	7566	1			T2	3		T3	96		T4	10
valid_sources[0x21]	6977	1			T3	117		T4	10		T15	41
valid_sources[0x22]	6547	1			T1	3		T2	1		T3	72
valid_sources[0x23]	7446	1			T3	49		T4	12		T5	5
valid_sources[0x24]	6986	1			T3	79		T4	11		T15	47
valid_sources[0x25]	7258	1			T3	93		T4	12		T15	70
valid_sources[0x26]	7963	1			T3	134		T4	10		T15	114
valid_sources[0x27]	7959	1			T3	147		T4	12		T14	1
valid_sources[0x28]	7350	1			T2	2		T3	144		T4	11
valid_sources[0x29]	7277	1			T3	112		T4	11		T15	106
valid_sources[0x2a]	7732	1			T1	2		T3	96		T4	11
valid_sources[0x2b]	7428	1			T1	5		T3	123		T4	11
valid_sources[0x2c]	9611	1			T3	119		T4	10		T5	1
valid_sources[0x2d]	6631	1			T3	97		T4	12		T15	86
valid_sources[0x2e]	7595	1			T2	1		T3	95		T4	10
valid_sources[0x2f]	6571	1			T1	2		T3	69		T4	10
valid_sources[0x30]	7050	1			T2	1		T3	92		T4	10
valid_sources[0x31]	7925	1			T1	4		T3	102		T4	9
valid_sources[0x32]	8223	1			T2	1		T3	121		T4	11
valid_sources[0x33]	7493	1			T1	8		T3	143		T4	9
valid_sources[0x34]	7372	1			T2	1		T3	137		T4	12
valid_sources[0x35]	7149	1			T3	124		T4	12		T15	94
valid_sources[0x36]	7963	1			T1	5		T3	138		T4	9
valid_sources[0x37]	7364	1			T1	5		T3	64		T4	11
valid_sources[0x38]	7852	1			T3	83		T4	10		T14	2
valid_sources[0x39]	7012	1			T3	85		T4	9		T14	2
valid_sources[0x3a]	8710	1			T3	108		T4	11		T15	85
valid_sources[0x3b]	7036	1			T1	2		T3	129		T4	12
valid_sources[0x3c]	7865	1			T2	1		T3	67		T4	11
valid_sources[0x3d]	6930	1			T3	83		T4	12		T14	2
valid_sources[0x3e]	9200	1			T1	3		T3	72		T4	11
valid_sources[0x3f]	7543	1			T3	76		T4	11		T15	89
valid_sources[0x40]	7612	1			T1	3		T3	108		T4	9
valid_sources[0x41]	6932	1			T1	8		T3	73		T4	10
valid_sources[0x42]	6987	1			T1	4		T2	1		T3	88
valid_sources[0x43]	6946	1			T1	1		T3	69		T4	11
valid_sources[0x44]	7042	1			T1	7		T3	91		T4	12
valid_sources[0x45]	7005	1			T1	1		T3	174		T4	10
valid_sources[0x46]	8199	1			T3	100		T4	10		T15	64
valid_sources[0x47]	7419	1			T2	2		T3	134		T4	11
valid_sources[0x48]	7563	1			T1	3		T3	122		T4	12
valid_sources[0x49]	6666	1			T1	1		T3	156		T4	9
valid_sources[0x4a]	8708	1			T1	31		T2	1		T3	122
valid_sources[0x4b]	7368	1			T3	122		T4	9		T15	55
valid_sources[0x4c]	6980	1			T1	8		T3	122		T4	12
valid_sources[0x4d]	8003	1			T1	6		T2	1		T3	126
valid_sources[0x4e]	7918	1			T1	2		T3	209		T4	11
valid_sources[0x4f]	7996	1			T1	19		T3	78		T4	10
valid_sources[0x50]	7625	1			T3	95		T4	10		T15	115
valid_sources[0x51]	8777	1			T3	130		T4	11		T15	100
valid_sources[0x52]	7613	1			T3	117		T4	10		T14	2
valid_sources[0x53]	7218	1			T1	10		T3	65		T4	12
valid_sources[0x54]	6668	1			T3	139		T4	11		T5	1
valid_sources[0x55]	7547	1			T1	2		T2	1		T3	89
valid_sources[0x56]	7259	1			T1	1		T3	110		T4	10
valid_sources[0x57]	7083	1			T1	13		T3	82		T4	8
valid_sources[0x58]	7735	1			T2	2		T3	120		T4	11
valid_sources[0x59]	8244	1			T2	1		T3	64		T4	10
valid_sources[0x5a]	6970	1			T1	2		T3	80		T4	9
valid_sources[0x5b]	8771	1			T3	119		T4	11		T14	1
valid_sources[0x5c]	7757	1			T2	1		T3	84		T4	11
valid_sources[0x5d]	7039	1			T1	4		T3	118		T4	11
valid_sources[0x5e]	6680	1			T3	103		T4	10		T14	2
valid_sources[0x5f]	7389	1			T1	3		T3	141		T4	11
valid_sources[0x60]	7712	1			T2	1		T3	108		T4	9
valid_sources[0x61]	7814	1			T3	96		T4	11		T14	1
valid_sources[0x62]	8531	1			T2	1		T3	134		T4	10
valid_sources[0x63]	7635	1			T1	10		T3	76		T4	10
valid_sources[0x64]	7463	1			T3	106		T4	12		T15	66
valid_sources[0x65]	7456	1			T1	6		T3	145		T4	9
valid_sources[0x66]	7443	1			T1	2		T3	105		T4	11
valid_sources[0x67]	8030	1			T2	1		T3	126		T4	10
valid_sources[0x68]	8015	1			T3	119		T4	9		T14	1
valid_sources[0x69]	7134	1			T1	18		T2	1		T3	94
valid_sources[0x6a]	7445	1			T3	62		T4	11		T5	3
valid_sources[0x6b]	7801	1			T1	3		T3	116		T4	12
valid_sources[0x6c]	6944	1			T3	109		T4	10		T14	1
valid_sources[0x6d]	7709	1			T1	11		T3	79		T4	13
valid_sources[0x6e]	7666	1			T3	140		T4	10		T5	4
valid_sources[0x6f]	8715	1			T3	161		T4	11		T15	90
valid_sources[0x70]	6694	1			T1	1		T2	2		T3	105
valid_sources[0x71]	6725	1			T1	3		T3	96		T4	13
valid_sources[0x72]	7645	1			T3	104		T4	9		T15	121
valid_sources[0x73]	6931	1			T3	84		T4	11		T15	46
valid_sources[0x74]	7317	1			T1	2		T3	90		T4	11
valid_sources[0x75]	7124	1			T3	121		T4	11		T14	1
valid_sources[0x76]	7265	1			T2	1		T3	146		T4	10
valid_sources[0x77]	7569	1			T3	163		T4	12		T5	1
valid_sources[0x78]	7244	1			T2	1		T3	122		T4	9
valid_sources[0x79]	7646	1			T1	3		T3	124		T4	9
valid_sources[0x7a]	7596	1			T1	4		T3	96		T4	10
valid_sources[0x7b]	7333	1			T2	1		T3	171		T4	12
valid_sources[0x7c]	6997	1			T1	4		T3	98		T4	11
valid_sources[0x7d]	7942	1			T1	3		T3	132		T4	9
valid_sources[0x7e]	8414	1			T1	2		T3	118		T4	11
valid_sources[0x7f]	7001	1			T1	6		T2	1		T3	83
valid_sources[0x80]	8354	1			T3	150		T4	13		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27512

1

T1

8

T2

4

T3

403

values[0x0]

all_enables

biggest_size

206158

1

T1

81

T2

3

T3

2873

values[0x1]

all_enables

biggest_size

27474

1

T1

10

T2

5

T3

352