Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	347276366	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347276366	0	0
T1	99432	14566	0	0
T2	202888	6856	0	0
T3	2928016	123038	0	0
T4	14579152	2010786	0	0
T5	11235504	262200	0	0
T14	321608	5299	0	0
T15	2333576	99496	0	0
T16	8281840	179899	0	0
T17	198912	8851	0	0
T18	172648	10612	0	0
T19	3809664	27179	0	0
T20	0	1203	0	0
T21	0	7860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	696024	693336	0	0
T2	202888	201712	0	0
T3	2928016	2862608	0	0
T4	14579152	14578984	0	0
T5	11235504	11233936	0	0
T14	321608	308168	0	0
T15	2333576	2317112	0	0
T16	8281840	8281504	0	0
T17	198912	198128	0	0
T18	172648	169904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	696024	693336	0	0
T2	202888	201712	0	0
T3	2928016	2862608	0	0
T4	14579152	14578984	0	0
T5	11235504	11233936	0	0
T14	321608	308168	0	0
T15	2333576	2317112	0	0
T16	8281840	8281504	0	0
T17	198912	198128	0	0
T18	172648	169904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	696024	693336	0	0
T2	202888	201712	0	0
T3	2928016	2862608	0	0
T4	14579152	14578984	0	0
T5	11235504	11233936	0	0
T14	321608	308168	0	0
T15	2333576	2317112	0	0
T16	8281840	8281504	0	0
T17	198912	198128	0	0
T18	172648	169904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	127336573	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	127336573	0	0
T1	12429	4456	0	0
T2	3623	3401	0	0
T3	52286	46335	0	0
T4	260342	12530	0	0
T5	200634	112487	0	0
T14	5743	2333	0	0
T15	41671	39017	0	0
T16	147890	144874	0	0
T17	3552	3440	0	0
T18	3083	2653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	88443359	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	88443359	0	0
T1	12429	2827	0	0
T2	3623	1737	0	0
T3	52286	27093	0	0
T4	260342	992863	0	0
T5	200634	45998	0	0
T14	5743	701	0	0
T15	41671	22668	0	0
T16	147890	11385	0	0
T17	3552	1805	0	0
T18	3083	2653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1634117	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1634117	0	0
T2	3623	37	0	0
T3	52286	1091	0	0
T4	260342	0	0	0
T5	200634	1476	0	0
T14	5743	100	0	0
T15	41671	1622	0	0
T16	147890	553	0	0
T17	3552	65	0	0
T18	3083	0	0	0
T19	79368	34	0	0
T20	0	17	0	0
T21	0	275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	4026237	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	4026237	0	0
T2	3623	37	0	0
T3	52286	1091	0	0
T4	260342	0	0	0
T5	200634	1060	0	0
T14	5743	21	0	0
T15	41671	1622	0	0
T16	147890	793	0	0
T17	3552	65	0	0
T18	3083	0	0	0
T19	79368	1525	0	0
T20	0	4	0	0
T21	0	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1611748	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1611748	0	0
T2	3623	35	0	0
T3	52286	1168	0	0
T4	260342	1390	0	0
T5	200634	2625	0	0
T14	5743	89	0	0
T15	41671	921	0	0
T16	147890	360	0	0
T17	3552	72	0	0
T18	3083	0	0	0
T19	79368	9	0	0
T20	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3834146	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3834146	0	0
T2	3623	35	0	0
T3	52286	1168	0	0
T4	260342	109288	0	0
T5	200634	1675	0	0
T14	5743	66	0	0
T15	41671	921	0	0
T16	147890	84	0	0
T17	3552	72	0	0
T18	3083	0	0	0
T19	79368	540	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1611041	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1611041	0	0
T2	3623	41	0	0
T3	52286	904	0	0
T4	260342	0	0	0
T5	200634	2397	0	0
T14	5743	59	0	0
T15	41671	863	0	0
T16	147890	469	0	0
T17	3552	63	0	0
T18	3083	0	0	0
T19	79368	13	0	0
T20	0	17	0	0
T21	0	371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2767423	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2767423	0	0
T2	3623	41	0	0
T3	52286	904	0	0
T4	260342	0	0	0
T5	200634	2331	0	0
T14	5743	10	0	0
T15	41671	863	0	0
T16	147890	106	0	0
T17	3552	63	0	0
T18	3083	0	0	0
T19	79368	3	0	0
T20	0	5	0	0
T21	0	325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1663255	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1663255	0	0
T1	12429	1885	0	0
T2	3623	32	0	0
T3	52286	963	0	0
T4	260342	2687	0	0
T5	200634	1930	0	0
T14	5743	86	0	0
T15	41671	452	0	0
T16	147890	456	0	0
T17	3552	77	0	0
T18	3083	0	0	0
T19	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3172362	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3172362	0	0
T1	12429	893	0	0
T2	3623	32	0	0
T3	52286	962	0	0
T4	260342	205723	0	0
T5	200634	2043	0	0
T14	5743	31	0	0
T15	41671	452	0	0
T16	147890	360	0	0
T17	3552	77	0	0
T18	3083	0	0	0
T19	0	1286	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1638554	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1638554	0	0
T2	3623	30	0	0
T3	52286	599	0	0
T4	260342	0	0	0
T5	200634	846	0	0
T14	5743	21	0	0
T15	41671	1109	0	0
T16	147890	472	0	0
T17	3552	58	0	0
T18	3083	472	0	0
T19	79368	18	0	0
T20	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2943884	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2943884	0	0
T2	3623	30	0	0
T3	52286	599	0	0
T4	260342	0	0	0
T5	200634	1165	0	0
T14	5743	35	0	0
T15	41671	1109	0	0
T16	147890	107	0	0
T17	3552	58	0	0
T18	3083	472	0	0
T19	79368	1018	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1647028	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1647028	0	0
T2	3623	24	0	0
T3	52286	838	0	0
T4	260342	0	0	0
T5	200634	2073	0	0
T14	5743	36	0	0
T15	41671	1477	0	0
T16	147890	453	0	0
T17	3552	64	0	0
T18	3083	0	0	0
T19	79368	7	0	0
T20	0	23	0	0
T21	0	368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	4072093	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	4072093	0	0
T2	3623	24	0	0
T3	52286	837	0	0
T4	260342	0	0	0
T5	200634	3002	0	0
T14	5743	11	0	0
T15	41671	1477	0	0
T16	147890	449	0	0
T17	3552	64	0	0
T18	3083	0	0	0
T19	79368	23	0	0
T20	0	7	0	0
T21	0	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1642603	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1642603	0	0
T2	3623	33	0	0
T3	52286	949	0	0
T4	260342	0	0	0
T5	200634	2976	0	0
T14	5743	71	0	0
T15	41671	873	0	0
T16	147890	489	0	0
T17	3552	61	0	0
T18	3083	0	0	0
T19	79368	9	0	0
T20	0	35	0	0
T21	0	335	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2874893	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2874893	0	0
T2	3623	33	0	0
T3	52286	949	0	0
T4	260342	0	0	0
T5	200634	2262	0	0
T14	5743	40	0	0
T15	41671	873	0	0
T16	147890	375	0	0
T17	3552	61	0	0
T18	3083	0	0	0
T19	79368	592	0	0
T20	0	7	0	0
T21	0	247	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1613709	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1613709	0	0
T2	3623	24	0	0
T3	52286	981	0	0
T4	260342	1209	0	0
T5	200634	1591	0	0
T14	5743	77	0	0
T15	41671	412	0	0
T16	147890	401	0	0
T17	3552	61	0	0
T18	3083	268	0	0
T19	79368	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2596090	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2596090	0	0
T2	3623	24	0	0
T3	52286	981	0	0
T4	260342	95224	0	0
T5	200634	1153	0	0
T14	5743	24	0	0
T15	41671	411	0	0
T16	147890	88	0	0
T17	3552	61	0	0
T18	3083	268	0	0
T19	79368	696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1636373	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1636373	0	0
T2	3623	25	0	0
T3	52286	1181	0	0
T4	260342	0	0	0
T5	200634	3126	0	0
T14	5743	74	0	0
T15	41671	666	0	0
T16	147890	462	0	0
T17	3552	69	0	0
T18	3083	0	0	0
T19	79368	16	0	0
T20	0	21	0	0
T21	0	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2795767	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2795767	0	0
T2	3623	25	0	0
T3	52286	1180	0	0
T4	260342	0	0	0
T5	200634	3455	0	0
T14	5743	35	0	0
T15	41671	666	0	0
T16	147890	1147	0	0
T17	3552	69	0	0
T18	3083	0	0	0
T19	79368	188	0	0
T20	0	5	0	0
T21	0	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1658121	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1658121	0	0
T2	3623	33	0	0
T3	52286	1124	0	0
T4	260342	0	0	0
T5	200634	1500	0	0
T14	5743	47	0	0
T15	41671	675	0	0
T16	147890	436	0	0
T17	3552	62	0	0
T18	3083	209	0	0
T19	79368	9	0	0
T20	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2807296	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2807296	0	0
T2	3623	33	0	0
T3	52286	1123	0	0
T4	260342	0	0	0
T5	200634	650	0	0
T14	5743	11	0	0
T15	41671	675	0	0
T16	147890	102	0	0
T17	3552	62	0	0
T18	3083	209	0	0
T19	79368	1	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1684199	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1684199	0	0
T2	3623	34	0	0
T3	52286	948	0	0
T4	260342	940	0	0
T5	200634	1131	0	0
T14	5743	95	0	0
T15	41671	392	0	0
T16	147890	446	0	0
T17	3552	58	0	0
T18	3083	0	0	0
T19	79368	34	0	0
T20	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3632561	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3632561	0	0
T2	3623	34	0	0
T3	52286	948	0	0
T4	260342	76518	0	0
T5	200634	783	0	0
T14	5743	58	0	0
T15	41671	392	0	0
T16	147890	115	0	0
T17	3552	58	0	0
T18	3083	0	0	0
T19	79368	995	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1576144	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1576144	0	0
T2	3623	33	0	0
T3	52286	958	0	0
T4	260342	0	0	0
T5	200634	2617	0	0
T14	5743	67	0	0
T15	41671	412	0	0
T16	147890	416	0	0
T17	3552	56	0	0
T18	3083	0	0	0
T19	79368	5	0	0
T20	0	22	0	0
T21	0	340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2355668	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2355668	0	0
T2	3623	33	0	0
T3	52286	958	0	0
T4	260342	0	0	0
T5	200634	1321	0	0
T14	5743	29	0	0
T15	41671	412	0	0
T16	147890	112	0	0
T17	3552	56	0	0
T18	3083	0	0	0
T19	79368	80	0	0
T20	0	6	0	0
T21	0	302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1621603	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1621603	0	0
T1	12429	1367	0	0
T2	3623	41	0	0
T3	52286	1121	0	0
T4	260342	2326	0	0
T5	200634	2444	0	0
T14	5743	45	0	0
T15	41671	710	0	0
T16	147890	403	0	0
T17	3552	65	0	0
T18	3083	0	0	0
T19	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2888387	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2888387	0	0
T1	12429	1109	0	0
T2	3623	41	0	0
T3	52286	1120	0	0
T4	260342	190808	0	0
T5	200634	1591	0	0
T14	5743	15	0	0
T15	41671	710	0	0
T16	147890	95	0	0
T17	3552	65	0	0
T18	3083	0	0	0
T19	0	5231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1638995	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1638995	0	0
T2	3623	35	0	0
T3	52286	1147	0	0
T4	260342	982	0	0
T5	200634	2993	0	0
T14	5743	38	0	0
T15	41671	398	0	0
T16	147890	417	0	0
T17	3552	68	0	0
T18	3083	0	0	0
T19	79368	22	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3334628	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3334628	0	0
T2	3623	35	0	0
T3	52286	1147	0	0
T4	260342	71981	0	0
T5	200634	2555	0	0
T14	5743	25	0	0
T15	41671	398	0	0
T16	147890	105	0	0
T17	3552	68	0	0
T18	3083	0	0	0
T19	79368	1853	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1636840	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1636840	0	0
T1	12429	1204	0	0
T2	3623	31	0	0
T3	52286	952	0	0
T4	260342	0	0	0
T5	200634	2645	0	0
T14	5743	36	0	0
T15	41671	911	0	0
T16	147890	550	0	0
T17	3552	66	0	0
T18	3083	0	0	0
T19	0	11	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3224541	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3224541	0	0
T1	12429	825	0	0
T2	3623	31	0	0
T3	52286	952	0	0
T4	260342	0	0	0
T5	200634	1050	0	0
T14	5743	34	0	0
T15	41671	910	0	0
T16	147890	732	0	0
T17	3552	66	0	0
T18	3083	0	0	0
T19	0	704	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1635609	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1635609	0	0
T2	3623	31	0	0
T3	52286	642	0	0
T4	260342	2092	0	0
T5	200634	2544	0	0
T14	5743	65	0	0
T15	41671	418	0	0
T16	147890	378	0	0
T17	3552	62	0	0
T18	3083	0	0	0
T19	79368	9	0	0
T20	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3272797	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3272797	0	0
T2	3623	31	0	0
T3	52286	642	0	0
T4	260342	170759	0	0
T5	200634	1217	0	0
T14	5743	19	0	0
T15	41671	418	0	0
T16	147890	91	0	0
T17	3552	62	0	0
T18	3083	0	0	0
T19	79368	690	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1630295	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1630295	0	0
T2	3623	39	0	0
T3	52286	953	0	0
T4	260342	0	0	0
T5	200634	1407	0	0
T14	5743	45	0	0
T15	41671	634	0	0
T16	147890	477	0	0
T17	3552	81	0	0
T18	3083	0	0	0
T19	79368	38	0	0
T20	0	38	0	0
T21	0	289	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3193801	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3193801	0	0
T2	3623	39	0	0
T3	52286	953	0	0
T4	260342	0	0	0
T5	200634	1043	0	0
T14	5743	18	0	0
T15	41671	634	0	0
T16	147890	266	0	0
T17	3552	81	0	0
T18	3083	0	0	0
T19	79368	1668	0	0
T20	0	9	0	0
T21	0	243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1579160	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1579160	0	0
T2	3623	30	0	0
T3	52286	1005	0	0
T4	260342	0	0	0
T5	200634	1220	0	0
T14	5743	55	0	0
T15	41671	904	0	0
T16	147890	404	0	0
T17	3552	60	0	0
T18	3083	0	0	0
T19	79368	30	0	0
T20	0	60	0	0
T21	0	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3557274	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3557274	0	0
T2	3623	30	0	0
T3	52286	1003	0	0
T4	260342	0	0	0
T5	200634	158	0	0
T14	5743	29	0	0
T15	41671	904	0	0
T16	147890	88	0	0
T17	3552	60	0	0
T18	3083	0	0	0
T19	79368	1108	0	0
T20	0	11	0	0
T21	0	334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1578498	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1578498	0	0
T2	3623	30	0	0
T3	52286	1149	0	0
T4	260342	0	0	0
T5	200634	834	0	0
T14	5743	23	0	0
T15	41671	410	0	0
T16	147890	474	0	0
T17	3552	59	0	0
T18	3083	237	0	0
T19	79368	11	0	0
T20	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3296166	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3296166	0	0
T2	3623	30	0	0
T3	52286	1149	0	0
T4	260342	0	0	0
T5	200634	1232	0	0
T14	5743	28	0	0
T15	41671	410	0	0
T16	147890	1278	0	0
T17	3552	59	0	0
T18	3083	237	0	0
T19	79368	932	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1627538	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1627538	0	0
T2	3623	28	0	0
T3	52286	878	0	0
T4	260342	0	0	0
T5	200634	3688	0	0
T14	5743	102	0	0
T15	41671	617	0	0
T16	147890	515	0	0
T17	3552	89	0	0
T18	3083	0	0	0
T19	79368	23	0	0
T20	0	26	0	0
T21	0	340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3578657	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3578657	0	0
T2	3623	28	0	0
T3	52286	878	0	0
T4	260342	0	0	0
T5	200634	3349	0	0
T14	5743	14	0	0
T15	41671	617	0	0
T16	147890	120	0	0
T17	3552	89	0	0
T18	3083	0	0	0
T19	79368	944	0	0
T20	0	340	0	0
T21	0	318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1636168	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1636168	0	0
T2	3623	31	0	0
T3	52286	711	0	0
T4	260342	0	0	0
T5	200634	1608	0	0
T14	5743	40	0	0
T15	41671	687	0	0
T16	147890	469	0	0
T17	3552	79	0	0
T18	3083	0	0	0
T19	79368	19	0	0
T20	0	29	0	0
T21	0	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3881565	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3881565	0	0
T2	3623	31	0	0
T3	52286	710	0	0
T4	260342	0	0	0
T5	200634	232	0	0
T14	5743	28	0	0
T15	41671	686	0	0
T16	147890	113	0	0
T17	3552	79	0	0
T18	3083	0	0	0
T19	79368	1087	0	0
T20	0	8	0	0
T21	0	358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1596122	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1596122	0	0
T2	3623	37	0	0
T3	52286	733	0	0
T4	260342	904	0	0
T5	200634	1138	0	0
T14	5743	41	0	0
T15	41671	734	0	0
T16	147890	472	0	0
T17	3552	67	0	0
T18	3083	0	0	0
T19	79368	8	0	0
T20	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2955849	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2955849	0	0
T2	3623	37	0	0
T3	52286	732	0	0
T4	260342	72562	0	0
T5	200634	1042	0	0
T14	5743	13	0	0
T15	41671	734	0	0
T16	147890	1208	0	0
T17	3552	67	0	0
T18	3083	0	0	0
T19	79368	1160	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1627417	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1627417	0	0
T2	3623	33	0	0
T3	52286	674	0	0
T4	260342	0	0	0
T5	200634	1579	0	0
T14	5743	24	0	0
T15	41671	636	0	0
T16	147890	519	0	0
T17	3552	69	0	0
T18	3083	486	0	0
T19	79368	27	0	0
T20	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3175292	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3175292	0	0
T2	3623	33	0	0
T3	52286	674	0	0
T4	260342	0	0	0
T5	200634	1414	0	0
T14	5743	16	0	0
T15	41671	636	0	0
T16	147890	930	0	0
T17	3552	69	0	0
T18	3083	486	0	0
T19	79368	2153	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1631025	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1631025	0	0
T2	3623	23	0	0
T3	52286	630	0	0
T4	260342	0	0	0
T5	200634	2274	0	0
T14	5743	70	0	0
T15	41671	695	0	0
T16	147890	506	0	0
T17	3552	77	0	0
T18	3083	244	0	0
T19	79368	20	0	0
T20	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3375624	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3375624	0	0
T2	3623	23	0	0
T3	52286	630	0	0
T4	260342	0	0	0
T5	200634	1318	0	0
T14	5743	32	0	0
T15	41671	695	0	0
T16	147890	116	0	0
T17	3552	77	0	0
T18	3083	244	0	0
T19	79368	799	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1606221	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1606221	0	0
T2	3623	29	0	0
T3	52286	865	0	0
T4	260342	0	0	0
T5	200634	1443	0	0
T14	5743	83	0	0
T15	41671	434	0	0
T16	147890	468	0	0
T17	3552	56	0	0
T18	3083	0	0	0
T19	79368	5	0	0
T20	0	16	0	0
T21	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	2688089	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	2688089	0	0
T2	3623	29	0	0
T3	52286	864	0	0
T4	260342	0	0	0
T5	200634	1320	0	0
T14	5743	25	0	0
T15	41671	434	0	0
T16	147890	652	0	0
T17	3552	56	0	0
T18	3083	0	0	0
T19	79368	762	0	0
T20	0	4	0	0
T21	0	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1647621	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1647621	0	0
T2	3623	25	0	0
T3	52286	990	0	0
T4	260342	0	0	0
T5	200634	5268	0	0
T14	5743	35	0	0
T15	41671	450	0	0
T16	147890	352	0	0
T17	3552	80	0	0
T18	3083	500	0	0
T19	79368	1	0	0
T20	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	4147020	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	4147020	0	0
T2	3623	25	0	0
T3	52286	990	0	0
T4	260342	0	0	0
T5	200634	5872	0	0
T14	5743	4	0	0
T15	41671	449	0	0
T16	147890	732	0	0
T17	3552	80	0	0
T18	3083	500	0	0
T19	79368	720	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	1623059	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	1623059	0	0
T2	3623	35	0	0
T3	52286	656	0	0
T4	260342	0	0	0
T5	200634	2344	0	0
T14	5743	55	0	0
T15	41671	396	0	0
T16	147890	439	0	0
T17	3552	59	0	0
T18	3083	237	0	0
T19	79368	0	0	0
T20	0	30	0	0
T21	0	368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	318952944	3115261	0	0
DepthKnown_A	318952944	318836405	0	0
RvalidKnown_A	318952944	318836405	0	0
WreadyKnown_A	318952944	318836405	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	3115261	0	0
T2	3623	35	0	0
T3	52286	656	0	0
T4	260342	0	0	0
T5	200634	1705	0	0
T14	5743	15	0	0
T15	41671	395	0	0
T16	147890	1020	0	0
T17	3552	59	0	0
T18	3083	237	0	0
T19	79368	0	0	0
T20	0	7	0	0
T21	0	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318952944	318836405	0	0
T1	12429	12381	0	0
T2	3623	3602	0	0
T3	52286	51118	0	0
T4	260342	260339	0	0
T5	200634	200606	0	0
T14	5743	5503	0	0
T15	41671	41377	0	0
T16	147890	147884	0	0
T17	3552	3538	0	0
T18	3083	3034	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0