Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1683538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263722

1

T1

82

T2

5

T3

559

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	661218	1			T1	367		T2	23		T3	1283
values[0x0]	627599	1			T1	74		T2	5		T3	1342
values[0x1]	658443	1			T1	403		T2	23		T3	1396

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1303252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644008

1

T1

319

T2

15

T3

1319

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8185	1			T1	4		T3	10		T4	5
valid_sources[0x01]	7199	1			T1	7		T2	2		T3	21
valid_sources[0x02]	7924	1			T1	2		T3	4		T4	5
valid_sources[0x03]	7886	1			T3	14		T4	4		T11	1
valid_sources[0x04]	8125	1			T1	1		T2	1		T3	32
valid_sources[0x05]	7883	1			T1	2		T3	12		T4	4
valid_sources[0x06]	7241	1			T1	2		T3	5		T4	6
valid_sources[0x07]	7181	1			T1	9		T3	15		T4	5
valid_sources[0x08]	7769	1			T1	3		T3	15		T4	6
valid_sources[0x09]	7612	1			T1	2		T3	11		T4	5
valid_sources[0x0a]	8060	1			T1	3		T2	1		T3	14
valid_sources[0x0b]	9564	1			T1	2		T3	7		T4	5
valid_sources[0x0c]	8487	1			T1	1		T3	14		T4	4
valid_sources[0x0d]	7649	1			T1	3		T2	1		T3	12
valid_sources[0x0e]	7899	1			T1	1		T3	16		T4	5
valid_sources[0x0f]	8041	1			T1	5		T3	15		T4	5
valid_sources[0x10]	7871	1			T1	2		T3	11		T4	5
valid_sources[0x11]	7622	1			T1	5		T3	16		T4	4
valid_sources[0x12]	6498	1			T1	7		T3	16		T4	5
valid_sources[0x13]	6784	1			T1	1		T3	8		T4	5
valid_sources[0x14]	6899	1			T1	2		T3	10		T4	4
valid_sources[0x15]	7457	1			T3	21		T4	5		T11	1
valid_sources[0x16]	7501	1			T1	4		T3	13		T4	5
valid_sources[0x17]	7097	1			T1	3		T3	13		T4	5
valid_sources[0x18]	7733	1			T1	8		T3	22		T4	5
valid_sources[0x19]	7388	1			T2	2		T3	12		T4	3
valid_sources[0x1a]	8068	1			T1	4		T3	7		T4	5
valid_sources[0x1b]	7622	1			T1	3		T3	18		T4	5
valid_sources[0x1c]	7473	1			T1	7		T3	18		T4	6
valid_sources[0x1d]	7626	1			T1	2		T3	16		T4	5
valid_sources[0x1e]	7158	1			T1	1		T3	17		T4	5
valid_sources[0x1f]	7175	1			T1	6		T3	13		T4	5
valid_sources[0x20]	6945	1			T1	6		T3	12		T4	5
valid_sources[0x21]	7371	1			T1	9		T3	7		T4	5
valid_sources[0x22]	8360	1			T1	3		T3	21		T4	5
valid_sources[0x23]	7415	1			T1	3		T3	10		T4	5
valid_sources[0x24]	7982	1			T1	1		T2	1		T3	17
valid_sources[0x25]	8552	1			T1	2		T3	21		T4	6
valid_sources[0x26]	8004	1			T1	1		T3	16		T4	5
valid_sources[0x27]	7548	1			T1	3		T3	18		T4	5
valid_sources[0x28]	7201	1			T1	4		T3	11		T4	5
valid_sources[0x29]	7202	1			T1	3		T3	6		T4	5
valid_sources[0x2a]	7373	1			T1	4		T3	13		T4	4
valid_sources[0x2b]	7653	1			T1	4		T3	16		T4	5
valid_sources[0x2c]	6779	1			T1	2		T3	6		T4	5
valid_sources[0x2d]	7741	1			T1	2		T2	1		T3	18
valid_sources[0x2e]	8434	1			T1	5		T3	14		T4	5
valid_sources[0x2f]	8175	1			T1	2		T3	6		T4	5
valid_sources[0x30]	7824	1			T1	1		T3	27		T4	5
valid_sources[0x31]	6723	1			T1	2		T3	16		T4	5
valid_sources[0x32]	7489	1			T1	1		T2	1		T3	13
valid_sources[0x33]	7279	1			T1	5		T3	10		T4	6
valid_sources[0x34]	7988	1			T1	5		T3	25		T4	4
valid_sources[0x35]	7552	1			T1	7		T3	11		T4	3
valid_sources[0x36]	7383	1			T1	8		T3	19		T4	7
valid_sources[0x37]	8044	1			T1	2		T3	20		T4	4
valid_sources[0x38]	7964	1			T1	5		T3	22		T4	5
valid_sources[0x39]	7612	1			T1	1		T3	12		T4	4
valid_sources[0x3a]	7423	1			T1	3		T3	3		T4	4
valid_sources[0x3b]	7548	1			T1	2		T3	24		T4	3
valid_sources[0x3c]	6449	1			T2	1		T3	13		T4	5
valid_sources[0x3d]	6605	1			T1	2		T3	16		T4	5
valid_sources[0x3e]	7085	1			T1	4		T3	15		T4	5
valid_sources[0x3f]	7882	1			T1	1		T2	1		T3	10
valid_sources[0x40]	7975	1			T1	3		T3	10		T4	5
valid_sources[0x41]	7181	1			T1	1		T3	19		T4	5
valid_sources[0x42]	7357	1			T1	1		T3	19		T4	4
valid_sources[0x43]	8788	1			T1	6		T3	7		T4	5
valid_sources[0x44]	7358	1			T1	6		T3	28		T4	5
valid_sources[0x45]	7052	1			T1	5		T2	1		T3	30
valid_sources[0x46]	8084	1			T1	8		T3	15		T4	4
valid_sources[0x47]	7768	1			T1	3		T3	7		T4	5
valid_sources[0x48]	7970	1			T1	3		T3	26		T4	5
valid_sources[0x49]	8304	1			T1	4		T3	18		T4	5
valid_sources[0x4a]	7146	1			T1	7		T3	16		T4	5
valid_sources[0x4b]	7698	1			T1	2		T2	1		T3	7
valid_sources[0x4c]	7328	1			T1	4		T2	1		T3	19
valid_sources[0x4d]	7670	1			T1	3		T3	6		T4	6
valid_sources[0x4e]	6994	1			T3	21		T4	5		T15	1
valid_sources[0x4f]	7264	1			T1	4		T2	1		T3	25
valid_sources[0x50]	9296	1			T1	4		T3	15		T4	5
valid_sources[0x51]	8019	1			T1	3		T2	1		T3	19
valid_sources[0x52]	8840	1			T3	19		T4	5		T12	4
valid_sources[0x53]	7738	1			T1	5		T3	10		T4	5
valid_sources[0x54]	7142	1			T1	3		T3	20		T4	3
valid_sources[0x55]	7348	1			T1	9		T3	17		T4	5
valid_sources[0x56]	7794	1			T1	1		T3	28		T4	5
valid_sources[0x57]	8244	1			T1	1		T3	17		T4	4
valid_sources[0x58]	7594	1			T1	1		T3	21		T4	5
valid_sources[0x59]	7840	1			T1	2		T3	15		T4	5
valid_sources[0x5a]	8110	1			T1	3		T3	13		T4	4
valid_sources[0x5b]	7301	1			T1	3		T3	24		T4	5
valid_sources[0x5c]	8374	1			T1	13		T2	1		T3	13
valid_sources[0x5d]	8279	1			T1	2		T2	1		T3	17
valid_sources[0x5e]	7167	1			T1	3		T3	10		T4	5
valid_sources[0x5f]	8453	1			T1	2		T3	12		T4	5
valid_sources[0x60]	8918	1			T3	25		T4	5		T17	15
valid_sources[0x61]	9325	1			T1	2		T3	17		T4	5
valid_sources[0x62]	7596	1			T1	3		T3	17		T4	5
valid_sources[0x63]	7294	1			T1	10		T3	18		T4	5
valid_sources[0x64]	8051	1			T1	6		T2	1		T3	18
valid_sources[0x65]	7540	1			T1	5		T2	1		T3	7
valid_sources[0x66]	7528	1			T1	2		T3	13		T4	4
valid_sources[0x67]	6873	1			T1	1		T2	1		T3	15
valid_sources[0x68]	7237	1			T3	9		T4	5		T11	1
valid_sources[0x69]	7891	1			T1	4		T3	13		T4	4
valid_sources[0x6a]	7167	1			T1	3		T2	1		T3	10
valid_sources[0x6b]	7255	1			T1	9		T3	17		T4	5
valid_sources[0x6c]	7358	1			T1	7		T3	19		T4	5
valid_sources[0x6d]	8424	1			T1	3		T3	15		T4	5
valid_sources[0x6e]	7241	1			T1	2		T3	19		T4	5
valid_sources[0x6f]	7819	1			T1	2		T3	12		T4	4
valid_sources[0x70]	7810	1			T1	2		T3	14		T4	5
valid_sources[0x71]	7371	1			T1	4		T2	1		T3	6
valid_sources[0x72]	7169	1			T1	4		T3	15		T4	4
valid_sources[0x73]	8065	1			T1	3		T3	18		T4	6
valid_sources[0x74]	6848	1			T1	1		T3	18		T4	4
valid_sources[0x75]	8024	1			T1	1		T3	17		T4	5
valid_sources[0x76]	6998	1			T1	2		T3	33		T4	4
valid_sources[0x77]	7333	1			T1	3		T3	15		T4	4
valid_sources[0x78]	7784	1			T1	4		T2	1		T3	14
valid_sources[0x79]	7090	1			T1	4		T3	7		T4	5
valid_sources[0x7a]	8431	1			T1	1		T3	14		T4	6
valid_sources[0x7b]	8439	1			T2	1		T3	10		T4	5
valid_sources[0x7c]	8126	1			T1	3		T3	10		T4	4
valid_sources[0x7d]	7484	1			T3	11		T4	5		T17	24
valid_sources[0x7e]	7704	1			T3	18		T4	3		T15	1
valid_sources[0x7f]	7043	1			T1	5		T3	22		T4	4
valid_sources[0x80]	7327	1			T1	2		T3	13		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27741

1

T1

34

T2

1

T3

50

values[0x0]

all_enables

biggest_size

208181

1

T1

25

T2

3

T3

442

values[0x1]

all_enables

biggest_size

27800

1

T1

23

T2

1

T3

67