Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	313229125	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	313229125	0	0
T1	24650304	620951	0	0
T2	124712	4978	0	0
T3	4271288	128948	0	0
T4	6214600	913900	0	0
T5	23408	636	0	0
T11	299488	12694	0	0
T12	2707040	49978	0	0
T13	0	815562	0	0
T14	0	6644	0	0
T15	3676904	96557	0	0
T16	3269728	67521	0	0
T17	285096	11565	0	0
T18	0	424	0	0
T19	0	88688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24650304	24641736	0	0
T2	124712	122640	0	0
T3	4271288	4265632	0	0
T4	6214600	6214208	0	0
T5	23408	21896	0	0
T11	299488	297192	0	0
T12	2707040	2705472	0	0
T15	3676904	3676120	0	0
T16	3269728	3268216	0	0
T17	285096	281232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24650304	24641736	0	0
T2	124712	122640	0	0
T3	4271288	4265632	0	0
T4	6214600	6214208	0	0
T5	23408	21896	0	0
T11	299488	297192	0	0
T12	2707040	2705472	0	0
T15	3676904	3676120	0	0
T16	3269728	3268216	0	0
T17	285096	281232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24650304	24641736	0	0
T2	124712	122640	0	0
T3	4271288	4265632	0	0
T4	6214600	6214208	0	0
T5	23408	21896	0	0
T11	299488	297192	0	0
T12	2707040	2705472	0	0
T15	3676904	3676120	0	0
T16	3269728	3268216	0	0
T17	285096	281232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	111234464	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	111234464	0	0
T1	440184	235224	0	0
T2	2227	1924	0	0
T3	76273	31471	0	0
T4	110975	5591	0	0
T5	418	249	0	0
T11	5348	4942	0	0
T12	48340	20186	0	0
T15	65659	41508	0	0
T16	58388	30763	0	0
T17	5091	4503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	82197159	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	82197159	0	0
T1	440184	145423	0	0
T2	2227	1018	0	0
T3	76273	33003	0	0
T4	110975	451359	0	0
T5	418	129	0	0
T11	5348	2584	0	0
T12	48340	13497	0	0
T15	65659	18622	0	0
T16	58388	8356	0	0
T17	5091	2354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1441847	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1441847	0	0
T1	440184	6266	0	0
T2	2227	44	0	0
T3	76273	2838	0	0
T4	110975	0	0	0
T5	418	6	0	0
T11	5348	88	0	0
T12	48340	346	0	0
T15	65659	592	0	0
T16	58388	760	0	0
T17	5091	78	0	0
T19	0	2872	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3411482	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3411482	0	0
T1	440184	6480	0	0
T2	2227	44	0	0
T3	76273	4036	0	0
T4	110975	0	0	0
T5	418	6	0	0
T11	5348	88	0	0
T12	48340	334	0	0
T15	65659	699	0	0
T16	58388	254	0	0
T17	5091	78	0	0
T19	0	2073	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1392867	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1392867	0	0
T1	440184	5934	0	0
T2	2227	37	0	0
T3	76273	1638	0	0
T4	110975	0	0	0
T5	418	10	0	0
T11	5348	97	0	0
T12	48340	315	0	0
T15	65659	525	0	0
T16	58388	842	0	0
T17	5091	88	0	0
T19	0	1534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3239056	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3239056	0	0
T1	440184	6270	0	0
T2	2227	37	0	0
T3	76273	1672	0	0
T4	110975	0	0	0
T5	418	10	0	0
T11	5348	97	0	0
T12	48340	225	0	0
T15	65659	581	0	0
T16	58388	324	0	0
T17	5091	88	0	0
T19	0	988	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1448652	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1448652	0	0
T1	440184	4209	0	0
T2	2227	40	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	83	0	0
T12	48340	353	0	0
T13	0	1387	0	0
T15	65659	619	0	0
T16	58388	656	0	0
T17	5091	85	0	0
T19	0	1221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3054164	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3054164	0	0
T1	440184	4277	0	0
T2	2227	40	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	83	0	0
T12	48340	282	0	0
T13	0	103880	0	0
T15	65659	703	0	0
T16	58388	283	0	0
T17	5091	85	0	0
T19	0	1215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1385821	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1385821	0	0
T1	440184	6599	0	0
T2	2227	30	0	0
T3	76273	2351	0	0
T4	110975	980	0	0
T5	418	4	0	0
T11	5348	82	0	0
T12	48340	372	0	0
T15	65659	600	0	0
T16	58388	614	0	0
T17	5091	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2639276	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2639276	0	0
T1	440184	6587	0	0
T2	2227	30	0	0
T3	76273	2459	0	0
T4	110975	72151	0	0
T5	418	4	0	0
T11	5348	82	0	0
T12	48340	315	0	0
T15	65659	698	0	0
T16	58388	253	0	0
T17	5091	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1356059	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1356059	0	0
T1	440184	3911	0	0
T2	2227	31	0	0
T3	76273	2400	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	103	0	0
T12	48340	377	0	0
T15	65659	739	0	0
T16	58388	776	0	0
T17	5091	86	0	0
T19	0	397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2146228	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2146228	0	0
T1	440184	3996	0	0
T2	2227	31	0	0
T3	76273	2501	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	103	0	0
T12	48340	266	0	0
T15	65659	727	0	0
T16	58388	377	0	0
T17	5091	86	0	0
T19	0	1475	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1425580	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1425580	0	0
T1	440184	2447	0	0
T2	2227	24	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	1	0	0
T11	5348	80	0	0
T12	48340	298	0	0
T14	0	436	0	0
T15	65659	774	0	0
T16	58388	656	0	0
T17	5091	78	0	0
T19	0	3999	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3243598	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3243598	0	0
T1	440184	2421	0	0
T2	2227	24	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	1	0	0
T11	5348	80	0	0
T12	48340	220	0	0
T14	0	436	0	0
T15	65659	796	0	0
T16	58388	320	0	0
T17	5091	78	0	0
T19	0	4368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1457484	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1457484	0	0
T1	440184	2290	0	0
T2	2227	46	0	0
T3	76273	2179	0	0
T4	110975	0	0	0
T5	418	9	0	0
T11	5348	103	0	0
T12	48340	401	0	0
T13	0	1242	0	0
T15	65659	677	0	0
T16	58388	891	0	0
T17	5091	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2988682	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2988682	0	0
T1	440184	2326	0	0
T2	2227	46	0	0
T3	76273	2140	0	0
T4	110975	0	0	0
T5	418	9	0	0
T11	5348	103	0	0
T12	48340	289	0	0
T13	0	89797	0	0
T15	65659	793	0	0
T16	58388	268	0	0
T17	5091	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1349538	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1349538	0	0
T1	440184	4118	0	0
T2	2227	34	0	0
T3	76273	1879	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	95	0	0
T12	48340	489	0	0
T13	0	1272	0	0
T15	65659	614	0	0
T16	58388	741	0	0
T17	5091	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3409837	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3409837	0	0
T1	440184	4316	0	0
T2	2227	34	0	0
T3	76273	1861	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	95	0	0
T12	48340	391	0	0
T13	0	94159	0	0
T15	65659	695	0	0
T16	58388	259	0	0
T17	5091	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1439898	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1439898	0	0
T1	440184	4229	0	0
T2	2227	39	0	0
T3	76273	2187	0	0
T4	110975	0	0	0
T5	418	7	0	0
T11	5348	108	0	0
T12	48340	373	0	0
T15	65659	529	0	0
T16	58388	626	0	0
T17	5091	91	0	0
T19	0	859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3739599	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3739599	0	0
T1	440184	4487	0	0
T2	2227	39	0	0
T3	76273	2286	0	0
T4	110975	0	0	0
T5	418	7	0	0
T11	5348	108	0	0
T12	48340	227	0	0
T15	65659	538	0	0
T16	58388	246	0	0
T17	5091	91	0	0
T19	0	2269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1452774	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1452774	0	0
T1	440184	6419	0	0
T2	2227	42	0	0
T3	76273	0	0	0
T4	110975	1224	0	0
T5	418	6	0	0
T11	5348	112	0	0
T12	48340	357	0	0
T15	65659	720	0	0
T16	58388	930	0	0
T17	5091	84	0	0
T19	0	2728	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3281419	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3281419	0	0
T1	440184	6944	0	0
T2	2227	42	0	0
T3	76273	0	0	0
T4	110975	99867	0	0
T5	418	6	0	0
T11	5348	112	0	0
T12	48340	313	0	0
T15	65659	691	0	0
T16	58388	342	0	0
T17	5091	84	0	0
T19	0	2254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1436355	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1436355	0	0
T1	440184	4357	0	0
T2	2227	35	0	0
T3	76273	3121	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	91	0	0
T12	48340	319	0	0
T15	65659	770	0	0
T16	58388	699	0	0
T17	5091	80	0	0
T19	0	652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2785715	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2785715	0	0
T1	440184	4377	0	0
T2	2227	35	0	0
T3	76273	3072	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	91	0	0
T12	48340	210	0	0
T15	65659	804	0	0
T16	58388	296	0	0
T17	5091	80	0	0
T19	0	866	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1462643	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1462643	0	0
T1	440184	4699	0	0
T2	2227	38	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	245	0	0
T14	0	187	0	0
T15	65659	687	0	0
T16	58388	709	0	0
T17	5091	97	0	0
T19	0	1500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3187257	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3187257	0	0
T1	440184	4960	0	0
T2	2227	38	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	260	0	0
T14	0	187	0	0
T15	65659	701	0	0
T16	58388	288	0	0
T17	5091	97	0	0
T19	0	3191	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1427400	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1427400	0	0
T1	440184	6736	0	0
T2	2227	34	0	0
T3	76273	0	0	0
T4	110975	1038	0	0
T5	418	2	0	0
T11	5348	94	0	0
T12	48340	313	0	0
T13	0	1297	0	0
T15	65659	760	0	0
T16	58388	713	0	0
T17	5091	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3168956	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3168956	0	0
T1	440184	6674	0	0
T2	2227	34	0	0
T3	76273	0	0	0
T4	110975	84768	0	0
T5	418	2	0	0
T11	5348	94	0	0
T12	48340	263	0	0
T13	0	99381	0	0
T15	65659	744	0	0
T16	58388	344	0	0
T17	5091	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1437247	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1437247	0	0
T1	440184	2666	0	0
T2	2227	45	0	0
T3	76273	1778	0	0
T4	110975	1107	0	0
T5	418	5	0	0
T11	5348	117	0	0
T12	48340	277	0	0
T15	65659	525	0	0
T16	58388	688	0	0
T17	5091	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3280463	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3280463	0	0
T1	440184	2412	0	0
T2	2227	45	0	0
T3	76273	1764	0	0
T4	110975	93260	0	0
T5	418	5	0	0
T11	5348	117	0	0
T12	48340	187	0	0
T15	65659	654	0	0
T16	58388	314	0	0
T17	5091	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1456124	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1456124	0	0
T1	440184	4338	0	0
T2	2227	40	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	72	0	0
T12	48340	234	0	0
T15	65659	580	0	0
T16	58388	577	0	0
T17	5091	100	0	0
T18	0	212	0	0
T19	0	2760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3186825	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3186825	0	0
T1	440184	4345	0	0
T2	2227	40	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	72	0	0
T12	48340	264	0	0
T15	65659	575	0	0
T16	58388	266	0	0
T17	5091	100	0	0
T18	0	212	0	0
T19	0	3189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1463601	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1463601	0	0
T1	440184	7503	0	0
T2	2227	35	0	0
T3	76273	1642	0	0
T4	110975	0	0	0
T5	418	11	0	0
T11	5348	95	0	0
T12	48340	243	0	0
T15	65659	715	0	0
T16	58388	848	0	0
T17	5091	99	0	0
T19	0	2112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3551372	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3551372	0	0
T1	440184	7112	0	0
T2	2227	35	0	0
T3	76273	1418	0	0
T4	110975	0	0	0
T5	418	11	0	0
T11	5348	95	0	0
T12	48340	228	0	0
T15	65659	802	0	0
T16	58388	382	0	0
T17	5091	99	0	0
T19	0	1924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1422396	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1422396	0	0
T1	440184	2468	0	0
T2	2227	46	0	0
T3	76273	1258	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	98	0	0
T12	48340	227	0	0
T13	0	2024	0	0
T15	65659	734	0	0
T16	58388	848	0	0
T17	5091	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2971079	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2971079	0	0
T1	440184	2685	0	0
T2	2227	46	0	0
T3	76273	1654	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	98	0	0
T12	48340	209	0	0
T13	0	147373	0	0
T15	65659	762	0	0
T16	58388	376	0	0
T17	5091	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1403186	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1403186	0	0
T1	440184	4012	0	0
T2	2227	38	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	466	0	0
T14	0	712	0	0
T15	65659	556	0	0
T16	58388	833	0	0
T17	5091	96	0	0
T19	0	2184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3353603	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3353603	0	0
T1	440184	4353	0	0
T2	2227	38	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	284	0	0
T14	0	712	0	0
T15	65659	656	0	0
T16	58388	255	0	0
T17	5091	96	0	0
T19	0	2192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1417729	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1417729	0	0
T1	440184	2361	0	0
T2	2227	41	0	0
T3	76273	4173	0	0
T4	110975	0	0	0
T5	418	2	0	0
T11	5348	89	0	0
T12	48340	231	0	0
T15	65659	754	0	0
T16	58388	771	0	0
T17	5091	97	0	0
T19	0	3018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2573109	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2573109	0	0
T1	440184	2468	0	0
T2	2227	41	0	0
T3	76273	4256	0	0
T4	110975	0	0	0
T5	418	2	0	0
T11	5348	89	0	0
T12	48340	221	0	0
T15	65659	710	0	0
T16	58388	301	0	0
T17	5091	97	0	0
T19	0	2942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1451176	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1451176	0	0
T1	440184	8738	0	0
T2	2227	41	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	351	0	0
T13	0	1250	0	0
T15	65659	703	0	0
T16	58388	726	0	0
T17	5091	98	0	0
T19	0	1280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3198445	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3198445	0	0
T1	440184	8417	0	0
T2	2227	41	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	106	0	0
T12	48340	223	0	0
T13	0	96341	0	0
T15	65659	723	0	0
T16	58388	304	0	0
T17	5091	98	0	0
T19	0	2777	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1466875	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1466875	0	0
T1	440184	2567	0	0
T2	2227	44	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	5	0	0
T11	5348	91	0	0
T12	48340	320	0	0
T14	0	611	0	0
T15	65659	803	0	0
T16	58388	625	0	0
T17	5091	89	0	0
T19	0	4714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2267486	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2267486	0	0
T1	440184	2533	0	0
T2	2227	44	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	5	0	0
T11	5348	91	0	0
T12	48340	308	0	0
T14	0	611	0	0
T15	65659	752	0	0
T16	58388	276	0	0
T17	5091	89	0	0
T19	0	3266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1473906	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1473906	0	0
T1	440184	3896	0	0
T2	2227	35	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	2	0	0
T11	5348	101	0	0
T12	48340	446	0	0
T14	0	737	0	0
T15	65659	615	0	0
T16	58388	679	0	0
T17	5091	86	0	0
T19	0	2292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2849078	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2849078	0	0
T1	440184	4234	0	0
T2	2227	35	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	2	0	0
T11	5348	101	0	0
T12	48340	237	0	0
T14	0	737	0	0
T15	65659	584	0	0
T16	58388	335	0	0
T17	5091	86	0	0
T19	0	2938	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1415189	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1415189	0	0
T1	440184	4576	0	0
T2	2227	32	0	0
T3	76273	1974	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	97	0	0
T12	48340	319	0	0
T13	0	1086	0	0
T15	65659	544	0	0
T16	58388	762	0	0
T17	5091	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	3021337	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	3021337	0	0
T1	440184	4711	0	0
T2	2227	32	0	0
T3	76273	1894	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	97	0	0
T12	48340	227	0	0
T13	0	77765	0	0
T15	65659	625	0	0
T16	58388	416	0	0
T17	5091	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1421363	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1421363	0	0
T1	440184	2499	0	0
T2	2227	44	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	87	0	0
T12	48340	383	0	0
T14	0	197	0	0
T15	65659	701	0	0
T16	58388	765	0	0
T17	5091	82	0	0
T19	0	3810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2287235	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2287235	0	0
T1	440184	2482	0	0
T2	2227	44	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	4	0	0
T11	5348	87	0	0
T12	48340	295	0	0
T14	0	197	0	0
T15	65659	671	0	0
T16	58388	336	0	0
T17	5091	82	0	0
T19	0	3027	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1420681	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1420681	0	0
T1	440184	4177	0	0
T2	2227	35	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	94	0	0
T12	48340	342	0	0
T14	0	442	0	0
T15	65659	530	0	0
T16	58388	709	0	0
T17	5091	71	0	0
T19	0	3389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2865554	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2865554	0	0
T1	440184	4075	0	0
T2	2227	35	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	3	0	0
T11	5348	94	0	0
T12	48340	368	0	0
T14	0	442	0	0
T15	65659	605	0	0
T16	58388	308	0	0
T17	5091	71	0	0
T19	0	3032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1425721	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1425721	0	0
T1	440184	4642	0	0
T2	2227	29	0	0
T3	76273	2053	0	0
T4	110975	1242	0	0
T5	418	7	0	0
T11	5348	103	0	0
T12	48340	357	0	0
T15	65659	671	0	0
T16	58388	794	0	0
T17	5091	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2836115	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2836115	0	0
T1	440184	4650	0	0
T2	2227	29	0	0
T3	76273	1990	0	0
T4	110975	101313	0	0
T5	418	7	0	0
T11	5348	103	0	0
T12	48340	264	0	0
T15	65659	671	0	0
T16	58388	317	0	0
T17	5091	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	1412225	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	1412225	0	0
T1	440184	2435	0	0
T2	2227	39	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	8	0	0
T11	5348	86	0	0
T12	48340	363	0	0
T13	0	1227	0	0
T15	65659	782	0	0
T16	58388	808	0	0
T17	5091	94	0	0
T19	0	1976	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294037427	2696195	0	0
DepthKnown_A	294037427	293913696	0	0
RvalidKnown_A	294037427	293913696	0	0
WreadyKnown_A	294037427	293913696	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	2696195	0	0
T1	440184	2620	0	0
T2	2227	39	0	0
T3	76273	0	0	0
T4	110975	0	0	0
T5	418	8	0	0
T11	5348	86	0	0
T12	48340	268	0	0
T13	0	96081	0	0
T15	65659	648	0	0
T16	58388	316	0	0
T17	5091	94	0	0
T19	0	1405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294037427	293913696	0	0
T1	440184	440031	0	0
T2	2227	2190	0	0
T3	76273	76172	0	0
T4	110975	110968	0	0
T5	418	391	0	0
T11	5348	5307	0	0
T12	48340	48312	0	0
T15	65659	65645	0	0
T16	58388	58361	0	0
T17	5091	5022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0