Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1820611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

286743

1

T1

189

T2

5996

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	711974	1			T1	482		T2	14524		T3	45
values[0x0]	684008	1			T1	477		T2	14604		T3	58
values[0x1]	711372	1			T1	473		T2	14570		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1411649	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

695705

1

T1

478

T2

14300

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9057	1			T1	2		T2	196		T4	115
valid_sources[0x01]	8356	1			T1	6		T2	164		T4	22
valid_sources[0x02]	8226	1			T1	5		T2	187		T4	34
valid_sources[0x03]	8233	1			T1	1		T2	227		T4	28
valid_sources[0x04]	7751	1			T1	3		T2	199		T4	28
valid_sources[0x05]	7853	1			T1	5		T2	199		T4	27
valid_sources[0x06]	7613	1			T1	7		T2	204		T4	27
valid_sources[0x07]	8024	1			T1	6		T2	221		T3	4
valid_sources[0x08]	8145	1			T1	10		T2	217		T4	35
valid_sources[0x09]	8098	1			T2	135		T4	14		T20	12
valid_sources[0x0a]	7831	1			T1	3		T2	133		T3	1
valid_sources[0x0b]	8848	1			T1	4		T2	171		T4	80
valid_sources[0x0c]	7970	1			T1	5		T2	103		T4	49
valid_sources[0x0d]	8670	1			T1	7		T2	126		T4	40
valid_sources[0x0e]	7673	1			T1	7		T2	149		T4	85
valid_sources[0x0f]	8583	1			T1	6		T2	138		T3	1
valid_sources[0x10]	8297	1			T1	5		T2	198		T4	15
valid_sources[0x11]	8599	1			T1	3		T2	130		T3	1
valid_sources[0x12]	8360	1			T1	3		T2	145		T4	68
valid_sources[0x13]	8500	1			T1	5		T2	134		T4	43
valid_sources[0x14]	8929	1			T1	9		T2	195		T4	41
valid_sources[0x15]	8700	1			T1	6		T2	163		T4	55
valid_sources[0x16]	8014	1			T1	3		T2	146		T3	2
valid_sources[0x17]	7875	1			T1	12		T2	231		T4	28
valid_sources[0x18]	7412	1			T1	10		T2	200		T4	54
valid_sources[0x19]	7297	1			T1	4		T2	195		T4	93
valid_sources[0x1a]	7572	1			T1	11		T2	234		T4	27
valid_sources[0x1b]	8404	1			T1	5		T2	157		T4	76
valid_sources[0x1c]	9018	1			T1	8		T2	103		T4	49
valid_sources[0x1d]	8080	1			T1	5		T2	246		T4	37
valid_sources[0x1e]	8109	1			T1	7		T2	133		T4	25
valid_sources[0x1f]	7852	1			T1	5		T2	173		T3	11
valid_sources[0x20]	7213	1			T1	5		T2	234		T3	1
valid_sources[0x21]	8009	1			T1	8		T2	146		T4	28
valid_sources[0x22]	8569	1			T1	7		T2	150		T4	14
valid_sources[0x23]	7891	1			T1	8		T2	168		T4	34
valid_sources[0x24]	8460	1			T1	3		T2	148		T4	103
valid_sources[0x25]	8305	1			T1	3		T2	186		T4	39
valid_sources[0x26]	8024	1			T1	8		T2	165		T3	4
valid_sources[0x27]	8779	1			T1	2		T2	142		T3	2
valid_sources[0x28]	9477	1			T1	1		T2	167		T4	18
valid_sources[0x29]	8630	1			T1	4		T2	172		T4	75
valid_sources[0x2a]	9079	1			T1	9		T2	227		T4	28
valid_sources[0x2b]	8538	1			T1	2		T2	333		T4	50
valid_sources[0x2c]	7670	1			T1	5		T2	177		T4	20
valid_sources[0x2d]	8833	1			T1	9		T2	226		T4	78
valid_sources[0x2e]	7340	1			T1	3		T2	159		T4	59
valid_sources[0x2f]	8510	1			T1	11		T2	101		T3	3
valid_sources[0x30]	8155	1			T1	6		T2	235		T3	1
valid_sources[0x31]	7902	1			T1	4		T2	143		T4	30
valid_sources[0x32]	7978	1			T1	5		T2	179		T4	24
valid_sources[0x33]	8094	1			T1	9		T2	102		T4	35
valid_sources[0x34]	8149	1			T1	2		T2	215		T4	75
valid_sources[0x35]	8694	1			T1	8		T2	200		T4	36
valid_sources[0x36]	8540	1			T1	7		T2	141		T4	32
valid_sources[0x37]	8905	1			T1	3		T2	224		T20	11
valid_sources[0x38]	8028	1			T1	4		T2	170		T4	40
valid_sources[0x39]	9047	1			T1	5		T2	168		T4	30
valid_sources[0x3a]	8093	1			T1	6		T2	177		T4	36
valid_sources[0x3b]	8432	1			T1	5		T2	194		T4	52
valid_sources[0x3c]	8520	1			T1	8		T2	203		T4	87
valid_sources[0x3d]	8372	1			T1	3		T2	186		T3	1
valid_sources[0x3e]	8373	1			T1	12		T2	187		T4	88
valid_sources[0x3f]	9110	1			T1	4		T2	173		T4	17
valid_sources[0x40]	9313	1			T1	7		T2	264		T4	88
valid_sources[0x41]	8431	1			T1	14		T2	192		T4	42
valid_sources[0x42]	8047	1			T1	6		T2	124		T3	1
valid_sources[0x43]	8851	1			T1	9		T2	154		T3	3
valid_sources[0x44]	9558	1			T1	3		T2	205		T4	42
valid_sources[0x45]	8209	1			T1	6		T2	175		T4	77
valid_sources[0x46]	8818	1			T1	4		T2	166		T4	58
valid_sources[0x47]	8047	1			T1	9		T2	234		T3	1
valid_sources[0x48]	8389	1			T1	4		T2	215		T4	40
valid_sources[0x49]	7906	1			T1	6		T2	123		T4	17
valid_sources[0x4a]	8714	1			T1	8		T2	188		T4	162
valid_sources[0x4b]	7785	1			T1	3		T2	164		T4	7
valid_sources[0x4c]	7529	1			T1	6		T2	121		T4	34
valid_sources[0x4d]	8656	1			T1	6		T2	196		T3	1
valid_sources[0x4e]	8207	1			T1	3		T2	135		T4	56
valid_sources[0x4f]	8629	1			T1	7		T2	158		T4	38
valid_sources[0x50]	8316	1			T1	4		T2	130		T4	13
valid_sources[0x51]	7786	1			T1	5		T2	160		T4	68
valid_sources[0x52]	7720	1			T1	8		T2	154		T4	28
valid_sources[0x53]	7760	1			T1	5		T2	158		T4	7
valid_sources[0x54]	6887	1			T1	3		T2	160		T4	52
valid_sources[0x55]	8727	1			T1	7		T2	149		T4	65
valid_sources[0x56]	8653	1			T1	2		T2	220		T3	1
valid_sources[0x57]	7378	1			T1	7		T2	200		T4	27
valid_sources[0x58]	8107	1			T1	5		T2	238		T4	78
valid_sources[0x59]	8380	1			T1	3		T2	181		T4	93
valid_sources[0x5a]	7387	1			T1	4		T2	282		T4	49
valid_sources[0x5b]	8501	1			T1	5		T2	193		T4	97
valid_sources[0x5c]	7688	1			T1	7		T2	125		T3	2
valid_sources[0x5d]	8163	1			T1	3		T2	137		T4	5
valid_sources[0x5e]	10010	1			T1	3		T2	205		T4	35
valid_sources[0x5f]	7795	1			T1	1		T2	185		T4	106
valid_sources[0x60]	7664	1			T1	8		T2	198		T4	35
valid_sources[0x61]	9106	1			T1	4		T2	139		T4	42
valid_sources[0x62]	8096	1			T1	5		T2	144		T4	14
valid_sources[0x63]	7863	1			T1	7		T2	149		T3	5
valid_sources[0x64]	8824	1			T1	6		T2	124		T4	2
valid_sources[0x65]	8357	1			T1	14		T2	95		T3	3
valid_sources[0x66]	8596	1			T1	2		T2	187		T4	108
valid_sources[0x67]	7936	1			T1	8		T2	163		T3	2
valid_sources[0x68]	7823	1			T1	3		T2	144		T3	1
valid_sources[0x69]	8031	1			T1	2		T2	157		T4	27
valid_sources[0x6a]	8558	1			T1	6		T2	180		T4	49
valid_sources[0x6b]	7278	1			T1	6		T2	97		T4	90
valid_sources[0x6c]	7887	1			T1	4		T2	180		T4	34
valid_sources[0x6d]	8148	1			T1	5		T2	238		T4	73
valid_sources[0x6e]	8093	1			T1	10		T2	233		T4	54
valid_sources[0x6f]	7693	1			T1	7		T2	118		T4	81
valid_sources[0x70]	7111	1			T1	4		T2	154		T4	73
valid_sources[0x71]	7330	1			T1	7		T2	163		T4	13
valid_sources[0x72]	7689	1			T1	4		T2	137		T4	51
valid_sources[0x73]	7491	1			T1	1		T2	129		T4	45
valid_sources[0x74]	8044	1			T1	9		T2	107		T4	63
valid_sources[0x75]	8473	1			T1	4		T2	198		T4	39
valid_sources[0x76]	8794	1			T1	4		T2	107		T4	60
valid_sources[0x77]	8243	1			T1	3		T2	191		T3	4
valid_sources[0x78]	7741	1			T1	2		T2	116		T4	40
valid_sources[0x79]	8689	1			T1	5		T2	161		T4	40
valid_sources[0x7a]	7876	1			T1	1		T2	164		T4	31
valid_sources[0x7b]	7697	1			T1	4		T2	128		T4	29
valid_sources[0x7c]	7977	1			T1	6		T2	97		T4	54
valid_sources[0x7d]	7732	1			T1	5		T2	263		T4	16
valid_sources[0x7e]	8149	1			T1	4		T2	222		T4	73
valid_sources[0x7f]	9044	1			T1	1		T2	152		T4	58
valid_sources[0x80]	8066	1			T1	6		T2	169		T4	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30086

1

T1

22

T2

617

T3

2

values[0x0]

all_enables

biggest_size

226784

1

T1

149

T2

4789

T3

25

values[0x1]

all_enables

biggest_size

29873

1

T1

18

T2

590

T3

2