Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	338305315	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338305315	0	0
T1	7509600	1220351	0	0
T2	52610656	1046004	0	0
T3	228760	5527	0	0
T4	1340864	56628	0	0
T18	47936	1132	0	0
T19	148008	4818	0	0
T20	319368	13831	0	0
T21	44016	807	0	0
T22	1571304	66614	0	0
T23	12257168	219341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7509600	7509544	0	0
T2	52610656	52532648	0	0
T3	228760	226352	0	0
T4	1340864	1295224	0	0
T18	47936	45472	0	0
T19	148008	146384	0	0
T20	319368	317352	0	0
T21	44016	41048	0	0
T22	1571304	1546048	0	0
T23	12257168	12252856	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7509600	7509544	0	0
T2	52610656	52532648	0	0
T3	228760	226352	0	0
T4	1340864	1295224	0	0
T18	47936	45472	0	0
T19	148008	146384	0	0
T20	319368	317352	0	0
T21	44016	41048	0	0
T22	1571304	1546048	0	0
T23	12257168	12252856	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7509600	7509544	0	0
T2	52610656	52532648	0	0
T3	228760	226352	0	0
T4	1340864	1295224	0	0
T18	47936	45472	0	0
T19	148008	146384	0	0
T20	319368	317352	0	0
T21	44016	41048	0	0
T22	1571304	1546048	0	0
T23	12257168	12252856	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	124535879	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	124535879	0	0
T1	134100	132096	0	0
T2	939476	439994	0	0
T3	4085	2454	0	0
T4	23944	20930	0	0
T18	856	557	0	0
T19	2643	1207	0	0
T20	5703	5387	0	0
T21	786	315	0	0
T22	28059	25880	0	0
T23	218878	213025	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	88298370	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	88298370	0	0
T1	134100	541608	0	0
T2	939476	147030	0	0
T3	4085	1063	0	0
T4	23944	12894	0	0
T18	856	283	0	0
T19	2643	1207	0	0
T20	5703	2816	0	0
T21	786	164	0	0
T22	28059	13841	0	0
T23	218878	2272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1397958	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1397958	0	0
T1	134100	199	0	0
T2	939476	7651	0	0
T3	4085	4	0	0
T4	23944	237	0	0
T18	856	1	0	0
T19	2643	38	0	0
T20	5703	87	0	0
T21	786	5	0	0
T22	28059	458	0	0
T23	218878	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3219187	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3219187	0	0
T1	134100	15338	0	0
T2	939476	3271	0	0
T3	4085	29	0	0
T4	23944	237	0	0
T18	856	1	0	0
T19	2643	38	0	0
T20	5703	87	0	0
T21	786	5	0	0
T22	28059	458	0	0
T23	218878	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1431718	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1431718	0	0
T1	134100	184	0	0
T2	939476	11327	0	0
T3	4085	63	0	0
T4	23944	512	0	0
T18	856	8	0	0
T19	2643	46	0	0
T20	5703	114	0	0
T21	786	11	0	0
T22	28059	473	0	0
T23	218878	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3774013	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3774013	0	0
T1	134100	24831	0	0
T2	939476	5004	0	0
T3	4085	56	0	0
T4	23944	512	0	0
T18	856	8	0	0
T19	2643	46	0	0
T20	5703	114	0	0
T21	786	11	0	0
T22	28059	473	0	0
T23	218878	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1452532	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1452532	0	0
T1	134100	221	0	0
T2	939476	9548	0	0
T3	4085	50	0	0
T4	23944	512	0	0
T18	856	9	0	0
T19	2643	52	0	0
T20	5703	93	0	0
T21	786	3	0	0
T22	28059	423	0	0
T23	218878	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3066181	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3066181	0	0
T1	134100	22469	0	0
T2	939476	4291	0	0
T3	4085	46	0	0
T4	23944	512	0	0
T18	856	9	0	0
T19	2643	52	0	0
T20	5703	93	0	0
T21	786	3	0	0
T22	28059	423	0	0
T23	218878	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1410009	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1410009	0	0
T1	134100	201	0	0
T2	939476	13285	0	0
T3	4085	54	0	0
T4	23944	264	0	0
T18	856	6	0	0
T19	2643	54	0	0
T20	5703	112	0	0
T21	786	7	0	0
T22	28059	455	0	0
T23	218878	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3387717	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3387717	0	0
T1	134100	18295	0	0
T2	939476	6569	0	0
T3	4085	31	0	0
T4	23944	264	0	0
T18	856	6	0	0
T19	2643	54	0	0
T20	5703	112	0	0
T21	786	7	0	0
T22	28059	455	0	0
T23	218878	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1418289	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1418289	0	0
T1	134100	194	0	0
T2	939476	14929	0	0
T3	4085	11	0	0
T4	23944	764	0	0
T18	856	6	0	0
T19	2643	47	0	0
T20	5703	112	0	0
T21	786	6	0	0
T22	28059	486	0	0
T23	218878	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2766461	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2766461	0	0
T1	134100	14222	0	0
T2	939476	6350	0	0
T3	4085	22	0	0
T4	23944	764	0	0
T18	856	6	0	0
T19	2643	47	0	0
T20	5703	112	0	0
T21	786	6	0	0
T22	28059	486	0	0
T23	218878	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1431116	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1431116	0	0
T1	134100	329	0	0
T2	939476	8668	0	0
T3	4085	39	0	0
T4	23944	256	0	0
T18	856	4	0	0
T19	2643	40	0	0
T20	5703	101	0	0
T21	786	3	0	0
T22	28059	739	0	0
T23	218878	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2727880	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2727880	0	0
T1	134100	22941	0	0
T2	939476	3995	0	0
T3	4085	28	0	0
T4	23944	256	0	0
T18	856	4	0	0
T19	2643	40	0	0
T20	5703	101	0	0
T21	786	3	0	0
T22	28059	739	0	0
T23	218878	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1440959	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1440959	0	0
T1	134100	198	0	0
T2	939476	12341	0	0
T3	4085	65	0	0
T4	23944	600	0	0
T18	856	2	0	0
T19	2643	39	0	0
T20	5703	112	0	0
T21	786	6	0	0
T22	28059	446	0	0
T23	218878	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3399729	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3399729	0	0
T1	134100	18244	0	0
T2	939476	5638	0	0
T3	4085	39	0	0
T4	23944	599	0	0
T18	856	2	0	0
T19	2643	39	0	0
T20	5703	112	0	0
T21	786	6	0	0
T22	28059	446	0	0
T23	218878	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1429636	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1429636	0	0
T1	134100	208	0	0
T2	939476	16057	0	0
T3	4085	40	0	0
T4	23944	496	0	0
T18	856	5	0	0
T19	2643	55	0	0
T20	5703	97	0	0
T21	786	8	0	0
T22	28059	487	0	0
T23	218878	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2873033	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2873033	0	0
T1	134100	24225	0	0
T2	939476	6799	0	0
T3	4085	31	0	0
T4	23944	496	0	0
T18	856	5	0	0
T19	2643	55	0	0
T20	5703	97	0	0
T21	786	8	0	0
T22	28059	487	0	0
T23	218878	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1432370	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1432370	0	0
T1	134100	235	0	0
T2	939476	15125	0	0
T3	4085	22	0	0
T4	23944	254	0	0
T18	856	5	0	0
T19	2643	39	0	0
T20	5703	97	0	0
T21	786	8	0	0
T22	28059	672	0	0
T23	218878	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3058669	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3058669	0	0
T1	134100	20467	0	0
T2	939476	6511	0	0
T3	4085	34	0	0
T4	23944	254	0	0
T18	856	5	0	0
T19	2643	39	0	0
T20	5703	97	0	0
T21	786	8	0	0
T22	28059	672	0	0
T23	218878	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1467489	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1467489	0	0
T1	134100	208	0	0
T2	939476	12380	0	0
T3	4085	24	0	0
T4	23944	272	0	0
T18	856	4	0	0
T19	2643	43	0	0
T20	5703	122	0	0
T21	786	8	0	0
T22	28059	451	0	0
T23	218878	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3907035	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3907035	0	0
T1	134100	17031	0	0
T2	939476	5216	0	0
T3	4085	55	0	0
T4	23944	272	0	0
T18	856	4	0	0
T19	2643	43	0	0
T20	5703	122	0	0
T21	786	8	0	0
T22	28059	451	0	0
T23	218878	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1406467	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1406467	0	0
T1	134100	229	0	0
T2	939476	6524	0	0
T3	4085	14	0	0
T4	23944	221	0	0
T18	856	7	0	0
T19	2643	35	0	0
T20	5703	104	0	0
T21	786	5	0	0
T22	28059	464	0	0
T23	218878	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3846779	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3846779	0	0
T1	134100	17100	0	0
T2	939476	2757	0	0
T3	4085	43	0	0
T4	23944	221	0	0
T18	856	7	0	0
T19	2643	35	0	0
T20	5703	104	0	0
T21	786	5	0	0
T22	28059	463	0	0
T23	218878	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1425790	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1425790	0	0
T1	134100	207	0	0
T2	939476	7697	0	0
T3	4085	14	0	0
T4	23944	259	0	0
T18	856	4	0	0
T19	2643	45	0	0
T20	5703	107	0	0
T21	786	6	0	0
T22	28059	808	0	0
T23	218878	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2775761	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2775761	0	0
T1	134100	18399	0	0
T2	939476	3834	0	0
T3	4085	35	0	0
T4	23944	258	0	0
T18	856	4	0	0
T19	2643	45	0	0
T20	5703	107	0	0
T21	786	6	0	0
T22	28059	808	0	0
T23	218878	287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1382402	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1382402	0	0
T1	134100	244	0	0
T2	939476	7942	0	0
T3	4085	38	0	0
T4	23944	252	0	0
T18	856	5	0	0
T19	2643	45	0	0
T20	5703	100	0	0
T21	786	5	0	0
T22	28059	452	0	0
T23	218878	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3785036	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3785036	0	0
T1	134100	21983	0	0
T2	939476	3485	0	0
T3	4085	67	0	0
T4	23944	252	0	0
T18	856	5	0	0
T19	2643	45	0	0
T20	5703	100	0	0
T21	786	5	0	0
T22	28059	452	0	0
T23	218878	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1405642	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1405642	0	0
T1	134100	201	0	0
T2	939476	8271	0	0
T3	4085	58	0	0
T4	23944	253	0	0
T18	856	3	0	0
T19	2643	37	0	0
T20	5703	94	0	0
T21	786	2	0	0
T22	28059	691	0	0
T23	218878	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2562192	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2562192	0	0
T1	134100	20833	0	0
T2	939476	3845	0	0
T3	4085	53	0	0
T4	23944	253	0	0
T18	856	3	0	0
T19	2643	37	0	0
T20	5703	94	0	0
T21	786	2	0	0
T22	28059	691	0	0
T23	218878	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1401736	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1401736	0	0
T1	134100	235	0	0
T2	939476	11020	0	0
T3	4085	50	0	0
T4	23944	247	0	0
T18	856	7	0	0
T19	2643	35	0	0
T20	5703	107	0	0
T21	786	6	0	0
T22	28059	466	0	0
T23	218878	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3008764	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3008764	0	0
T1	134100	20493	0	0
T2	939476	5339	0	0
T3	4085	28	0	0
T4	23944	247	0	0
T18	856	7	0	0
T19	2643	35	0	0
T20	5703	107	0	0
T21	786	6	0	0
T22	28059	465	0	0
T23	218878	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1409026	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1409026	0	0
T1	134100	251	0	0
T2	939476	15471	0	0
T3	4085	27	0	0
T4	23944	662	0	0
T18	856	6	0	0
T19	2643	44	0	0
T20	5703	120	0	0
T21	786	10	0	0
T22	28059	424	0	0
T23	218878	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2558991	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2558991	0	0
T1	134100	23002	0	0
T2	939476	6559	0	0
T3	4085	23	0	0
T4	23944	662	0	0
T18	856	6	0	0
T19	2643	44	0	0
T20	5703	120	0	0
T21	786	10	0	0
T22	28059	423	0	0
T23	218878	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1422378	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1422378	0	0
T1	134100	201	0	0
T2	939476	12634	0	0
T3	4085	40	0	0
T4	23944	508	0	0
T18	856	4	0	0
T19	2643	45	0	0
T20	5703	119	0	0
T21	786	6	0	0
T22	28059	462	0	0
T23	218878	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3636571	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3636571	0	0
T1	134100	18054	0	0
T2	939476	5404	0	0
T3	4085	54	0	0
T4	23944	508	0	0
T18	856	4	0	0
T19	2643	45	0	0
T20	5703	119	0	0
T21	786	6	0	0
T22	28059	462	0	0
T23	218878	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1399246	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1399246	0	0
T1	134100	160	0	0
T2	939476	14979	0	0
T3	4085	24	0	0
T4	23944	260	0	0
T18	856	7	0	0
T19	2643	50	0	0
T20	5703	87	0	0
T21	786	4	0	0
T22	28059	471	0	0
T23	218878	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3473867	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3473867	0	0
T1	134100	13280	0	0
T2	939476	8364	0	0
T3	4085	9	0	0
T4	23944	259	0	0
T18	856	7	0	0
T19	2643	50	0	0
T20	5703	87	0	0
T21	786	4	0	0
T22	28059	471	0	0
T23	218878	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1421151	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1421151	0	0
T1	134100	226	0	0
T2	939476	10674	0	0
T3	4085	10	0	0
T4	23944	734	0	0
T18	856	11	0	0
T19	2643	58	0	0
T20	5703	105	0	0
T21	786	9	0	0
T22	28059	418	0	0
T23	218878	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3960943	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3960943	0	0
T1	134100	17453	0	0
T2	939476	5202	0	0
T3	4085	20	0	0
T4	23944	734	0	0
T18	856	11	0	0
T19	2643	58	0	0
T20	5703	105	0	0
T21	786	9	0	0
T22	28059	418	0	0
T23	218878	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1402297	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1402297	0	0
T1	134100	263	0	0
T2	939476	8930	0	0
T3	4085	25	0	0
T4	23944	513	0	0
T18	856	7	0	0
T19	2643	45	0	0
T20	5703	105	0	0
T21	786	7	0	0
T22	28059	436	0	0
T23	218878	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2734242	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2734242	0	0
T1	134100	22357	0	0
T2	939476	4010	0	0
T3	4085	18	0	0
T4	23944	513	0	0
T18	856	7	0	0
T19	2643	45	0	0
T20	5703	105	0	0
T21	786	7	0	0
T22	28059	436	0	0
T23	218878	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1405155	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1405155	0	0
T1	134100	291	0	0
T2	939476	18909	0	0
T3	4085	52	0	0
T4	23944	259	0	0
T18	856	6	0	0
T19	2643	52	0	0
T20	5703	85	0	0
T21	786	1	0	0
T22	28059	473	0	0
T23	218878	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3495683	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3495683	0	0
T1	134100	23735	0	0
T2	939476	8214	0	0
T3	4085	90	0	0
T4	23944	259	0	0
T18	856	6	0	0
T19	2643	52	0	0
T20	5703	85	0	0
T21	786	1	0	0
T22	28059	473	0	0
T23	218878	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1374552	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1374552	0	0
T1	134100	218	0	0
T2	939476	12491	0	0
T3	4085	59	0	0
T4	23944	261	0	0
T18	856	6	0	0
T19	2643	28	0	0
T20	5703	100	0	0
T21	786	6	0	0
T22	28059	488	0	0
T23	218878	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3300187	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3300187	0	0
T1	134100	16720	0	0
T2	939476	5874	0	0
T3	4085	37	0	0
T4	23944	261	0	0
T18	856	6	0	0
T19	2643	28	0	0
T20	5703	100	0	0
T21	786	6	0	0
T22	28059	488	0	0
T23	218878	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1398408	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1398408	0	0
T1	134100	257	0	0
T2	939476	9130	0	0
T3	4085	72	0	0
T4	23944	769	0	0
T18	856	3	0	0
T19	2643	49	0	0
T20	5703	100	0	0
T21	786	5	0	0
T22	28059	457	0	0
T23	218878	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2901457	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2901457	0	0
T1	134100	24188	0	0
T2	939476	4645	0	0
T3	4085	79	0	0
T4	23944	769	0	0
T18	856	3	0	0
T19	2643	49	0	0
T20	5703	100	0	0
T21	786	5	0	0
T22	28059	457	0	0
T23	218878	766	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1429596	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1429596	0	0
T1	134100	275	0	0
T2	939476	10381	0	0
T3	4085	37	0	0
T4	23944	266	0	0
T18	856	8	0	0
T19	2643	40	0	0
T20	5703	120	0	0
T21	786	8	0	0
T22	28059	482	0	0
T23	218878	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3327234	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3327234	0	0
T1	134100	23302	0	0
T2	939476	4413	0	0
T3	4085	33	0	0
T4	23944	266	0	0
T18	856	8	0	0
T19	2643	40	0	0
T20	5703	120	0	0
T21	786	8	0	0
T22	28059	482	0	0
T23	218878	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1419412	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1419412	0	0
T1	134100	288	0	0
T2	939476	17080	0	0
T3	4085	18	0	0
T4	23944	985	0	0
T18	856	5	0	0
T19	2643	55	0	0
T20	5703	98	0	0
T21	786	4	0	0
T22	28059	444	0	0
T23	218878	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3521781	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3521781	0	0
T1	134100	23094	0	0
T2	939476	8610	0	0
T3	4085	20	0	0
T4	23944	984	0	0
T18	856	5	0	0
T19	2643	55	0	0
T20	5703	98	0	0
T21	786	4	0	0
T22	28059	444	0	0
T23	218878	825	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1349918	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1349918	0	0
T1	134100	184	0	0
T2	939476	10403	0	0
T3	4085	18	0	0
T4	23944	282	0	0
T18	856	4	0	0
T19	2643	43	0	0
T20	5703	111	0	0
T21	786	10	0	0
T22	28059	479	0	0
T23	218878	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	2595354	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	2595354	0	0
T1	134100	17103	0	0
T2	939476	5477	0	0
T3	4085	28	0	0
T4	23944	282	0	0
T18	856	4	0	0
T19	2643	43	0	0
T20	5703	111	0	0
T21	786	10	0	0
T22	28059	479	0	0
T23	218878	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	1420950	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	1420950	0	0
T1	134100	240	0	0
T2	939476	10723	0	0
T3	4085	19	0	0
T4	23944	506	0	0
T18	856	3	0	0
T19	2643	43	0	0
T20	5703	105	0	0
T21	786	5	0	0
T22	28059	443	0	0
T23	218878	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298610837	3620117	0	0
DepthKnown_A	298610837	298495463	0	0
RvalidKnown_A	298610837	298495463	0	0
WreadyKnown_A	298610837	298495463	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	3620117	0	0
T1	134100	21341	0	0
T2	939476	4734	0	0
T3	4085	55	0	0
T4	23944	506	0	0
T18	856	3	0	0
T19	2643	43	0	0
T20	5703	105	0	0
T21	786	5	0	0
T22	28059	443	0	0
T23	218878	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298610837	298495463	0	0
T1	134100	134099	0	0
T2	939476	938083	0	0
T3	4085	4042	0	0
T4	23944	23129	0	0
T18	856	812	0	0
T19	2643	2614	0	0
T20	5703	5667	0	0
T21	786	733	0	0
T22	28059	27608	0	0
T23	218878	218801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0