Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1586197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249426

1

T1

17

T2

358

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	620403	1			T1	63		T2	715		T3	22
values[0x0]	592734	1			T1	55		T2	772		T3	31
values[0x1]	622486	1			T1	55		T2	833		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1230045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

605578

1

T1

45

T2

812

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7469	1			T1	2		T2	11		T4	5
valid_sources[0x01]	6660	1			T2	9		T4	6		T18	1
valid_sources[0x02]	7273	1			T1	1		T2	18		T4	11
valid_sources[0x03]	7614	1			T1	1		T2	9		T15	9
valid_sources[0x04]	7402	1			T2	10		T4	5		T15	5
valid_sources[0x05]	7906	1			T1	2		T2	5		T18	1
valid_sources[0x06]	7837	1			T1	1		T2	5		T15	6
valid_sources[0x07]	8746	1			T2	11		T15	6		T22	10
valid_sources[0x08]	7419	1			T2	5		T4	6		T15	1
valid_sources[0x09]	6550	1			T1	2		T2	15		T4	3
valid_sources[0x0a]	7389	1			T2	5		T4	3		T15	3
valid_sources[0x0b]	7318	1			T1	2		T2	13		T3	1
valid_sources[0x0c]	7044	1			T1	2		T2	7		T15	6
valid_sources[0x0d]	6736	1			T1	1		T2	11		T15	2
valid_sources[0x0e]	7120	1			T2	7		T18	1		T15	7
valid_sources[0x0f]	6975	1			T1	3		T2	11		T4	4
valid_sources[0x10]	6351	1			T2	7		T4	1		T18	1
valid_sources[0x11]	7303	1			T2	5		T4	3		T15	8
valid_sources[0x12]	6706	1			T2	5		T3	1		T15	3
valid_sources[0x13]	6633	1			T2	11		T15	7		T21	2
valid_sources[0x14]	8385	1			T2	10		T3	3		T18	2
valid_sources[0x15]	6379	1			T2	8		T17	1		T22	3
valid_sources[0x16]	7716	1			T2	14		T4	2		T18	1
valid_sources[0x17]	7411	1			T1	2		T2	9		T4	2
valid_sources[0x18]	7779	1			T2	9		T4	1		T15	11
valid_sources[0x19]	6989	1			T1	1		T2	17		T4	1
valid_sources[0x1a]	6815	1			T1	2		T2	8		T4	3
valid_sources[0x1b]	8369	1			T2	3		T15	1		T20	3
valid_sources[0x1c]	8161	1			T2	9		T4	5		T15	3
valid_sources[0x1d]	7269	1			T1	3		T2	9		T18	3
valid_sources[0x1e]	7572	1			T1	4		T2	12		T3	8
valid_sources[0x1f]	6415	1			T1	1		T2	10		T4	1
valid_sources[0x20]	6536	1			T2	7		T4	4		T15	2
valid_sources[0x21]	6819	1			T2	13		T18	1		T15	12
valid_sources[0x22]	7701	1			T1	1		T2	4		T3	3
valid_sources[0x23]	6778	1			T1	1		T2	9		T4	6
valid_sources[0x24]	6853	1			T1	1		T2	5		T15	4
valid_sources[0x25]	6546	1			T1	1		T2	12		T15	5
valid_sources[0x26]	7319	1			T2	5		T4	1		T18	1
valid_sources[0x27]	6472	1			T2	16		T4	6		T15	3
valid_sources[0x28]	6912	1			T2	11		T15	7		T21	3
valid_sources[0x29]	6784	1			T1	1		T2	4		T4	5
valid_sources[0x2a]	6899	1			T2	8		T15	11		T19	17
valid_sources[0x2b]	7498	1			T2	11		T4	4		T15	3
valid_sources[0x2c]	7357	1			T1	1		T2	6		T18	1
valid_sources[0x2d]	6668	1			T2	13		T4	4		T15	5
valid_sources[0x2e]	7130	1			T2	2		T4	1		T15	3
valid_sources[0x2f]	7177	1			T1	2		T2	6		T4	2
valid_sources[0x30]	6694	1			T1	1		T2	6		T4	7
valid_sources[0x31]	7369	1			T2	7		T4	2		T18	1
valid_sources[0x32]	6480	1			T2	11		T15	5		T21	1
valid_sources[0x33]	6961	1			T1	1		T2	4		T3	2
valid_sources[0x34]	6762	1			T1	1		T2	6		T4	3
valid_sources[0x35]	7031	1			T2	13		T4	1		T18	1
valid_sources[0x36]	6496	1			T1	1		T2	6		T18	1
valid_sources[0x37]	6679	1			T2	6		T4	7		T15	1
valid_sources[0x38]	6756	1			T2	8		T18	1		T15	13
valid_sources[0x39]	7852	1			T1	1		T2	11		T4	3
valid_sources[0x3a]	7337	1			T1	1		T2	10		T15	3
valid_sources[0x3b]	8050	1			T2	10		T4	4		T18	2
valid_sources[0x3c]	7092	1			T1	1		T2	5		T18	1
valid_sources[0x3d]	7766	1			T1	1		T2	7		T18	1
valid_sources[0x3e]	7353	1			T2	10		T15	6		T19	13
valid_sources[0x3f]	6548	1			T2	3		T15	11		T20	27
valid_sources[0x40]	9170	1			T1	2		T2	6		T15	9
valid_sources[0x41]	7091	1			T2	10		T21	2		T22	6
valid_sources[0x42]	6759	1			T2	5		T15	1		T20	12
valid_sources[0x43]	6936	1			T1	1		T2	3		T4	1
valid_sources[0x44]	6313	1			T1	1		T2	18		T4	1
valid_sources[0x45]	7349	1			T2	11		T3	2		T15	8
valid_sources[0x46]	7076	1			T2	5		T4	2		T15	1
valid_sources[0x47]	6825	1			T1	1		T2	2		T18	2
valid_sources[0x48]	6795	1			T2	9		T15	7		T19	20
valid_sources[0x49]	6501	1			T2	16		T4	3		T15	6
valid_sources[0x4a]	7849	1			T2	10		T18	1		T15	4
valid_sources[0x4b]	7005	1			T1	3		T2	4		T4	1
valid_sources[0x4c]	6337	1			T1	1		T2	8		T4	12
valid_sources[0x4d]	7769	1			T2	14		T4	7		T15	1
valid_sources[0x4e]	7583	1			T2	12		T4	4		T15	2
valid_sources[0x4f]	7650	1			T2	7		T4	3		T15	4
valid_sources[0x50]	7049	1			T2	2		T4	2		T15	3
valid_sources[0x51]	7034	1			T1	1		T2	11		T4	4
valid_sources[0x52]	6903	1			T1	1		T2	7		T18	1
valid_sources[0x53]	8002	1			T1	1		T2	5		T4	10
valid_sources[0x54]	8168	1			T1	2		T2	8		T4	3
valid_sources[0x55]	7512	1			T1	1		T2	6		T4	5
valid_sources[0x56]	7237	1			T1	1		T2	4		T18	1
valid_sources[0x57]	7268	1			T1	2		T2	7		T4	1
valid_sources[0x58]	6995	1			T2	9		T4	2		T15	3
valid_sources[0x59]	6749	1			T2	12		T18	2		T15	6
valid_sources[0x5a]	7367	1			T2	8		T15	4		T16	1
valid_sources[0x5b]	7444	1			T1	1		T2	2		T15	4
valid_sources[0x5c]	6552	1			T2	2		T3	2		T15	6
valid_sources[0x5d]	7935	1			T1	1		T2	11		T18	2
valid_sources[0x5e]	6677	1			T1	1		T2	13		T18	1
valid_sources[0x5f]	6910	1			T1	2		T2	9		T4	1
valid_sources[0x60]	6872	1			T1	1		T2	10		T4	3
valid_sources[0x61]	7509	1			T1	1		T2	10		T22	9
valid_sources[0x62]	7266	1			T2	5		T4	3		T15	2
valid_sources[0x63]	6631	1			T2	7		T4	8		T15	4
valid_sources[0x64]	6851	1			T1	2		T2	11		T15	1
valid_sources[0x65]	6994	1			T1	3		T2	9		T4	2
valid_sources[0x66]	6727	1			T2	10		T15	5		T20	6
valid_sources[0x67]	7027	1			T2	9		T18	1		T15	4
valid_sources[0x68]	7439	1			T1	2		T2	7		T15	3
valid_sources[0x69]	6612	1			T2	9		T4	2		T15	15
valid_sources[0x6a]	6704	1			T2	17		T3	1		T4	1
valid_sources[0x6b]	7192	1			T1	1		T2	9		T3	1
valid_sources[0x6c]	6928	1			T2	5		T18	1		T15	6
valid_sources[0x6d]	7454	1			T2	7		T4	3		T15	5
valid_sources[0x6e]	7136	1			T1	1		T2	12		T4	8
valid_sources[0x6f]	6772	1			T2	11		T15	3		T21	1
valid_sources[0x70]	8050	1			T2	9		T15	8		T22	6
valid_sources[0x71]	6618	1			T2	7		T4	6		T18	1
valid_sources[0x72]	7121	1			T1	2		T2	6		T4	3
valid_sources[0x73]	7946	1			T2	8		T18	1		T15	4
valid_sources[0x74]	7088	1			T1	1		T2	16		T15	1
valid_sources[0x75]	6575	1			T1	2		T2	8		T15	2
valid_sources[0x76]	7126	1			T1	2		T2	9		T4	4
valid_sources[0x77]	7031	1			T2	13		T15	10		T19	19
valid_sources[0x78]	7325	1			T2	20		T4	3		T15	4
valid_sources[0x79]	7182	1			T1	2		T2	12		T4	10
valid_sources[0x7a]	6695	1			T1	2		T2	9		T18	1
valid_sources[0x7b]	7039	1			T1	1		T2	8		T15	6
valid_sources[0x7c]	6521	1			T2	13		T18	1		T15	9
valid_sources[0x7d]	6325	1			T1	1		T2	7		T4	1
valid_sources[0x7e]	8042	1			T1	1		T2	9		T18	1
valid_sources[0x7f]	6935	1			T1	1		T2	11		T4	3
valid_sources[0x80]	7157	1			T2	12		T4	6		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26224

1

T2

29

T4

8

T18

3

values[0x0]

all_enables

biggest_size

196966

1

T1

17

T2

293

T3

12

values[0x1]

all_enables

biggest_size

26236

1

T2

36

T3

1

T4

9