Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	353692784	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353692784	0	0
T1	10409616	183218	0	0
T2	2649864	61368	0	0
T3	4473280	133855	0	0
T4	16043272	285044	0	0
T15	1314992	30158	0	0
T16	1329832	29406	0	0
T17	161112	5621	0	0
T18	244048	8314	0	0
T19	1046808	15012	0	0
T20	3616760	84664	0	0
T21	0	34501	0	0
T22	0	1442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10409616	10406704	0	0
T2	2649864	2646560	0	0
T3	4473280	4472664	0	0
T4	16043272	16040304	0	0
T15	1314992	1313648	0	0
T16	1329832	1329048	0	0
T17	161112	160664	0	0
T18	244048	242256	0	0
T19	1046808	1044176	0	0
T20	3616760	3613624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10409616	10406704	0	0
T2	2649864	2646560	0	0
T3	4473280	4472664	0	0
T4	16043272	16040304	0	0
T15	1314992	1313648	0	0
T16	1329832	1329048	0	0
T17	161112	160664	0	0
T18	244048	242256	0	0
T19	1046808	1044176	0	0
T20	3616760	3613624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10409616	10406704	0	0
T2	2649864	2646560	0	0
T3	4473280	4472664	0	0
T4	16043272	16040304	0	0
T15	1314992	1313648	0	0
T16	1329832	1329048	0	0
T17	161112	160664	0	0
T18	244048	242256	0	0
T19	1046808	1044176	0	0
T20	3616760	3613624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	128383993	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	128383993	0	0
T1	185886	88649	0	0
T2	47319	23337	0	0
T3	79880	77713	0	0
T4	286487	280677	0	0
T15	23482	10354	0	0
T16	23747	12311	0	0
T17	2877	2781	0	0
T18	4358	4136	0	0
T19	18693	3719	0	0
T20	64585	33820	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	94686066	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	94686066	0	0
T1	185886	17819	0	0
T2	47319	20244	0	0
T3	79880	27923	0	0
T4	286487	945	0	0
T15	23482	4725	0	0
T16	23747	5386	0	0
T17	2877	1418	0	0
T18	4358	2112	0	0
T19	18693	3789	0	0
T20	64585	16661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1356295	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1356295	0	0
T1	185886	1625	0	0
T2	47319	388	0	0
T3	79880	13	0	0
T4	286487	84	0	0
T15	23482	0	0	0
T16	23747	359	0	0
T17	2877	18	0	0
T18	4358	37	0	0
T19	18693	143	0	0
T20	64585	499	0	0
T21	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3363095	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3363095	0	0
T1	185886	354	0	0
T2	47319	255	0	0
T3	79880	1443	0	0
T4	286487	17	0	0
T15	23482	0	0	0
T16	23747	177	0	0
T17	2877	18	0	0
T18	4358	37	0	0
T19	18693	119	0	0
T20	64585	538	0	0
T21	0	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1399525	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1399525	0	0
T1	185886	1883	0	0
T2	47319	318	0	0
T3	79880	27	0	0
T4	286487	103	0	0
T15	23482	0	0	0
T16	23747	287	0	0
T17	2877	30	0	0
T18	4358	43	0	0
T19	18693	121	0	0
T20	64585	563	0	0
T21	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3328749	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3328749	0	0
T1	185886	698	0	0
T2	47319	292	0	0
T3	79880	1425	0	0
T4	286487	22	0	0
T15	23482	0	0	0
T16	23747	282	0	0
T17	2877	30	0	0
T18	4358	43	0	0
T19	18693	176	0	0
T20	64585	587	0	0
T21	0	704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1323127	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1323127	0	0
T1	185886	3888	0	0
T2	47319	291	0	0
T3	79880	0	0	0
T4	286487	104	0	0
T15	23482	0	0	0
T16	23747	160	0	0
T17	2877	29	0	0
T18	4358	26	0	0
T19	18693	78	0	0
T20	64585	709	0	0
T21	0	26	0	0
T22	0	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3252844	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3252844	0	0
T1	185886	803	0	0
T2	47319	221	0	0
T3	79880	0	0	0
T4	286487	22	0	0
T15	23482	0	0	0
T16	23747	155	0	0
T17	2877	29	0	0
T18	4358	26	0	0
T19	18693	101	0	0
T20	64585	677	0	0
T21	0	2419	0	0
T22	0	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1413044	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1413044	0	0
T1	185886	1964	0	0
T2	47319	363	0	0
T3	79880	6	0	0
T4	286487	62	0	0
T15	23482	2235	0	0
T16	23747	235	0	0
T17	2877	21	0	0
T18	4358	37	0	0
T19	18693	155	0	0
T20	64585	755	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	4002061	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	4002061	0	0
T1	185886	504	0	0
T2	47319	342	0	0
T3	79880	913	0	0
T4	286487	16	0	0
T15	23482	934	0	0
T16	23747	141	0	0
T17	2877	21	0	0
T18	4358	37	0	0
T19	18693	182	0	0
T20	64585	650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1377986	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1377986	0	0
T1	185886	1638	0	0
T2	47319	353	0	0
T3	79880	16	0	0
T4	286487	91	0	0
T15	23482	0	0	0
T16	23747	176	0	0
T17	2877	24	0	0
T18	4358	45	0	0
T19	18693	91	0	0
T20	64585	556	0	0
T21	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3292621	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3292621	0	0
T1	185886	140	0	0
T2	47319	351	0	0
T3	79880	1356	0	0
T4	286487	21	0	0
T15	23482	0	0	0
T16	23747	177	0	0
T17	2877	24	0	0
T18	4358	45	0	0
T19	18693	117	0	0
T20	64585	564	0	0
T21	0	1190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1342983	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1342983	0	0
T1	185886	885	0	0
T2	47319	336	0	0
T3	79880	26	0	0
T4	286487	70	0	0
T15	23482	0	0	0
T16	23747	309	0	0
T17	2877	30	0	0
T18	4358	31	0	0
T19	18693	139	0	0
T20	64585	775	0	0
T21	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2854443	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2854443	0	0
T1	185886	920	0	0
T2	47319	344	0	0
T3	79880	655	0	0
T4	286487	20	0	0
T15	23482	0	0	0
T16	23747	225	0	0
T17	2877	30	0	0
T18	4358	31	0	0
T19	18693	165	0	0
T20	64585	677	0	0
T21	0	1162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1343842	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1343842	0	0
T1	185886	2168	0	0
T2	47319	378	0	0
T3	79880	14	0	0
T4	286487	77	0	0
T15	23482	1670	0	0
T16	23747	196	0	0
T17	2877	31	0	0
T18	4358	58	0	0
T19	18693	133	0	0
T20	64585	546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	4121912	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	4121912	0	0
T1	185886	1290	0	0
T2	47319	418	0	0
T3	79880	1226	0	0
T4	286487	18	0	0
T15	23482	863	0	0
T16	23747	181	0	0
T17	2877	31	0	0
T18	4358	58	0	0
T19	18693	150	0	0
T20	64585	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1384616	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1384616	0	0
T1	185886	1191	0	0
T2	47319	365	0	0
T3	79880	12	0	0
T4	286487	162	0	0
T15	23482	0	0	0
T16	23747	182	0	0
T17	2877	23	0	0
T18	4358	42	0	0
T19	18693	230	0	0
T20	64585	568	0	0
T21	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3267643	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3267643	0	0
T1	185886	700	0	0
T2	47319	434	0	0
T3	79880	1421	0	0
T4	286487	33	0	0
T15	23482	0	0	0
T16	23747	200	0	0
T17	2877	23	0	0
T18	4358	42	0	0
T19	18693	197	0	0
T20	64585	577	0	0
T21	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1403313	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1403313	0	0
T1	185886	2246	0	0
T2	47319	324	0	0
T3	79880	0	0	0
T4	286487	117	0	0
T15	23482	0	0	0
T16	23747	179	0	0
T17	2877	31	0	0
T18	4358	34	0	0
T19	18693	96	0	0
T20	64585	503	0	0
T21	0	20	0	0
T22	0	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	4123587	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	4123587	0	0
T1	185886	1006	0	0
T2	47319	313	0	0
T3	79880	0	0	0
T4	286487	32	0	0
T15	23482	0	0	0
T16	23747	187	0	0
T17	2877	31	0	0
T18	4358	34	0	0
T19	18693	121	0	0
T20	64585	559	0	0
T21	0	2176	0	0
T22	0	308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1373876	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1373876	0	0
T1	185886	3797	0	0
T2	47319	337	0	0
T3	79880	13	0	0
T4	286487	132	0	0
T15	23482	0	0	0
T16	23747	319	0	0
T17	2877	22	0	0
T18	4358	32	0	0
T19	18693	110	0	0
T20	64585	661	0	0
T21	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3890875	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3890875	0	0
T1	185886	705	0	0
T2	47319	263	0	0
T3	79880	787	0	0
T4	286487	27	0	0
T15	23482	0	0	0
T16	23747	266	0	0
T17	2877	22	0	0
T18	4358	32	0	0
T19	18693	99	0	0
T20	64585	631	0	0
T21	0	1394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1353354	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1353354	0	0
T1	185886	2784	0	0
T2	47319	315	0	0
T3	79880	17	0	0
T4	286487	75	0	0
T15	23482	0	0	0
T16	23747	229	0	0
T17	2877	27	0	0
T18	4358	28	0	0
T19	18693	94	0	0
T20	64585	552	0	0
T21	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3662067	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3662067	0	0
T1	185886	798	0	0
T2	47319	329	0	0
T3	79880	1123	0	0
T4	286487	19	0	0
T15	23482	0	0	0
T16	23747	196	0	0
T17	2877	27	0	0
T18	4358	28	0	0
T19	18693	91	0	0
T20	64585	575	0	0
T21	0	2652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1384753	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1384753	0	0
T1	185886	2579	0	0
T2	47319	271	0	0
T3	79880	9	0	0
T4	286487	68	0	0
T15	23482	0	0	0
T16	23747	223	0	0
T17	2877	24	0	0
T18	4358	49	0	0
T19	18693	157	0	0
T20	64585	680	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3912994	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3912994	0	0
T1	185886	1240	0	0
T2	47319	272	0	0
T3	79880	1598	0	0
T4	286487	27	0	0
T15	23482	0	0	0
T16	23747	179	0	0
T17	2877	24	0	0
T18	4358	49	0	0
T19	18693	177	0	0
T20	64585	631	0	0
T21	0	949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1379404	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1379404	0	0
T1	185886	1535	0	0
T2	47319	313	0	0
T3	79880	7	0	0
T4	286487	93	0	0
T15	23482	0	0	0
T16	23747	216	0	0
T17	2877	32	0	0
T18	4358	40	0	0
T19	18693	149	0	0
T20	64585	666	0	0
T21	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3513096	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3513096	0	0
T1	185886	579	0	0
T2	47319	348	0	0
T3	79880	721	0	0
T4	286487	24	0	0
T15	23482	0	0	0
T16	23747	198	0	0
T17	2877	32	0	0
T18	4358	40	0	0
T19	18693	154	0	0
T20	64585	681	0	0
T21	0	1676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1353281	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1353281	0	0
T1	185886	1582	0	0
T2	47319	308	0	0
T3	79880	10	0	0
T4	286487	113	0	0
T15	23482	0	0	0
T16	23747	278	0	0
T17	2877	28	0	0
T18	4358	37	0	0
T19	18693	106	0	0
T20	64585	618	0	0
T21	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2806562	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2806562	0	0
T1	185886	337	0	0
T2	47319	346	0	0
T3	79880	1492	0	0
T4	286487	24	0	0
T15	23482	0	0	0
T16	23747	265	0	0
T17	2877	28	0	0
T18	4358	37	0	0
T19	18693	145	0	0
T20	64585	603	0	0
T21	0	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1383480	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1383480	0	0
T1	185886	3790	0	0
T2	47319	288	0	0
T3	79880	11	0	0
T4	286487	101	0	0
T15	23482	1944	0	0
T16	23747	245	0	0
T17	2877	28	0	0
T18	4358	43	0	0
T19	18693	234	0	0
T20	64585	647	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3094919	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3094919	0	0
T1	185886	795	0	0
T2	47319	341	0	0
T3	79880	738	0	0
T4	286487	22	0	0
T15	23482	827	0	0
T16	23747	181	0	0
T17	2877	28	0	0
T18	4358	43	0	0
T19	18693	193	0	0
T20	64585	635	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1393753	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1393753	0	0
T1	185886	1246	0	0
T2	47319	293	0	0
T3	79880	5	0	0
T4	286487	66	0	0
T15	23482	2289	0	0
T16	23747	252	0	0
T17	2877	18	0	0
T18	4358	35	0	0
T19	18693	72	0	0
T20	64585	794	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2889031	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2889031	0	0
T1	185886	267	0	0
T2	47319	286	0	0
T3	79880	148	0	0
T4	286487	16	0	0
T15	23482	1118	0	0
T16	23747	246	0	0
T17	2877	18	0	0
T18	4358	35	0	0
T19	18693	58	0	0
T20	64585	664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1299364	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1299364	0	0
T1	185886	1760	0	0
T2	47319	260	0	0
T3	79880	18	0	0
T4	286487	73	0	0
T15	23482	0	0	0
T16	23747	249	0	0
T17	2877	25	0	0
T18	4358	45	0	0
T19	18693	189	0	0
T20	64585	702	0	0
T21	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3331118	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3331118	0	0
T1	185886	427	0	0
T2	47319	343	0	0
T3	79880	1349	0	0
T4	286487	222	0	0
T15	23482	0	0	0
T16	23747	209	0	0
T17	2877	25	0	0
T18	4358	45	0	0
T19	18693	158	0	0
T20	64585	667	0	0
T21	0	1766	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1366435	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1366435	0	0
T1	185886	1111	0	0
T2	47319	349	0	0
T3	79880	1	0	0
T4	286487	127	0	0
T15	23482	0	0	0
T16	23747	195	0	0
T17	2877	28	0	0
T18	4358	30	0	0
T19	18693	137	0	0
T20	64585	682	0	0
T21	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3985961	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3985961	0	0
T1	185886	3	0	0
T2	47319	303	0	0
T3	79880	777	0	0
T4	286487	28	0	0
T15	23482	0	0	0
T16	23747	139	0	0
T17	2877	28	0	0
T18	4358	30	0	0
T19	18693	151	0	0
T20	64585	550	0	0
T21	0	1890	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1377431	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1377431	0	0
T1	185886	2785	0	0
T2	47319	290	0	0
T3	79880	17	0	0
T4	286487	55	0	0
T15	23482	0	0	0
T16	23747	384	0	0
T17	2877	27	0	0
T18	4358	42	0	0
T19	18693	134	0	0
T20	64585	707	0	0
T21	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3491044	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3491044	0	0
T1	185886	467	0	0
T2	47319	356	0	0
T3	79880	2353	0	0
T4	286487	13	0	0
T15	23482	0	0	0
T16	23747	322	0	0
T17	2877	27	0	0
T18	4358	42	0	0
T19	18693	181	0	0
T20	64585	555	0	0
T21	0	2151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1360455	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1360455	0	0
T1	185886	2285	0	0
T2	47319	415	0	0
T3	79880	2	0	0
T4	286487	80	0	0
T15	23482	0	0	0
T16	23747	176	0	0
T17	2877	36	0	0
T18	4358	39	0	0
T19	18693	148	0	0
T20	64585	767	0	0
T21	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2686271	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2686271	0	0
T1	185886	182	0	0
T2	47319	387	0	0
T3	79880	324	0	0
T4	286487	22	0	0
T15	23482	0	0	0
T16	23747	250	0	0
T17	2877	36	0	0
T18	4358	39	0	0
T19	18693	111	0	0
T20	64585	628	0	0
T21	0	1392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1371712	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1371712	0	0
T1	185886	1184	0	0
T2	47319	298	0	0
T3	79880	12	0	0
T4	286487	59	0	0
T15	23482	0	0	0
T16	23747	260	0	0
T17	2877	21	0	0
T18	4358	38	0	0
T19	18693	74	0	0
T20	64585	520	0	0
T21	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2994857	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2994857	0	0
T1	185886	559	0	0
T2	47319	371	0	0
T3	79880	1183	0	0
T4	286487	16	0	0
T15	23482	0	0	0
T16	23747	225	0	0
T17	2877	21	0	0
T18	4358	38	0	0
T19	18693	75	0	0
T20	64585	544	0	0
T21	0	610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1375692	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1375692	0	0
T1	185886	2863	0	0
T2	47319	310	0	0
T3	79880	16	0	0
T4	286487	63	0	0
T15	23482	2216	0	0
T16	23747	174	0	0
T17	2877	24	0	0
T18	4358	43	0	0
T19	18693	164	0	0
T20	64585	714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3197173	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3197173	0	0
T1	185886	964	0	0
T2	47319	244	0	0
T3	79880	2241	0	0
T4	286487	20	0	0
T15	23482	983	0	0
T16	23747	211	0	0
T17	2877	24	0	0
T18	4358	43	0	0
T19	18693	181	0	0
T20	64585	719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1318165	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1318165	0	0
T1	185886	2853	0	0
T2	47319	345	0	0
T3	79880	13	0	0
T4	286487	122	0	0
T15	23482	0	0	0
T16	23747	139	0	0
T17	2877	23	0	0
T18	4358	32	0	0
T19	18693	133	0	0
T20	64585	715	0	0
T21	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3475140	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3475140	0	0
T1	185886	1076	0	0
T2	47319	280	0	0
T3	79880	1378	0	0
T4	286487	28	0	0
T15	23482	0	0	0
T16	23747	98	0	0
T17	2877	23	0	0
T18	4358	32	0	0
T19	18693	139	0	0
T20	64585	806	0	0
T21	0	3478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1416808	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1416808	0	0
T1	185886	891	0	0
T2	47319	335	0	0
T3	79880	6	0	0
T4	286487	74	0	0
T15	23482	0	0	0
T16	23747	195	0	0
T17	2877	30	0	0
T18	4358	36	0	0
T19	18693	151	0	0
T20	64585	686	0	0
T21	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	5178303	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	5178303	0	0
T1	185886	256	0	0
T2	47319	339	0	0
T3	79880	353	0	0
T4	286487	169	0	0
T15	23482	0	0	0
T16	23747	163	0	0
T17	2877	30	0	0
T18	4358	36	0	0
T19	18693	148	0	0
T20	64585	580	0	0
T21	0	4079	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1349844	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1349844	0	0
T1	185886	2476	0	0
T2	47319	334	0	0
T3	79880	8	0	0
T4	286487	69	0	0
T15	23482	0	0	0
T16	23747	117	0	0
T17	2877	26	0	0
T18	4358	38	0	0
T19	18693	126	0	0
T20	64585	604	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3270426	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3270426	0	0
T1	185886	1050	0	0
T2	47319	332	0	0
T3	79880	1237	0	0
T4	286487	18	0	0
T15	23482	0	0	0
T16	23747	142	0	0
T17	2877	26	0	0
T18	4358	38	0	0
T19	18693	102	0	0
T20	64585	563	0	0
T21	0	605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1393461	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1393461	0	0
T1	185886	1623	0	0
T2	47319	451	0	0
T3	79880	6	0	0
T4	286487	129	0	0
T15	23482	0	0	0
T16	23747	316	0	0
T17	2877	29	0	0
T18	4358	44	0	0
T19	18693	219	0	0
T20	64585	649	0	0
T21	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	3699991	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	3699991	0	0
T1	185886	904	0	0
T2	47319	464	0	0
T3	79880	756	0	0
T4	286487	27	0	0
T15	23482	0	0	0
T16	23747	157	0	0
T17	2877	29	0	0
T18	4358	44	0	0
T19	18693	187	0	0
T20	64585	633	0	0
T21	0	1727	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	1353967	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	1353967	0	0
T1	185886	4299	0	0
T2	47319	297	0	0
T3	79880	11	0	0
T4	286487	108	0	0
T15	23482	0	0	0
T16	23747	273	0	0
T17	2877	26	0	0
T18	4358	29	0	0
T19	18693	134	0	0
T20	64585	691	0	0
T21	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316720928	2985976	0	0
DepthKnown_A	316720928	316605741	0	0
RvalidKnown_A	316720928	316605741	0	0
WreadyKnown_A	316720928	316605741	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	2985976	0	0
T1	185886	795	0	0
T2	47319	288	0	0
T3	79880	926	0	0
T4	286487	22	0	0
T15	23482	0	0	0
T16	23747	214	0	0
T17	2877	26	0	0
T18	4358	29	0	0
T19	18693	109	0	0
T20	64585	656	0	0
T21	0	1586	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316720928	316605741	0	0
T1	185886	185834	0	0
T2	47319	47260	0	0
T3	79880	79869	0	0
T4	286487	286434	0	0
T15	23482	23458	0	0
T16	23747	23733	0	0
T17	2877	2869	0	0
T18	4358	4326	0	0
T19	18693	18646	0	0
T20	64585	64529	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0