Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1765305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

278831

1

T1

30

T2

84

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	690662	1			T1	56		T2	351		T3	34
values[0x0]	663388	1			T1	70		T2	65		T3	33
values[0x1]	690086	1			T1	50		T2	383		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1368508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

675628

1

T1

65

T2

288

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8446	1			T2	1		T4	66		T15	19
valid_sources[0x01]	8315	1			T4	79		T15	5		T12	10
valid_sources[0x02]	7629	1			T2	1		T4	61		T15	13
valid_sources[0x03]	8330	1			T2	1		T4	31		T15	7
valid_sources[0x04]	7792	1			T2	6		T4	56		T15	15
valid_sources[0x05]	8422	1			T2	5		T4	45		T15	15
valid_sources[0x06]	7406	1			T2	7		T4	45		T15	11
valid_sources[0x07]	8987	1			T6	1		T4	44		T15	16
valid_sources[0x08]	7571	1			T2	2		T3	1		T6	2
valid_sources[0x09]	7421	1			T4	71		T15	8		T12	9
valid_sources[0x0a]	8548	1			T4	56		T15	10		T12	9
valid_sources[0x0b]	8484	1			T4	47		T15	21		T12	9
valid_sources[0x0c]	8227	1			T2	3		T4	75		T15	9
valid_sources[0x0d]	8531	1			T4	48		T15	20		T12	9
valid_sources[0x0e]	7191	1			T4	47		T15	17		T12	10
valid_sources[0x0f]	8247	1			T2	10		T3	1		T6	1
valid_sources[0x10]	7644	1			T2	25		T4	42		T15	21
valid_sources[0x11]	7220	1			T2	9		T4	62		T15	16
valid_sources[0x12]	7419	1			T2	8		T4	59		T15	8
valid_sources[0x13]	9096	1			T1	5		T2	6		T4	51
valid_sources[0x14]	8415	1			T4	81		T15	15		T12	9
valid_sources[0x15]	7534	1			T4	57		T15	10		T12	8
valid_sources[0x16]	7999	1			T2	13		T4	38		T15	2
valid_sources[0x17]	7283	1			T4	41		T15	11		T12	9
valid_sources[0x18]	8135	1			T4	56		T15	10		T12	9
valid_sources[0x19]	8105	1			T2	27		T4	77		T15	26
valid_sources[0x1a]	7631	1			T4	65		T15	14		T12	9
valid_sources[0x1b]	8310	1			T2	2		T6	1		T4	67
valid_sources[0x1c]	7226	1			T2	2		T4	72		T15	17
valid_sources[0x1d]	8929	1			T1	4		T2	56		T4	54
valid_sources[0x1e]	8226	1			T3	4		T6	1		T4	47
valid_sources[0x1f]	7958	1			T4	51		T15	12		T12	8
valid_sources[0x20]	8163	1			T1	13		T4	72		T15	15
valid_sources[0x21]	8036	1			T6	1		T4	45		T15	20
valid_sources[0x22]	7005	1			T2	1		T3	1		T4	40
valid_sources[0x23]	7350	1			T2	3		T4	45		T15	9
valid_sources[0x24]	8057	1			T4	60		T15	14		T12	7
valid_sources[0x25]	9088	1			T6	1		T4	28		T15	28
valid_sources[0x26]	7512	1			T4	53		T15	4		T12	9
valid_sources[0x27]	8174	1			T1	12		T2	6		T4	42
valid_sources[0x28]	8598	1			T1	4		T2	33		T6	1
valid_sources[0x29]	8675	1			T2	2		T4	38		T15	16
valid_sources[0x2a]	9174	1			T2	1		T3	1		T6	1
valid_sources[0x2b]	7827	1			T2	13		T4	44		T15	11
valid_sources[0x2c]	8044	1			T3	1		T4	41		T15	8
valid_sources[0x2d]	7239	1			T4	75		T15	9		T12	9
valid_sources[0x2e]	8200	1			T2	1		T4	51		T15	17
valid_sources[0x2f]	8177	1			T6	2		T4	54		T15	13
valid_sources[0x30]	7426	1			T1	3		T2	14		T4	59
valid_sources[0x31]	7753	1			T2	2		T3	2		T4	38
valid_sources[0x32]	7798	1			T1	1		T4	41		T15	15
valid_sources[0x33]	7660	1			T1	3		T2	14		T4	42
valid_sources[0x34]	8940	1			T2	1		T4	46		T15	10
valid_sources[0x35]	7448	1			T2	1		T4	53		T15	6
valid_sources[0x36]	7626	1			T6	1		T4	40		T15	2
valid_sources[0x37]	7228	1			T2	1		T4	55		T15	22
valid_sources[0x38]	8923	1			T3	2		T4	71		T15	10
valid_sources[0x39]	7730	1			T1	11		T4	36		T15	17
valid_sources[0x3a]	8581	1			T2	2		T4	50		T15	14
valid_sources[0x3b]	8870	1			T1	2		T2	1		T4	49
valid_sources[0x3c]	8478	1			T4	38		T15	13		T12	8
valid_sources[0x3d]	7754	1			T1	10		T2	3		T4	47
valid_sources[0x3e]	8764	1			T2	1		T4	41		T15	5
valid_sources[0x3f]	8500	1			T2	1		T4	45		T15	3
valid_sources[0x40]	8085	1			T4	48		T15	14		T12	9
valid_sources[0x41]	8999	1			T4	48		T15	5		T12	10
valid_sources[0x42]	8728	1			T2	1		T4	81		T15	25
valid_sources[0x43]	7609	1			T1	6		T4	62		T15	16
valid_sources[0x44]	9002	1			T4	46		T15	6		T12	10
valid_sources[0x45]	8097	1			T2	1		T6	1		T4	49
valid_sources[0x46]	8397	1			T2	6		T4	75		T15	21
valid_sources[0x47]	7579	1			T3	2		T4	57		T15	12
valid_sources[0x48]	8457	1			T2	1		T4	42		T15	10
valid_sources[0x49]	7861	1			T3	3		T4	41		T5	1
valid_sources[0x4a]	8368	1			T2	9		T4	49		T15	10
valid_sources[0x4b]	9219	1			T1	3		T2	3		T4	51
valid_sources[0x4c]	7808	1			T4	31		T15	7		T12	9
valid_sources[0x4d]	6983	1			T4	54		T15	12		T12	12
valid_sources[0x4e]	8969	1			T4	44		T15	8		T12	8
valid_sources[0x4f]	7451	1			T4	51		T15	4		T12	7
valid_sources[0x50]	8180	1			T4	47		T15	11		T12	8
valid_sources[0x51]	8129	1			T1	11		T4	53		T15	7
valid_sources[0x52]	7644	1			T4	64		T15	15		T12	10
valid_sources[0x53]	7781	1			T6	1		T4	53		T15	13
valid_sources[0x54]	8320	1			T2	6		T3	2		T4	44
valid_sources[0x55]	7649	1			T4	45		T5	8		T15	13
valid_sources[0x56]	8312	1			T2	22		T4	52		T15	7
valid_sources[0x57]	7852	1			T1	2		T2	1		T6	2
valid_sources[0x58]	7374	1			T2	4		T4	63		T15	14
valid_sources[0x59]	7167	1			T1	2		T6	1		T4	52
valid_sources[0x5a]	7358	1			T2	13		T4	67		T15	18
valid_sources[0x5b]	7911	1			T1	3		T2	7		T6	1
valid_sources[0x5c]	7207	1			T2	1		T3	2		T4	63
valid_sources[0x5d]	8166	1			T2	4		T4	64		T15	8
valid_sources[0x5e]	8367	1			T4	34		T15	11		T12	9
valid_sources[0x5f]	7951	1			T2	1		T4	42		T15	14
valid_sources[0x60]	7814	1			T2	1		T4	60		T15	11
valid_sources[0x61]	7620	1			T2	3		T3	2		T4	34
valid_sources[0x62]	7283	1			T4	48		T15	3		T12	9
valid_sources[0x63]	8074	1			T2	1		T4	64		T15	15
valid_sources[0x64]	7884	1			T4	50		T15	2		T12	9
valid_sources[0x65]	8873	1			T2	1		T4	58		T15	14
valid_sources[0x66]	7482	1			T2	2		T4	53		T15	4
valid_sources[0x67]	8415	1			T3	5		T4	47		T15	17
valid_sources[0x68]	7293	1			T4	42		T15	25		T12	9
valid_sources[0x69]	7769	1			T2	1		T4	38		T15	7
valid_sources[0x6a]	8372	1			T2	1		T4	58		T15	12
valid_sources[0x6b]	7280	1			T2	1		T4	55		T15	10
valid_sources[0x6c]	8096	1			T4	60		T15	16		T12	9
valid_sources[0x6d]	8145	1			T2	22		T4	104		T15	10
valid_sources[0x6e]	8146	1			T6	1		T4	35		T15	9
valid_sources[0x6f]	7453	1			T2	1		T4	104		T15	14
valid_sources[0x70]	7538	1			T4	47		T15	6		T12	8
valid_sources[0x71]	7768	1			T2	4		T4	51		T15	8
valid_sources[0x72]	7755	1			T4	56		T15	11		T12	9
valid_sources[0x73]	8936	1			T2	1		T4	68		T15	9
valid_sources[0x74]	7463	1			T3	2		T4	57		T5	21
valid_sources[0x75]	7565	1			T3	4		T4	42		T15	8
valid_sources[0x76]	7793	1			T2	3		T6	2		T4	40
valid_sources[0x77]	8297	1			T2	1		T6	1		T4	65
valid_sources[0x78]	8361	1			T2	4		T4	40		T15	21
valid_sources[0x79]	8342	1			T2	4		T4	39		T15	11
valid_sources[0x7a]	8639	1			T2	5		T4	34		T15	3
valid_sources[0x7b]	8359	1			T4	33		T15	8		T12	9
valid_sources[0x7c]	8007	1			T2	2		T4	60		T15	22
valid_sources[0x7d]	7256	1			T4	70		T15	12		T12	8
valid_sources[0x7e]	7690	1			T2	1		T4	40		T15	12
valid_sources[0x7f]	7831	1			T2	1		T3	6		T4	53
valid_sources[0x80]	7626	1			T1	1		T3	2		T4	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28972

1

T1

2

T2

26

T3

3

values[0x0]

all_enables

biggest_size

220601

1

T1

27

T2

30

T3

9

values[0x1]

all_enables

biggest_size

29258

1

T1

1

T2

28

T6

3