Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	356438610	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	356438610	0	0
T1	43680	862	0	0
T2	1471400	73406	0	0
T3	39816	544	0	0
T4	16760576	313745	0	0
T5	5300344	175801	0	0
T6	139384	5128	0	0
T12	11245416	1657967	0	0
T15	358736	15925	0	0
T16	30240	839	0	0
T17	9475088	310278	0	0
T18	0	294	0	0
T19	0	5845	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43680	40600	0	0
T2	1471400	1466192	0	0
T3	39816	36288	0	0
T4	16760576	16717848	0	0
T5	5300344	5297208	0	0
T6	139384	135464	0	0
T12	11245416	11245304	0	0
T15	358736	357000	0	0
T16	30240	28784	0	0
T17	9475088	9473800	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43680	40600	0	0
T2	1471400	1466192	0	0
T3	39816	36288	0	0
T4	16760576	16717848	0	0
T5	5300344	5297208	0	0
T6	139384	135464	0	0
T12	11245416	11245304	0	0
T15	358736	357000	0	0
T16	30240	28784	0	0
T17	9475088	9473800	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43680	40600	0	0
T2	1471400	1466192	0	0
T3	39816	36288	0	0
T4	16760576	16717848	0	0
T5	5300344	5297208	0	0
T6	139384	135464	0	0
T12	11245416	11245304	0	0
T15	358736	357000	0	0
T16	30240	28784	0	0
T17	9475088	9473800	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T12	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	127678529	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	127678529	0	0
T1	780	334	0	0
T2	26275	24021	0	0
T3	711	211	0	0
T4	299296	127390	0	0
T5	94649	92399	0	0
T6	2489	1996	0	0
T12	200811	11360	0	0
T15	6406	6188	0	0
T16	540	323	0	0
T17	169198	167667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	94411428	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	94411428	0	0
T1	780	176	0	0
T2	26275	16797	0	0
T3	711	111	0	0
T4	299296	48058	0	0
T5	94649	41441	0	0
T6	2489	1044	0	0
T12	200811	818256	0	0
T15	6406	3247	0	0
T16	540	172	0	0
T17	169198	70868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1558708	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1558708	0	0
T1	780	8	0	0
T2	26275	453	0	0
T3	711	3	0	0
T4	299296	5953	0	0
T5	94649	19	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	136	0	0
T16	540	4	0	0
T17	169198	46	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3711630	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3711630	0	0
T1	780	8	0	0
T2	26275	453	0	0
T3	711	3	0	0
T4	299296	2850	0	0
T5	94649	1342	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	136	0	0
T16	540	4	0	0
T17	169198	2466	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1588862	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1588862	0	0
T1	780	9	0	0
T2	26275	259	0	0
T3	711	8	0	0
T4	299296	6008	0	0
T5	94649	22	0	0
T6	2489	37	0	0
T12	200811	0	0	0
T15	6406	117	0	0
T16	540	8	0	0
T17	169198	30	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3258418	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3258418	0	0
T1	780	9	0	0
T2	26275	259	0	0
T3	711	8	0	0
T4	299296	2696	0	0
T5	94649	1059	0	0
T6	2489	37	0	0
T12	200811	0	0	0
T15	6406	117	0	0
T16	540	8	0	0
T17	169198	2876	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1536885	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1536885	0	0
T1	780	8	0	0
T2	26275	1070	0	0
T3	711	7	0	0
T4	299296	6180	0	0
T5	94649	33	0	0
T6	2489	46	0	0
T12	200811	0	0	0
T15	6406	124	0	0
T16	540	5	0	0
T17	169198	37	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2886816	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2886816	0	0
T1	780	8	0	0
T2	26275	1070	0	0
T3	711	7	0	0
T4	299296	2674	0	0
T5	94649	3755	0	0
T6	2489	46	0	0
T12	200811	0	0	0
T15	6406	124	0	0
T16	540	5	0	0
T17	169198	3034	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1530963	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1530963	0	0
T1	780	5	0	0
T2	26275	524	0	0
T3	711	5	0	0
T4	299296	3940	0	0
T5	94649	7	0	0
T6	2489	48	0	0
T12	200811	0	0	0
T15	6406	115	0	0
T16	540	6	0	0
T17	169198	29	0	0
T18	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3787035	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3787035	0	0
T1	780	5	0	0
T2	26275	524	0	0
T3	711	5	0	0
T4	299296	1928	0	0
T5	94649	778	0	0
T6	2489	48	0	0
T12	200811	0	0	0
T15	6406	115	0	0
T16	540	6	0	0
T17	169198	2449	0	0
T18	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1510903	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1510903	0	0
T1	780	5	0	0
T2	26275	238	0	0
T3	711	2	0	0
T4	299296	3798	0	0
T5	94649	26	0	0
T6	2489	30	0	0
T12	200811	0	0	0
T15	6406	107	0	0
T16	540	3	0	0
T17	169198	17	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3800977	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3800977	0	0
T1	780	5	0	0
T2	26275	238	0	0
T3	711	2	0	0
T4	299296	1901	0	0
T5	94649	1626	0	0
T6	2489	30	0	0
T12	200811	0	0	0
T15	6406	107	0	0
T16	540	3	0	0
T17	169198	1169	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1520163	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1520163	0	0
T1	780	7	0	0
T2	26275	233	0	0
T3	711	4	0	0
T4	299296	3707	0	0
T5	94649	3	0	0
T6	2489	58	0	0
T12	200811	0	0	0
T15	6406	111	0	0
T16	540	3	0	0
T17	169198	46	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3671637	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3671637	0	0
T1	780	7	0	0
T2	26275	233	0	0
T3	711	4	0	0
T4	299296	1864	0	0
T5	94649	598	0	0
T6	2489	58	0	0
T12	200811	0	0	0
T15	6406	111	0	0
T16	540	3	0	0
T17	169198	3361	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1526655	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1526655	0	0
T1	780	7	0	0
T2	26275	453	0	0
T3	711	5	0	0
T4	299296	2108	0	0
T5	94649	10	0	0
T6	2489	29	0	0
T12	200811	0	0	0
T15	6406	131	0	0
T16	540	10	0	0
T17	169198	48	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2712119	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2712119	0	0
T1	780	7	0	0
T2	26275	453	0	0
T3	711	5	0	0
T4	299296	1060	0	0
T5	94649	770	0	0
T6	2489	29	0	0
T12	200811	0	0	0
T15	6406	131	0	0
T16	540	10	0	0
T17	169198	4787	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1536447	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1536447	0	0
T1	780	6	0	0
T2	26275	1260	0	0
T3	711	4	0	0
T4	299296	3701	0	0
T5	94649	28	0	0
T6	2489	25	0	0
T12	200811	0	0	0
T15	6406	108	0	0
T16	540	4	0	0
T17	169198	39	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3646226	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3646226	0	0
T1	780	6	0	0
T2	26275	1260	0	0
T3	711	4	0	0
T4	299296	1780	0	0
T5	94649	3851	0	0
T6	2489	25	0	0
T12	200811	0	0	0
T15	6406	108	0	0
T16	540	4	0	0
T17	169198	4552	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1526815	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1526815	0	0
T1	780	7	0	0
T2	26275	258	0	0
T3	711	3	0	0
T4	299296	2569	0	0
T5	94649	27	0	0
T6	2489	44	0	0
T12	200811	1148	0	0
T15	6406	100	0	0
T16	540	3	0	0
T17	169198	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3607303	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3607303	0	0
T1	780	7	0	0
T2	26275	258	0	0
T3	711	3	0	0
T4	299296	1420	0	0
T5	94649	1820	0	0
T6	2489	44	0	0
T12	200811	86849	0	0
T15	6406	100	0	0
T16	540	3	0	0
T17	169198	1500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1591155	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1591155	0	0
T1	780	7	0	0
T2	26275	468	0	0
T3	711	2	0	0
T4	299296	1822	0	0
T5	94649	40	0	0
T6	2489	44	0	0
T12	200811	0	0	0
T15	6406	127	0	0
T16	540	10	0	0
T17	169198	31	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3628567	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3628567	0	0
T1	780	7	0	0
T2	26275	468	0	0
T3	711	2	0	0
T4	299296	1068	0	0
T5	94649	2746	0	0
T6	2489	44	0	0
T12	200811	0	0	0
T15	6406	127	0	0
T16	540	10	0	0
T17	169198	3212	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1558921	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1558921	0	0
T1	780	6	0	0
T2	26275	485	0	0
T3	711	1	0	0
T4	299296	3538	0	0
T5	94649	4	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	132	0	0
T16	540	3	0	0
T17	169198	23	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2966924	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2966924	0	0
T1	780	6	0	0
T2	26275	485	0	0
T3	711	1	0	0
T4	299296	1764	0	0
T5	94649	265	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	132	0	0
T16	540	3	0	0
T17	169198	1229	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1505018	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1505018	0	0
T1	780	3	0	0
T2	26275	736	0	0
T3	711	5	0	0
T4	299296	1940	0	0
T5	94649	12	0	0
T6	2489	41	0	0
T12	200811	0	0	0
T15	6406	128	0	0
T16	540	11	0	0
T17	169198	63	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3395530	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3395530	0	0
T1	780	3	0	0
T2	26275	736	0	0
T3	711	5	0	0
T4	299296	1090	0	0
T5	94649	871	0	0
T6	2489	41	0	0
T12	200811	0	0	0
T15	6406	128	0	0
T16	540	11	0	0
T17	169198	4985	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1482390	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1482390	0	0
T1	780	5	0	0
T2	26275	447	0	0
T3	711	2	0	0
T4	299296	1665	0	0
T5	94649	11	0	0
T6	2489	38	0	0
T12	200811	0	0	0
T15	6406	130	0	0
T16	540	3	0	0
T17	169198	20	0	0
T18	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2840560	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2840560	0	0
T1	780	5	0	0
T2	26275	447	0	0
T3	711	2	0	0
T4	299296	1054	0	0
T5	94649	880	0	0
T6	2489	38	0	0
T12	200811	0	0	0
T15	6406	130	0	0
T16	540	3	0	0
T17	169198	1095	0	0
T18	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1454746	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1454746	0	0
T1	780	8	0	0
T2	26275	426	0	0
T3	711	4	0	0
T4	299296	2006	0	0
T5	94649	32	0	0
T6	2489	29	0	0
T12	200811	0	0	0
T15	6406	97	0	0
T16	540	7	0	0
T17	169198	34	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2923450	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2923450	0	0
T1	780	8	0	0
T2	26275	426	0	0
T3	711	4	0	0
T4	299296	1065	0	0
T5	94649	2574	0	0
T6	2489	29	0	0
T12	200811	0	0	0
T15	6406	97	0	0
T16	540	7	0	0
T17	169198	1601	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1456963	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1456963	0	0
T1	780	7	0	0
T2	26275	486	0	0
T3	711	6	0	0
T4	299296	3847	0	0
T5	94649	28	0	0
T6	2489	37	0	0
T12	200811	1276	0	0
T15	6406	105	0	0
T16	540	9	0	0
T17	169198	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	4358119	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	4358119	0	0
T1	780	7	0	0
T2	26275	486	0	0
T3	711	6	0	0
T4	299296	1801	0	0
T5	94649	1899	0	0
T6	2489	37	0	0
T12	200811	105675	0	0
T15	6406	105	0	0
T16	540	9	0	0
T17	169198	2928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1535443	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1535443	0	0
T1	780	9	0	0
T2	26275	1245	0	0
T3	711	0	0	0
T4	299296	2049	0	0
T5	94649	21	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	111	0	0
T16	540	2	0	0
T17	169198	38	0	0
T18	0	5	0	0
T19	0	2205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3875298	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3875298	0	0
T1	780	9	0	0
T2	26275	1245	0	0
T3	711	0	0	0
T4	299296	1226	0	0
T5	94649	2025	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	111	0	0
T16	540	2	0	0
T17	169198	2965	0	0
T18	0	5	0	0
T19	0	983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1485127	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1485127	0	0
T1	780	3	0	0
T2	26275	238	0	0
T3	711	3	0	0
T4	299296	4133	0	0
T5	94649	23	0	0
T6	2489	33	0	0
T12	200811	1193	0	0
T15	6406	117	0	0
T16	540	8	0	0
T17	169198	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3042743	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3042743	0	0
T1	780	3	0	0
T2	26275	238	0	0
T3	711	3	0	0
T4	299296	2016	0	0
T5	94649	1868	0	0
T6	2489	33	0	0
T12	200811	86106	0	0
T15	6406	117	0	0
T16	540	8	0	0
T17	169198	2500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1517226	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1517226	0	0
T1	780	5	0	0
T2	26275	487	0	0
T3	711	4	0	0
T4	299296	5390	0	0
T5	94649	5	0	0
T6	2489	53	0	0
T12	200811	0	0	0
T15	6406	126	0	0
T16	540	8	0	0
T17	169198	48	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3751949	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3751949	0	0
T1	780	5	0	0
T2	26275	487	0	0
T3	711	4	0	0
T4	299296	2480	0	0
T5	94649	712	0	0
T6	2489	53	0	0
T12	200811	0	0	0
T15	6406	126	0	0
T16	540	8	0	0
T17	169198	4444	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1540884	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1540884	0	0
T1	780	4	0	0
T2	26275	1042	0	0
T3	711	6	0	0
T4	299296	2763	0	0
T5	94649	40	0	0
T6	2489	52	0	0
T12	200811	2365	0	0
T15	6406	93	0	0
T16	540	7	0	0
T17	169198	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2915690	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2915690	0	0
T1	780	4	0	0
T2	26275	1042	0	0
T3	711	6	0	0
T4	299296	1877	0	0
T5	94649	1493	0	0
T6	2489	52	0	0
T12	200811	178831	0	0
T15	6406	93	0	0
T16	540	7	0	0
T17	169198	2135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1455935	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1455935	0	0
T1	780	2	0	0
T2	26275	803	0	0
T3	711	7	0	0
T4	299296	3456	0	0
T5	94649	0	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	102	0	0
T16	540	4	0	0
T17	169198	22	0	0
T18	0	9	0	0
T19	0	1544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3302361	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3302361	0	0
T1	780	2	0	0
T2	26275	803	0	0
T3	711	7	0	0
T4	299296	1860	0	0
T5	94649	0	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	102	0	0
T16	540	4	0	0
T17	169198	1267	0	0
T18	0	9	0	0
T19	0	1113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1543934	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1543934	0	0
T1	780	5	0	0
T2	26275	515	0	0
T3	711	4	0	0
T4	299296	3128	0	0
T5	94649	17	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	128	0	0
T16	540	10	0	0
T17	169198	29	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	4272932	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	4272932	0	0
T1	780	5	0	0
T2	26275	515	0	0
T3	711	4	0	0
T4	299296	1622	0	0
T5	94649	1633	0	0
T6	2489	33	0	0
T12	200811	0	0	0
T15	6406	128	0	0
T16	540	10	0	0
T17	169198	2519	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1514854	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1514854	0	0
T1	780	8	0	0
T2	26275	470	0	0
T3	711	7	0	0
T4	299296	3505	0	0
T5	94649	17	0	0
T6	2489	31	0	0
T12	200811	0	0	0
T15	6406	132	0	0
T16	540	7	0	0
T17	169198	10	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3966039	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3966039	0	0
T1	780	8	0	0
T2	26275	470	0	0
T3	711	7	0	0
T4	299296	1790	0	0
T5	94649	1291	0	0
T6	2489	31	0	0
T12	200811	0	0	0
T15	6406	132	0	0
T16	540	7	0	0
T17	169198	1510	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1502241	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1502241	0	0
T1	780	4	0	0
T2	26275	1030	0	0
T3	711	1	0	0
T4	299296	3016	0	0
T5	94649	24	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	131	0	0
T16	540	9	0	0
T17	169198	24	0	0
T18	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3520245	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3520245	0	0
T1	780	4	0	0
T2	26275	1030	0	0
T3	711	1	0	0
T4	299296	1684	0	0
T5	94649	2147	0	0
T6	2489	40	0	0
T12	200811	0	0	0
T15	6406	131	0	0
T16	540	9	0	0
T17	169198	2378	0	0
T18	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1507371	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1507371	0	0
T1	780	10	0	0
T2	26275	986	0	0
T3	711	6	0	0
T4	299296	5122	0	0
T5	94649	23	0	0
T6	2489	42	0	0
T12	200811	1047	0	0
T15	6406	145	0	0
T16	540	10	0	0
T17	169198	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3394184	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3394184	0	0
T1	780	10	0	0
T2	26275	986	0	0
T3	711	6	0	0
T4	299296	2339	0	0
T5	94649	1545	0	0
T6	2489	42	0	0
T12	200811	82849	0	0
T15	6406	145	0	0
T16	540	10	0	0
T17	169198	2868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1511081	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1511081	0	0
T1	780	12	0	0
T2	26275	451	0	0
T3	711	5	0	0
T4	299296	2049	0	0
T5	94649	0	0	0
T6	2489	41	0	0
T12	200811	1354	0	0
T15	6406	138	0	0
T16	540	4	0	0
T17	169198	51	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3843964	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3843964	0	0
T1	780	12	0	0
T2	26275	451	0	0
T3	711	5	0	0
T4	299296	1209	0	0
T5	94649	0	0	0
T6	2489	41	0	0
T12	200811	99429	0	0
T15	6406	138	0	0
T16	540	4	0	0
T17	169198	3536	0	0
T18	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1476644	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1476644	0	0
T1	780	9	0	0
T2	26275	997	0	0
T3	711	4	0	0
T4	299296	1783	0	0
T5	94649	25	0	0
T6	2489	29	0	0
T12	200811	1065	0	0
T15	6406	125	0	0
T16	540	7	0	0
T17	169198	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	3335911	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	3335911	0	0
T1	780	9	0	0
T2	26275	997	0	0
T3	711	4	0	0
T4	299296	1177	0	0
T5	94649	992	0	0
T6	2489	29	0	0
T12	200811	80978	0	0
T15	6406	125	0	0
T16	540	7	0	0
T17	169198	2230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	1499724	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	1499724	0	0
T1	780	7	0	0
T2	26275	234	0	0
T3	711	3	0	0
T4	299296	2516	0	0
T5	94649	23	0	0
T6	2489	38	0	0
T12	200811	1280	0	0
T15	6406	129	0	0
T16	540	7	0	0
T17	169198	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	321284517	2955968	0	0
DepthKnown_A	321284517	321160738	0	0
RvalidKnown_A	321284517	321160738	0	0
WreadyKnown_A	321284517	321160738	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	2955968	0	0
T1	780	7	0	0
T2	26275	234	0	0
T3	711	3	0	0
T4	299296	1310	0	0
T5	94649	2901	0	0
T6	2489	38	0	0
T12	200811	96906	0	0
T15	6406	129	0	0
T16	540	7	0	0
T17	169198	1272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321284517	321160738	0	0
T1	780	725	0	0
T2	26275	26182	0	0
T3	711	648	0	0
T4	299296	298533	0	0
T5	94649	94593	0	0
T6	2489	2419	0	0
T12	200811	200809	0	0
T15	6406	6375	0	0
T16	540	514	0	0
T17	169198	169175	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0