Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1727652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

271747

1

T1

2265

T2

27

T3

191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	676278	1			T1	5652		T2	61		T3	473
values[0x0]	646503	1			T1	5559		T2	66		T3	500
values[0x1]	676618	1			T1	5568		T2	55		T3	501

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1338866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

660533

1

T1

5464

T2

58

T3

465

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7309	1			T1	82		T3	5		T4	6
valid_sources[0x01]	7755	1			T1	58		T3	6		T4	9
valid_sources[0x02]	7682	1			T1	68		T3	6		T4	4
valid_sources[0x03]	7560	1			T1	50		T3	5		T4	3
valid_sources[0x04]	7437	1			T1	62		T3	6		T4	1
valid_sources[0x05]	7539	1			T1	57		T3	5		T4	8
valid_sources[0x06]	7390	1			T1	64		T3	5		T4	14
valid_sources[0x07]	7002	1			T1	99		T3	5		T4	16
valid_sources[0x08]	7173	1			T1	45		T3	6		T4	9
valid_sources[0x09]	7470	1			T1	84		T3	6		T4	3
valid_sources[0x0a]	7657	1			T1	61		T3	6		T4	17
valid_sources[0x0b]	7491	1			T1	65		T3	6		T4	9
valid_sources[0x0c]	8882	1			T1	59		T3	5		T4	4
valid_sources[0x0d]	8836	1			T1	75		T3	5		T15	19
valid_sources[0x0e]	7919	1			T1	64		T3	6		T15	3
valid_sources[0x0f]	7487	1			T1	99		T3	6		T4	5
valid_sources[0x10]	7467	1			T1	109		T3	5		T4	20
valid_sources[0x11]	8021	1			T1	55		T3	6		T4	24
valid_sources[0x12]	7148	1			T1	55		T3	6		T4	1
valid_sources[0x13]	7614	1			T1	116		T3	5		T4	5
valid_sources[0x14]	7650	1			T1	74		T3	6		T15	8
valid_sources[0x15]	7035	1			T1	36		T3	6		T15	34
valid_sources[0x16]	8762	1			T1	48		T3	4		T4	4
valid_sources[0x17]	8321	1			T1	60		T3	5		T4	7
valid_sources[0x18]	7769	1			T1	47		T3	5		T4	3
valid_sources[0x19]	7830	1			T1	53		T3	6		T4	22
valid_sources[0x1a]	7602	1			T1	63		T3	7		T4	5
valid_sources[0x1b]	8914	1			T1	61		T3	6		T4	1
valid_sources[0x1c]	7691	1			T1	79		T3	6		T4	36
valid_sources[0x1d]	7240	1			T1	69		T3	6		T4	10
valid_sources[0x1e]	7600	1			T1	67		T3	7		T4	3
valid_sources[0x1f]	8070	1			T1	54		T3	6		T4	17
valid_sources[0x20]	7690	1			T1	68		T3	6		T4	4
valid_sources[0x21]	7771	1			T1	52		T3	6		T4	22
valid_sources[0x22]	7019	1			T1	51		T3	7		T4	14
valid_sources[0x23]	8976	1			T1	76		T3	7		T4	9
valid_sources[0x24]	6931	1			T1	57		T3	6		T4	2
valid_sources[0x25]	7112	1			T1	64		T3	6		T4	7
valid_sources[0x26]	7770	1			T1	69		T3	6		T4	15
valid_sources[0x27]	7694	1			T1	64		T3	6		T4	26
valid_sources[0x28]	7449	1			T1	35		T3	6		T4	1
valid_sources[0x29]	7348	1			T1	44		T3	5		T15	58
valid_sources[0x2a]	8547	1			T1	66		T3	6		T4	3
valid_sources[0x2b]	7560	1			T1	62		T3	5		T4	4
valid_sources[0x2c]	7343	1			T1	83		T3	5		T4	8
valid_sources[0x2d]	7604	1			T1	44		T3	6		T4	1
valid_sources[0x2e]	7331	1			T1	61		T3	8		T4	15
valid_sources[0x2f]	7464	1			T1	63		T3	6		T4	17
valid_sources[0x30]	7640	1			T1	56		T3	8		T4	8
valid_sources[0x31]	7882	1			T1	51		T3	6		T4	3
valid_sources[0x32]	7524	1			T1	60		T3	6		T4	1
valid_sources[0x33]	8482	1			T1	59		T3	6		T4	12
valid_sources[0x34]	8169	1			T1	75		T3	6		T4	11
valid_sources[0x35]	7010	1			T1	60		T3	6		T4	7
valid_sources[0x36]	7537	1			T1	52		T3	5		T4	1
valid_sources[0x37]	8645	1			T1	53		T3	7		T4	4
valid_sources[0x38]	7443	1			T1	86		T3	6		T15	25
valid_sources[0x39]	7686	1			T1	53		T3	5		T4	3
valid_sources[0x3a]	8258	1			T1	67		T3	6		T4	2
valid_sources[0x3b]	8401	1			T1	78		T3	6		T15	13
valid_sources[0x3c]	7588	1			T1	37		T3	5		T4	13
valid_sources[0x3d]	8080	1			T1	48		T3	6		T4	5
valid_sources[0x3e]	7243	1			T1	63		T3	4		T4	5
valid_sources[0x3f]	8612	1			T1	69		T3	5		T4	1
valid_sources[0x40]	7347	1			T1	47		T3	6		T4	2
valid_sources[0x41]	8236	1			T1	66		T3	6		T15	22
valid_sources[0x42]	8654	1			T1	73		T3	8		T4	28
valid_sources[0x43]	7937	1			T1	73		T3	6		T4	18
valid_sources[0x44]	7584	1			T1	71		T3	6		T4	6
valid_sources[0x45]	7886	1			T1	53		T3	6		T4	9
valid_sources[0x46]	7805	1			T1	48		T3	6		T4	28
valid_sources[0x47]	8331	1			T1	65		T3	6		T4	8
valid_sources[0x48]	7819	1			T1	75		T3	5		T4	22
valid_sources[0x49]	7835	1			T1	65		T3	6		T4	16
valid_sources[0x4a]	7986	1			T1	92		T3	5		T4	2
valid_sources[0x4b]	7933	1			T1	49		T3	6		T4	38
valid_sources[0x4c]	7571	1			T1	61		T3	6		T4	24
valid_sources[0x4d]	7177	1			T1	60		T3	7		T4	5
valid_sources[0x4e]	8390	1			T1	103		T3	5		T4	2
valid_sources[0x4f]	7702	1			T1	62		T3	4		T15	44
valid_sources[0x50]	8014	1			T1	92		T3	6		T4	4
valid_sources[0x51]	7670	1			T1	50		T3	6		T4	5
valid_sources[0x52]	7651	1			T1	48		T3	6		T15	17
valid_sources[0x53]	7568	1			T1	60		T3	5		T4	3
valid_sources[0x54]	7741	1			T1	77		T3	5		T15	7
valid_sources[0x55]	8230	1			T1	77		T3	6		T4	4
valid_sources[0x56]	9298	1			T1	41		T3	6		T4	11
valid_sources[0x57]	7741	1			T1	57		T3	6		T4	31
valid_sources[0x58]	7186	1			T1	64		T3	6		T4	5
valid_sources[0x59]	6914	1			T1	67		T3	5		T4	2
valid_sources[0x5a]	8263	1			T1	50		T3	6		T4	13
valid_sources[0x5b]	8590	1			T1	76		T3	6		T4	1
valid_sources[0x5c]	8223	1			T1	58		T3	6		T4	2
valid_sources[0x5d]	7262	1			T1	45		T3	5		T4	1
valid_sources[0x5e]	7850	1			T1	138		T3	7		T4	8
valid_sources[0x5f]	7520	1			T1	51		T3	4		T4	6
valid_sources[0x60]	7973	1			T1	61		T3	5		T4	34
valid_sources[0x61]	7467	1			T1	51		T3	8		T4	21
valid_sources[0x62]	7919	1			T1	72		T3	6		T4	6
valid_sources[0x63]	8165	1			T1	112		T3	5		T4	12
valid_sources[0x64]	8971	1			T1	67		T3	5		T4	1
valid_sources[0x65]	7397	1			T1	42		T3	6		T4	21
valid_sources[0x66]	8004	1			T1	96		T3	5		T4	4
valid_sources[0x67]	8246	1			T1	71		T3	6		T4	6
valid_sources[0x68]	8430	1			T1	43		T3	6		T4	12
valid_sources[0x69]	7916	1			T1	59		T3	6		T4	13
valid_sources[0x6a]	7999	1			T1	80		T3	6		T4	5
valid_sources[0x6b]	7462	1			T1	71		T3	5		T15	13
valid_sources[0x6c]	8650	1			T1	48		T3	7		T4	3
valid_sources[0x6d]	7064	1			T1	51		T3	5		T4	2
valid_sources[0x6e]	7741	1			T1	58		T3	5		T4	7
valid_sources[0x6f]	7843	1			T1	74		T3	6		T4	5
valid_sources[0x70]	7576	1			T1	74		T3	6		T4	8
valid_sources[0x71]	8480	1			T1	78		T3	6		T4	4
valid_sources[0x72]	7274	1			T1	78		T3	6		T4	5
valid_sources[0x73]	7131	1			T1	74		T3	6		T4	11
valid_sources[0x74]	7484	1			T1	55		T3	5		T4	3
valid_sources[0x75]	7347	1			T1	64		T3	6		T4	2
valid_sources[0x76]	8080	1			T1	59		T3	6		T4	4
valid_sources[0x77]	8093	1			T1	102		T3	6		T4	9
valid_sources[0x78]	7577	1			T1	79		T3	6		T4	6
valid_sources[0x79]	8606	1			T1	72		T3	6		T4	1
valid_sources[0x7a]	8242	1			T1	90		T3	5		T4	17
valid_sources[0x7b]	7565	1			T1	51		T3	5		T4	11
valid_sources[0x7c]	7201	1			T1	83		T3	6		T4	2
valid_sources[0x7d]	7466	1			T1	83		T3	5		T4	2
valid_sources[0x7e]	8152	1			T1	62		T2	91		T3	6
valid_sources[0x7f]	8243	1			T1	70		T3	7		T4	18
valid_sources[0x80]	7495	1			T1	85		T3	6		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28677

1

T1

229

T2

4

T3

19

values[0x0]

all_enables

biggest_size

214764

1

T1

1818

T2

22

T3

147

values[0x1]

all_enables

biggest_size

28306

1

T1

218

T2

1

T3

25