Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	333339923	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333339923	0	0
T1	1731520	74151	0	0
T2	40656	893	0	0
T3	8045520	1113996	0	0
T4	2240280	56318	0	0
T5	2162608	46136	0	0
T13	244832	8337	0	0
T14	22288	596	0	0
T15	14691376	334634	0	0
T16	219632	5040	0	0
T17	5954256	1004656	0	0
T18	0	3545	0	0
T19	0	493614	0	0
T20	0	784	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1731520	1721328	0	0
T2	40656	37688	0	0
T3	8045520	8045240	0	0
T4	2240280	2238992	0	0
T5	2162608	2157736	0	0
T13	244832	242816	0	0
T14	22288	21224	0	0
T15	14691376	14635824	0	0
T16	219632	214312	0	0
T17	5954256	5954032	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1731520	1721328	0	0
T2	40656	37688	0	0
T3	8045520	8045240	0	0
T4	2240280	2238992	0	0
T5	2162608	2157736	0	0
T13	244832	242816	0	0
T14	22288	21224	0	0
T15	14691376	14635824	0	0
T16	219632	214312	0	0
T17	5954256	5954032	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1731520	1721328	0	0
T2	40656	37688	0	0
T3	8045520	8045240	0	0
T4	2240280	2238992	0	0
T5	2162608	2157736	0	0
T13	244832	242816	0	0
T14	22288	21224	0	0
T15	14691376	14635824	0	0
T16	219632	214312	0	0
T17	5954256	5954032	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	123545196	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	123545196	0	0
T1	30920	27676	0	0
T2	726	347	0	0
T3	143670	6814	0	0
T4	40005	15312	0	0
T5	38618	17841	0	0
T13	4372	4089	0	0
T14	398	233	0	0
T15	262346	127136	0	0
T16	3922	2137	0	0
T17	106326	104810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	87036337	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	87036337	0	0
T1	30920	16779	0	0
T2	726	182	0	0
T3	143670	550184	0	0
T4	40005	12848	0	0
T5	38618	14610	0	0
T13	4372	2094	0	0
T14	398	121	0	0
T15	262346	71675	0	0
T16	3922	985	0	0
T17	106326	447214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1338544	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1338544	0	0
T1	30920	362	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	3380	0	0
T5	38618	267	0	0
T13	4372	33	0	0
T14	398	12	0	0
T15	262346	2221	0	0
T16	3922	38	0	0
T17	106326	180	0	0
T18	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3429093	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3429093	0	0
T1	30920	362	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	3233	0	0
T5	38618	250	0	0
T13	4372	33	0	0
T14	398	12	0	0
T15	262346	2296	0	0
T16	3922	41	0	0
T17	106326	19318	0	0
T18	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1384010	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1384010	0	0
T1	30920	356	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	388	0	0
T13	4372	43	0	0
T14	398	3	0	0
T15	262346	1880	0	0
T16	3922	20	0	0
T17	106326	222	0	0
T18	0	102	0	0
T19	0	318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2821737	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2821737	0	0
T1	30920	356	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	355	0	0
T13	4372	43	0	0
T14	398	3	0	0
T15	262346	1920	0	0
T16	3922	43	0	0
T17	106326	20565	0	0
T18	0	53	0	0
T19	0	32151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1370107	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1370107	0	0
T1	30920	807	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	296	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	2567	0	0
T16	3922	18	0	0
T17	106326	239	0	0
T18	0	123	0	0
T19	0	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3500430	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3500430	0	0
T1	30920	807	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	250	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	2670	0	0
T16	3922	25	0	0
T17	106326	17004	0	0
T18	0	48	0	0
T19	0	35864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1406565	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1406565	0	0
T1	30920	346	0	0
T2	726	11	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	265	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	2072	0	0
T16	3922	34	0	0
T17	106326	167	0	0
T18	0	92	0	0
T19	0	304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3908368	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3908368	0	0
T1	30920	346	0	0
T2	726	11	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	278	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	1981	0	0
T16	3922	58	0	0
T17	106326	14029	0	0
T18	0	34	0	0
T19	0	27064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1357184	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1357184	0	0
T1	30920	832	0	0
T2	726	9	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	304	0	0
T13	4372	44	0	0
T14	398	4	0	0
T15	262346	2064	0	0
T16	3922	39	0	0
T17	106326	204	0	0
T18	0	148	0	0
T19	0	298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2884702	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2884702	0	0
T1	30920	832	0	0
T2	726	9	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	280	0	0
T13	4372	44	0	0
T14	398	4	0	0
T15	262346	1959	0	0
T16	3922	19	0	0
T17	106326	16015	0	0
T18	0	91	0	0
T19	0	26112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1375406	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1375406	0	0
T1	30920	776	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	1335	0	0
T5	38618	372	0	0
T13	4372	34	0	0
T14	398	3	0	0
T15	262346	2269	0	0
T16	3922	26	0	0
T17	106326	234	0	0
T18	0	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3473822	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3473822	0	0
T1	30920	776	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	1552	0	0
T5	38618	347	0	0
T13	4372	34	0	0
T14	398	3	0	0
T15	262346	2322	0	0
T16	3922	11	0	0
T17	106326	22118	0	0
T18	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1363282	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1363282	0	0
T1	30920	349	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	95	0	0
T13	4372	40	0	0
T14	398	10	0	0
T15	262346	2345	0	0
T16	3922	76	0	0
T17	106326	157	0	0
T18	0	121	0	0
T19	0	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2844859	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2844859	0	0
T1	30920	349	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	158	0	0
T13	4372	40	0	0
T14	398	10	0	0
T15	262346	2009	0	0
T16	3922	65	0	0
T17	106326	9781	0	0
T18	0	49	0	0
T19	0	40715	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1356381	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1356381	0	0
T1	30920	621	0	0
T2	726	5	0	0
T3	143670	1105	0	0
T4	40005	0	0	0
T5	38618	286	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	1848	0	0
T16	3922	20	0	0
T17	106326	223	0	0
T18	0	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3206710	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3206710	0	0
T1	30920	621	0	0
T2	726	5	0	0
T3	143670	92177	0	0
T4	40005	0	0	0
T5	38618	324	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	1609	0	0
T16	3922	73	0	0
T17	106326	12443	0	0
T18	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1389280	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1389280	0	0
T1	30920	668	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	247	0	0
T13	4372	40	0	0
T14	398	4	0	0
T15	262346	2028	0	0
T16	3922	0	0	0
T17	106326	208	0	0
T18	0	66	0	0
T19	0	270	0	0
T20	0	570	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3296516	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3296516	0	0
T1	30920	668	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	245	0	0
T13	4372	40	0	0
T14	398	4	0	0
T15	262346	2080	0	0
T16	3922	0	0	0
T17	106326	15455	0	0
T18	0	34	0	0
T19	0	26105	0	0
T20	0	214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1364875	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1364875	0	0
T1	30920	342	0	0
T2	726	8	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	242	0	0
T13	4372	43	0	0
T14	398	1	0	0
T15	262346	2146	0	0
T16	3922	73	0	0
T17	106326	194	0	0
T18	0	134	0	0
T19	0	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3403435	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3403435	0	0
T1	30920	342	0	0
T2	726	8	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	231	0	0
T13	4372	43	0	0
T14	398	1	0	0
T15	262346	1939	0	0
T16	3922	59	0	0
T17	106326	16737	0	0
T18	0	55	0	0
T19	0	22719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1381578	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1381578	0	0
T1	30920	784	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	191	0	0
T13	4372	33	0	0
T14	398	1	0	0
T15	262346	2117	0	0
T16	3922	46	0	0
T17	106326	172	0	0
T18	0	91	0	0
T19	0	362	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3349631	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3349631	0	0
T1	30920	784	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	213	0	0
T13	4372	33	0	0
T14	398	1	0	0
T15	262346	2146	0	0
T16	3922	47	0	0
T17	106326	16709	0	0
T18	0	10	0	0
T19	0	33571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1343307	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1343307	0	0
T1	30920	556	0	0
T2	726	6	0	0
T3	143670	1136	0	0
T4	40005	1645	0	0
T5	38618	234	0	0
T13	4372	48	0	0
T14	398	8	0	0
T15	262346	3791	0	0
T16	3922	25	0	0
T17	106326	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3064746	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3064746	0	0
T1	30920	556	0	0
T2	726	6	0	0
T3	143670	92118	0	0
T4	40005	1184	0	0
T5	38618	279	0	0
T13	4372	48	0	0
T14	398	8	0	0
T15	262346	4021	0	0
T16	3922	62	0	0
T17	106326	19617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1320994	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1320994	0	0
T1	30920	342	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	300	0	0
T13	4372	40	0	0
T14	398	6	0	0
T15	262346	1791	0	0
T16	3922	43	0	0
T17	106326	238	0	0
T18	0	102	0	0
T19	0	360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3686690	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3686690	0	0
T1	30920	342	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	302	0	0
T13	4372	40	0	0
T14	398	6	0	0
T15	262346	1703	0	0
T16	3922	53	0	0
T17	106326	18498	0	0
T18	0	45	0	0
T19	0	37269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1336063	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1336063	0	0
T1	30920	308	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	155	0	0
T13	4372	43	0	0
T14	398	2	0	0
T15	262346	2160	0	0
T16	3922	38	0	0
T17	106326	193	0	0
T18	0	147	0	0
T19	0	359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3501889	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3501889	0	0
T1	30920	308	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	152	0	0
T13	4372	43	0	0
T14	398	2	0	0
T15	262346	2164	0	0
T16	3922	25	0	0
T17	106326	15383	0	0
T18	0	29	0	0
T19	0	31869	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1333318	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1333318	0	0
T1	30920	341	0	0
T2	726	11	0	0
T3	143670	1372	0	0
T4	40005	0	0	0
T5	38618	138	0	0
T13	4372	30	0	0
T14	398	4	0	0
T15	262346	4295	0	0
T16	3922	77	0	0
T17	106326	214	0	0
T18	0	116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2953315	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2953315	0	0
T1	30920	341	0	0
T2	726	11	0	0
T3	143670	104115	0	0
T4	40005	0	0	0
T5	38618	187	0	0
T13	4372	30	0	0
T14	398	4	0	0
T15	262346	4197	0	0
T16	3922	63	0	0
T17	106326	16498	0	0
T18	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1382673	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1382673	0	0
T1	30920	365	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	197	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	1950	0	0
T16	3922	6	0	0
T17	106326	208	0	0
T18	0	110	0	0
T19	0	359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2872981	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2872981	0	0
T1	30920	365	0	0
T2	726	6	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	225	0	0
T13	4372	39	0	0
T14	398	5	0	0
T15	262346	1913	0	0
T16	3922	15	0	0
T17	106326	18726	0	0
T18	0	37	0	0
T19	0	34034	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1352659	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1352659	0	0
T1	30920	1108	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	238	0	0
T13	4372	44	0	0
T14	398	1	0	0
T15	262346	4207	0	0
T16	3922	35	0	0
T17	106326	223	0	0
T18	0	62	0	0
T19	0	291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3022052	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3022052	0	0
T1	30920	1108	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	226	0	0
T13	4372	44	0	0
T14	398	1	0	0
T15	262346	4048	0	0
T16	3922	35	0	0
T17	106326	14834	0	0
T18	0	19	0	0
T19	0	28961	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1316411	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1316411	0	0
T1	30920	356	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	362	0	0
T13	4372	28	0	0
T14	398	4	0	0
T15	262346	2331	0	0
T16	3922	11	0	0
T17	106326	212	0	0
T18	0	60	0	0
T19	0	389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3231241	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3231241	0	0
T1	30920	356	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	384	0	0
T13	4372	28	0	0
T14	398	4	0	0
T15	262346	2350	0	0
T16	3922	18	0	0
T17	106326	18483	0	0
T18	0	32	0	0
T19	0	31283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1367332	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1367332	0	0
T1	30920	557	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	322	0	0
T13	4372	36	0	0
T14	398	8	0	0
T15	262346	4196	0	0
T16	3922	62	0	0
T17	106326	197	0	0
T18	0	92	0	0
T19	0	332	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2781067	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2781067	0	0
T1	30920	557	0	0
T2	726	5	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	288	0	0
T13	4372	36	0	0
T14	398	8	0	0
T15	262346	4405	0	0
T16	3922	47	0	0
T17	106326	15768	0	0
T18	0	45	0	0
T19	0	26464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1402853	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1402853	0	0
T1	30920	579	0	0
T2	726	4	0	0
T3	143670	1109	0	0
T4	40005	0	0	0
T5	38618	199	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	5692	0	0
T16	3922	23	0	0
T17	106326	163	0	0
T18	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2680465	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2680465	0	0
T1	30920	579	0	0
T2	726	4	0	0
T3	143670	95372	0	0
T4	40005	0	0	0
T5	38618	207	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	5832	0	0
T16	3922	37	0	0
T17	106326	16990	0	0
T18	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1371548	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1371548	0	0
T1	30920	339	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	1809	0	0
T5	38618	195	0	0
T13	4372	42	0	0
T14	398	5	0	0
T15	262346	1906	0	0
T16	3922	36	0	0
T17	106326	185	0	0
T18	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2230271	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2230271	0	0
T1	30920	339	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	1797	0	0
T5	38618	223	0	0
T13	4372	42	0	0
T14	398	5	0	0
T15	262346	1783	0	0
T16	3922	33	0	0
T17	106326	14727	0	0
T18	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1319764	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1319764	0	0
T1	30920	852	0	0
T2	726	12	0	0
T3	143670	0	0	0
T4	40005	2565	0	0
T5	38618	152	0	0
T13	4372	46	0	0
T14	398	4	0	0
T15	262346	2079	0	0
T16	3922	30	0	0
T17	106326	189	0	0
T18	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3399628	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3399628	0	0
T1	30920	852	0	0
T2	726	12	0	0
T3	143670	0	0	0
T4	40005	1743	0	0
T5	38618	209	0	0
T13	4372	46	0	0
T14	398	4	0	0
T15	262346	2115	0	0
T16	3922	14	0	0
T17	106326	17814	0	0
T18	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1387918	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1387918	0	0
T1	30920	558	0	0
T2	726	8	0	0
T3	143670	0	0	0
T4	40005	2032	0	0
T5	38618	295	0	0
T13	4372	50	0	0
T14	398	4	0	0
T15	262346	1766	0	0
T16	3922	26	0	0
T17	106326	217	0	0
T18	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3404715	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3404715	0	0
T1	30920	558	0	0
T2	726	8	0	0
T3	143670	0	0	0
T4	40005	1510	0	0
T5	38618	325	0	0
T13	4372	50	0	0
T14	398	4	0	0
T15	262346	1780	0	0
T16	3922	30	0	0
T17	106326	18778	0	0
T18	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1339496	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1339496	0	0
T1	30920	310	0	0
T2	726	11	0	0
T3	143670	928	0	0
T4	40005	0	0	0
T5	38618	209	0	0
T13	4372	43	0	0
T14	398	4	0	0
T15	262346	2239	0	0
T16	3922	23	0	0
T17	106326	210	0	0
T18	0	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3408821	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3408821	0	0
T1	30920	310	0	0
T2	726	11	0	0
T3	143670	77808	0	0
T4	40005	0	0	0
T5	38618	294	0	0
T13	4372	43	0	0
T14	398	4	0	0
T15	262346	2174	0	0
T16	3922	31	0	0
T17	106326	19780	0	0
T18	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1341460	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1341460	0	0
T1	30920	1068	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	310	0	0
T13	4372	41	0	0
T14	398	1	0	0
T15	262346	1936	0	0
T16	3922	45	0	0
T17	106326	130	0	0
T18	0	148	0	0
T19	0	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	2936141	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	2936141	0	0
T1	30920	1068	0	0
T2	726	7	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	349	0	0
T13	4372	41	0	0
T14	398	1	0	0
T15	262346	1985	0	0
T16	3922	12	0	0
T17	106326	11051	0	0
T18	0	23	0	0
T19	0	26170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1355781	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1355781	0	0
T1	30920	595	0	0
T2	726	4	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	211	0	0
T13	4372	39	0	0
T14	398	2	0	0
T15	262346	2288	0	0
T16	3922	31	0	0
T17	106326	205	0	0
T18	0	81	0	0
T19	0	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3671968	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3671968	0	0
T1	30920	595	0	0
T2	726	4	0	0
T3	143670	0	0	0
T4	40005	0	0	0
T5	38618	200	0	0
T13	4372	39	0	0
T14	398	2	0	0
T15	262346	2275	0	0
T16	3922	38	0	0
T17	106326	13865	0	0
T18	0	34	0	0
T19	0	27922	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	1310138	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	1310138	0	0
T1	30920	371	0	0
T2	726	5	0	0
T3	143670	1164	0	0
T4	40005	2545	0	0
T5	38618	224	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	2013	0	0
T16	3922	32	0	0
T17	106326	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300670215	3124170	0	0
DepthKnown_A	300670215	300552354	0	0
RvalidKnown_A	300670215	300552354	0	0
WreadyKnown_A	300670215	300552354	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	3124170	0	0
T1	30920	371	0	0
T2	726	5	0	0
T3	143670	88594	0	0
T4	40005	1828	0	0
T5	38618	210	0	0
T13	4372	40	0	0
T14	398	5	0	0
T15	262346	1950	0	0
T16	3922	31	0	0
T17	106326	16228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300670215	300552354	0	0
T1	30920	30738	0	0
T2	726	673	0	0
T3	143670	143665	0	0
T4	40005	39982	0	0
T5	38618	38531	0	0
T13	4372	4336	0	0
T14	398	379	0	0
T15	262346	261354	0	0
T16	3922	3827	0	0
T17	106326	106322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0