Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1556262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244053

1

T1

14

T2

360

T3

454

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	610942	1			T1	51		T2	911		T3	1045
values[0x0]	578669	1			T1	34		T2	920		T3	1035
values[0x1]	610704	1			T1	40		T2	988		T3	1075

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

594660

1

T1

44

T2

952

T3

1053

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6785	1			T3	8		T4	8		T13	3
valid_sources[0x01]	6532	1			T3	6		T4	4		T13	5
valid_sources[0x02]	6367	1			T2	1		T3	5		T4	2
valid_sources[0x03]	7375	1			T3	16		T4	4		T13	3
valid_sources[0x04]	7113	1			T3	18		T4	4		T13	4
valid_sources[0x05]	6896	1			T3	18		T4	5		T13	3
valid_sources[0x06]	6778	1			T2	32		T3	21		T4	2
valid_sources[0x07]	7309	1			T2	22		T3	9		T13	3
valid_sources[0x08]	7245	1			T2	85		T3	12		T4	3
valid_sources[0x09]	6822	1			T3	12		T4	4		T13	3
valid_sources[0x0a]	6869	1			T2	3		T3	13		T4	4
valid_sources[0x0b]	7177	1			T3	9		T4	4		T13	3
valid_sources[0x0c]	7199	1			T2	20		T3	7		T4	2
valid_sources[0x0d]	6849	1			T3	15		T4	4		T13	3
valid_sources[0x0e]	7453	1			T2	12		T3	15		T4	5
valid_sources[0x0f]	7190	1			T3	8		T4	5		T13	3
valid_sources[0x10]	6726	1			T2	10		T3	15		T4	6
valid_sources[0x11]	7153	1			T2	5		T3	13		T4	5
valid_sources[0x12]	6975	1			T3	9		T4	4		T13	3
valid_sources[0x13]	6856	1			T3	12		T4	2		T13	4
valid_sources[0x14]	6915	1			T3	8		T4	6		T13	2
valid_sources[0x15]	6248	1			T2	17		T3	11		T4	3
valid_sources[0x16]	6739	1			T3	18		T4	6		T13	3
valid_sources[0x17]	6759	1			T2	11		T3	12		T4	3
valid_sources[0x18]	6990	1			T2	42		T3	10		T4	5
valid_sources[0x19]	6897	1			T2	2		T3	11		T4	2
valid_sources[0x1a]	7924	1			T2	11		T3	7		T4	3
valid_sources[0x1b]	6852	1			T2	34		T3	7		T4	4
valid_sources[0x1c]	7018	1			T3	18		T4	3		T13	3
valid_sources[0x1d]	6814	1			T1	2		T2	40		T3	11
valid_sources[0x1e]	6934	1			T3	15		T4	3		T14	4
valid_sources[0x1f]	8140	1			T3	5		T4	2		T13	3
valid_sources[0x20]	6899	1			T2	1		T3	9		T4	4
valid_sources[0x21]	7433	1			T2	2		T3	18		T4	4
valid_sources[0x22]	7537	1			T3	15		T4	4		T13	3
valid_sources[0x23]	6261	1			T3	15		T4	2		T13	3
valid_sources[0x24]	6734	1			T2	6		T3	11		T4	7
valid_sources[0x25]	6985	1			T3	9		T4	7		T13	2
valid_sources[0x26]	7312	1			T3	13		T4	3		T13	3
valid_sources[0x27]	7332	1			T2	12		T3	8		T4	5
valid_sources[0x28]	7269	1			T2	7		T3	8		T4	8
valid_sources[0x29]	6573	1			T2	8		T3	12		T4	7
valid_sources[0x2a]	6840	1			T2	41		T3	13		T4	4
valid_sources[0x2b]	7579	1			T1	21		T3	9		T4	3
valid_sources[0x2c]	7024	1			T2	20		T3	13		T4	3
valid_sources[0x2d]	7070	1			T3	7		T4	3		T13	3
valid_sources[0x2e]	7055	1			T2	4		T3	13		T4	4
valid_sources[0x2f]	6799	1			T3	18		T4	2		T13	3
valid_sources[0x30]	6843	1			T2	4		T3	10		T4	4
valid_sources[0x31]	7948	1			T2	11		T3	15		T4	4
valid_sources[0x32]	7451	1			T3	8		T4	8		T13	4
valid_sources[0x33]	7461	1			T2	16		T3	11		T4	6
valid_sources[0x34]	6659	1			T2	5		T3	15		T4	3
valid_sources[0x35]	6611	1			T2	3		T3	6		T4	1
valid_sources[0x36]	7222	1			T2	40		T3	8		T4	2
valid_sources[0x37]	6860	1			T2	67		T3	16		T4	4
valid_sources[0x38]	6976	1			T3	19		T4	6		T13	3
valid_sources[0x39]	6458	1			T2	2		T3	12		T4	2
valid_sources[0x3a]	6910	1			T2	8		T3	13		T4	5
valid_sources[0x3b]	7233	1			T2	20		T3	15		T4	2
valid_sources[0x3c]	7037	1			T3	14		T4	4		T13	3
valid_sources[0x3d]	7448	1			T3	11		T4	6		T13	4
valid_sources[0x3e]	7144	1			T3	15		T4	6		T13	3
valid_sources[0x3f]	6448	1			T3	6		T4	5		T13	3
valid_sources[0x40]	8066	1			T2	6		T3	16		T4	6
valid_sources[0x41]	7054	1			T2	30		T3	16		T4	2
valid_sources[0x42]	8069	1			T3	13		T4	3		T13	3
valid_sources[0x43]	6905	1			T3	7		T4	7		T13	3
valid_sources[0x44]	6700	1			T3	11		T4	2		T13	3
valid_sources[0x45]	7192	1			T2	26		T3	13		T4	5
valid_sources[0x46]	7366	1			T2	59		T3	13		T4	5
valid_sources[0x47]	6642	1			T2	18		T3	22		T4	4
valid_sources[0x48]	6998	1			T3	16		T4	8		T14	1
valid_sources[0x49]	6886	1			T3	24		T4	2		T13	4
valid_sources[0x4a]	7616	1			T3	11		T4	3		T13	3
valid_sources[0x4b]	7264	1			T3	18		T4	5		T13	3
valid_sources[0x4c]	6983	1			T3	11		T4	5		T13	2
valid_sources[0x4d]	6694	1			T1	40		T3	10		T13	3
valid_sources[0x4e]	6584	1			T2	56		T3	9		T4	6
valid_sources[0x4f]	6810	1			T2	9		T3	22		T4	4
valid_sources[0x50]	7244	1			T2	47		T3	15		T4	1
valid_sources[0x51]	7137	1			T2	8		T3	15		T4	8
valid_sources[0x52]	7676	1			T2	4		T3	13		T4	4
valid_sources[0x53]	6921	1			T2	28		T3	10		T4	7
valid_sources[0x54]	6748	1			T3	12		T4	1		T13	3
valid_sources[0x55]	7008	1			T2	7		T3	18		T4	2
valid_sources[0x56]	7320	1			T2	2		T3	15		T4	5
valid_sources[0x57]	6766	1			T3	10		T4	1		T13	3
valid_sources[0x58]	7378	1			T2	58		T3	15		T4	6
valid_sources[0x59]	7521	1			T3	11		T4	9		T13	3
valid_sources[0x5a]	7007	1			T2	6		T3	17		T4	4
valid_sources[0x5b]	6831	1			T2	32		T3	10		T4	5
valid_sources[0x5c]	6997	1			T2	20		T3	16		T4	5
valid_sources[0x5d]	6831	1			T2	1		T3	9		T4	2
valid_sources[0x5e]	7348	1			T2	13		T3	10		T4	5
valid_sources[0x5f]	6913	1			T2	1		T3	13		T4	2
valid_sources[0x60]	6583	1			T3	11		T4	4		T13	3
valid_sources[0x61]	7095	1			T2	18		T3	6		T4	1
valid_sources[0x62]	6839	1			T2	43		T3	16		T4	2
valid_sources[0x63]	6320	1			T2	13		T3	8		T4	4
valid_sources[0x64]	6674	1			T2	14		T3	6		T4	4
valid_sources[0x65]	6800	1			T2	49		T3	12		T4	4
valid_sources[0x66]	7110	1			T2	21		T3	8		T4	3
valid_sources[0x67]	6530	1			T2	4		T3	14		T4	4
valid_sources[0x68]	6861	1			T2	3		T3	14		T4	5
valid_sources[0x69]	6975	1			T3	17		T4	4		T13	4
valid_sources[0x6a]	6276	1			T2	17		T3	9		T4	4
valid_sources[0x6b]	7130	1			T3	7		T4	5		T13	3
valid_sources[0x6c]	7360	1			T3	14		T4	6		T13	3
valid_sources[0x6d]	7215	1			T3	15		T4	9		T13	3
valid_sources[0x6e]	6754	1			T3	9		T4	5		T13	3
valid_sources[0x6f]	6646	1			T3	14		T4	3		T14	1
valid_sources[0x70]	7075	1			T2	1		T3	14		T4	3
valid_sources[0x71]	7028	1			T3	12		T4	6		T13	3
valid_sources[0x72]	6958	1			T2	43		T3	10		T4	4
valid_sources[0x73]	6650	1			T2	12		T3	15		T4	7
valid_sources[0x74]	7015	1			T2	31		T3	15		T4	3
valid_sources[0x75]	7503	1			T2	23		T3	15		T4	2
valid_sources[0x76]	8342	1			T2	10		T3	14		T4	4
valid_sources[0x77]	6572	1			T3	12		T4	2		T13	4
valid_sources[0x78]	7490	1			T3	10		T4	3		T13	3
valid_sources[0x79]	6805	1			T2	4		T3	11		T4	5
valid_sources[0x7a]	6842	1			T2	4		T3	9		T4	4
valid_sources[0x7b]	6662	1			T2	23		T3	8		T4	7
valid_sources[0x7c]	6972	1			T3	12		T4	7		T13	3
valid_sources[0x7d]	6883	1			T3	9		T4	2		T13	3
valid_sources[0x7e]	7445	1			T3	12		T4	5		T13	3
valid_sources[0x7f]	7172	1			T3	5		T4	3		T13	3
valid_sources[0x80]	6838	1			T2	102		T3	11		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26097

1

T1

1

T2

34

T3

38

values[0x0]

all_enables

biggest_size

191843

1

T1

11

T2

285

T3

360

values[0x1]

all_enables

biggest_size

26113

1

T1

2

T2

41

T3

56