Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	319634371	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319634371	0	0
T1	6433236	122322	0	0
T2	18998280	2706157	0	0
T3	3486504	71705	0	0
T4	2590224	111227	0	0
T11	217728	9104	0	0
T12	944160	42466	0	0
T13	36974728	545150	0	0
T14	3219832	58100	0	0
T15	13486816	2094564	0	0
T16	311136	12833	0	0
T17	49912	21768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671504	6671000	0	0
T2	18998280	18998000	0	0
T3	3486504	3484656	0	0
T4	2590224	2533384	0	0
T11	217728	214592	0	0
T12	944160	942592	0	0
T13	36974728	36974056	0	0
T14	3219832	3218936	0	0
T15	13486816	13486536	0	0
T16	311136	306376	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671504	6671000	0	0
T2	18998280	18998000	0	0
T3	3486504	3484656	0	0
T4	2590224	2533384	0	0
T11	217728	214592	0	0
T12	944160	942592	0	0
T13	36974728	36974056	0	0
T14	3219832	3218936	0	0
T15	13486816	13486536	0	0
T16	311136	306376	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6671504	6671000	0	0
T2	18998280	18998000	0	0
T3	3486504	3484656	0	0
T4	2590224	2533384	0	0
T11	217728	214592	0	0
T12	944160	942592	0	0
T13	36974728	36974056	0	0
T14	3219832	3218936	0	0
T15	13486816	13486536	0	0
T16	311136	306376	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	115465834	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	115465834	0	0
T1	119134	57783	0	0
T2	339255	189608	0	0
T3	62259	29763	0	0
T4	46254	42636	0	0
T11	3888	3543	0	0
T12	16860	13728	0	0
T13	660263	3449	0	0
T14	57497	55588	0	0
T15	240836	148113	0	0
T16	5556	4993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	83194156	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	83194156	0	0
T1	119134	13690	0	0
T2	339255	787110	0	0
T3	62259	19191	0	0
T4	46254	24553	0	0
T11	3888	1855	0	0
T12	16860	9926	0	0
T13	660263	269126	0	0
T14	57497	1018	0	0
T15	240836	655791	0	0
T16	5556	2614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1457100	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1457100	0	0
T1	119134	989	0	0
T2	339255	36101	0	0
T3	62259	376	0	0
T4	46254	810	0	0
T11	3888	63	0	0
T12	16860	489	0	0
T13	660263	1305	0	0
T14	57497	25	0	0
T15	240836	18852	0	0
T16	5556	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3265833	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3265833	0	0
T1	119134	522	0	0
T2	339255	33243	0	0
T3	62259	332	0	0
T4	46254	810	0	0
T11	3888	63	0	0
T12	16860	489	0	0
T13	660263	97460	0	0
T14	57497	5	0	0
T15	240836	16196	0	0
T16	5556	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1420736	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1420736	0	0
T1	119134	899	0	0
T2	339255	30244	0	0
T3	62259	421	0	0
T4	46254	537	0	0
T11	3888	62	0	0
T12	16860	227	0	0
T13	660263	0	0	0
T14	57497	1	0	0
T15	240836	19268	0	0
T16	5556	113	0	0
T17	0	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3670953	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3670953	0	0
T1	119134	3	0	0
T2	339255	20974	0	0
T3	62259	373	0	0
T4	46254	537	0	0
T11	3888	62	0	0
T12	16860	227	0	0
T13	660263	0	0	0
T14	57497	1	0	0
T15	240836	24256	0	0
T16	5556	113	0	0
T17	0	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1385385	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1385385	0	0
T1	119134	2077	0	0
T2	339255	33154	0	0
T3	62259	374	0	0
T4	46254	788	0	0
T11	3888	76	0	0
T12	16860	242	0	0
T13	660263	0	0	0
T14	57497	14	0	0
T15	240836	23379	0	0
T16	5556	85	0	0
T17	0	489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2529905	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2529905	0	0
T1	119134	267	0	0
T2	339255	27265	0	0
T3	62259	366	0	0
T4	46254	788	0	0
T11	3888	76	0	0
T12	16860	242	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	30543	0	0
T16	5556	85	0	0
T17	0	489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1452555	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1452555	0	0
T1	119134	1721	0	0
T2	339255	32311	0	0
T3	62259	509	0	0
T4	46254	827	0	0
T11	3888	80	0	0
T12	16860	225	0	0
T13	660263	0	0	0
T14	57497	22	0	0
T15	240836	22103	0	0
T16	5556	87	0	0
T17	0	721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3248357	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3248357	0	0
T1	119134	1260	0	0
T2	339255	24655	0	0
T3	62259	442	0	0
T4	46254	827	0	0
T11	3888	80	0	0
T12	16860	225	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	22018	0	0
T16	5556	87	0	0
T17	0	721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1436637	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1436637	0	0
T1	119134	2429	0	0
T2	339255	37637	0	0
T3	62259	475	0	0
T4	46254	603	0	0
T11	3888	82	0	0
T12	16860	447	0	0
T13	660263	0	0	0
T14	57497	5	0	0
T15	240836	24998	0	0
T16	5556	85	0	0
T17	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3252382	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3252382	0	0
T1	119134	167	0	0
T2	339255	22466	0	0
T3	62259	440	0	0
T4	46254	603	0	0
T11	3888	82	0	0
T12	16860	447	0	0
T13	660263	0	0	0
T14	57497	911	0	0
T15	240836	22977	0	0
T16	5556	85	0	0
T17	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1400594	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1400594	0	0
T2	339255	38307	0	0
T3	62259	480	0	0
T4	46254	578	0	0
T11	3888	75	0	0
T12	16860	240	0	0
T13	660263	988	0	0
T14	57497	10	0	0
T15	240836	29882	0	0
T16	5556	94	0	0
T17	24956	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2765886	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2765886	0	0
T2	339255	32686	0	0
T3	62259	428	0	0
T4	46254	578	0	0
T11	3888	75	0	0
T12	16860	240	0	0
T13	660263	81596	0	0
T14	57497	1	0	0
T15	240836	28549	0	0
T16	5556	94	0	0
T17	24956	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1395660	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1395660	0	0
T1	119134	1869	0	0
T2	339255	33560	0	0
T3	62259	432	0	0
T4	46254	848	0	0
T11	3888	73	0	0
T12	16860	420	0	0
T13	660263	0	0	0
T14	57497	30	0	0
T15	240836	29347	0	0
T16	5556	85	0	0
T17	0	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3218092	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3218092	0	0
T1	119134	1132	0	0
T2	339255	28139	0	0
T3	62259	355	0	0
T4	46254	848	0	0
T11	3888	73	0	0
T12	16860	420	0	0
T13	660263	0	0	0
T14	57497	5	0	0
T15	240836	34109	0	0
T16	5556	85	0	0
T17	0	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1458195	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1458195	0	0
T1	119134	2097	0	0
T2	339255	33734	0	0
T3	62259	460	0	0
T4	46254	785	0	0
T11	3888	66	0	0
T12	16860	782	0	0
T13	660263	0	0	0
T14	57497	28	0	0
T15	240836	26479	0	0
T16	5556	91	0	0
T17	0	525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2878068	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2878068	0	0
T1	119134	1210	0	0
T2	339255	26970	0	0
T3	62259	340	0	0
T4	46254	785	0	0
T11	3888	66	0	0
T12	16860	782	0	0
T13	660263	0	0	0
T14	57497	6	0	0
T15	240836	29768	0	0
T16	5556	91	0	0
T17	0	525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1462014	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1462014	0	0
T1	119134	1080	0	0
T2	339255	34690	0	0
T3	62259	449	0	0
T4	46254	1396	0	0
T11	3888	57	0	0
T12	16860	209	0	0
T13	660263	0	0	0
T14	57497	14	0	0
T15	240836	18028	0	0
T16	5556	110	0	0
T17	0	700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3048441	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3048441	0	0
T1	119134	253	0	0
T2	339255	22707	0	0
T3	62259	435	0	0
T4	46254	1396	0	0
T11	3888	57	0	0
T12	16860	209	0	0
T13	660263	0	0	0
T14	57497	3	0	0
T15	240836	18788	0	0
T16	5556	110	0	0
T17	0	700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1402177	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1402177	0	0
T1	119134	1625	0	0
T2	339255	34824	0	0
T3	62259	485	0	0
T4	46254	1120	0	0
T11	3888	61	0	0
T12	16860	179	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	21141	0	0
T16	5556	83	0	0
T17	0	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2737097	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2737097	0	0
T1	119134	38	0	0
T2	339255	31657	0	0
T3	62259	430	0	0
T4	46254	1120	0	0
T11	3888	61	0	0
T12	16860	179	0	0
T13	660263	0	0	0
T14	57497	3	0	0
T15	240836	22650	0	0
T16	5556	83	0	0
T17	0	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1412656	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1412656	0	0
T1	119134	414	0	0
T2	339255	29365	0	0
T3	62259	583	0	0
T4	46254	552	0	0
T11	3888	90	0	0
T12	16860	224	0	0
T13	660263	0	0	0
T14	57497	9	0	0
T15	240836	19477	0	0
T16	5556	116	0	0
T17	0	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3448134	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3448134	0	0
T1	119134	34	0	0
T2	339255	23103	0	0
T3	62259	430	0	0
T4	46254	552	0	0
T11	3888	90	0	0
T12	16860	224	0	0
T13	660263	0	0	0
T14	57497	3	0	0
T15	240836	17665	0	0
T16	5556	116	0	0
T17	0	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1414361	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1414361	0	0
T1	119134	320	0	0
T2	339255	40888	0	0
T3	62259	562	0	0
T4	46254	823	0	0
T11	3888	77	0	0
T12	16860	241	0	0
T13	660263	1156	0	0
T14	57497	11	0	0
T15	240836	18751	0	0
T16	5556	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2996231	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2996231	0	0
T1	119134	2	0	0
T2	339255	34940	0	0
T3	62259	524	0	0
T4	46254	823	0	0
T11	3888	77	0	0
T12	16860	241	0	0
T13	660263	90070	0	0
T14	57497	5	0	0
T15	240836	21246	0	0
T16	5556	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1417624	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1417624	0	0
T1	119134	3085	0	0
T2	339255	35019	0	0
T3	62259	403	0	0
T4	46254	586	0	0
T11	3888	72	0	0
T12	16860	221	0	0
T13	660263	0	0	0
T14	57497	29	0	0
T15	240836	21428	0	0
T16	5556	102	0	0
T17	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2381090	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2381090	0	0
T1	119134	830	0	0
T2	339255	32621	0	0
T3	62259	324	0	0
T4	46254	586	0	0
T11	3888	72	0	0
T12	16860	221	0	0
T13	660263	0	0	0
T14	57497	5	0	0
T15	240836	28844	0	0
T16	5556	102	0	0
T17	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1416603	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1416603	0	0
T1	119134	2605	0	0
T2	339255	33254	0	0
T3	62259	297	0	0
T4	46254	594	0	0
T11	3888	60	0	0
T12	16860	456	0	0
T13	660263	0	0	0
T14	57497	14	0	0
T15	240836	24556	0	0
T16	5556	81	0	0
T17	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2997637	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2997637	0	0
T1	119134	378	0	0
T2	339255	29034	0	0
T3	62259	281	0	0
T4	46254	593	0	0
T11	3888	60	0	0
T12	16860	456	0	0
T13	660263	0	0	0
T14	57497	2	0	0
T15	240836	26824	0	0
T16	5556	81	0	0
T17	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1459916	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1459916	0	0
T1	119134	1313	0	0
T2	339255	34979	0	0
T3	62259	452	0	0
T4	46254	588	0	0
T11	3888	78	0	0
T12	16860	229	0	0
T13	660263	0	0	0
T14	57497	11	0	0
T15	240836	21454	0	0
T16	5556	90	0	0
T17	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2164291	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2164291	0	0
T1	119134	2307	0	0
T2	339255	29398	0	0
T3	62259	396	0	0
T4	46254	587	0	0
T11	3888	78	0	0
T12	16860	229	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	23787	0	0
T16	5556	90	0	0
T17	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1464874	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1464874	0	0
T1	119134	2269	0	0
T2	339255	34827	0	0
T3	62259	457	0	0
T4	46254	855	0	0
T11	3888	70	0	0
T12	16860	211	0	0
T13	660263	0	0	0
T14	57497	27	0	0
T15	240836	26283	0	0
T16	5556	100	0	0
T17	0	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3267502	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3267502	0	0
T1	119134	126	0	0
T2	339255	28085	0	0
T3	62259	342	0	0
T4	46254	855	0	0
T11	3888	70	0	0
T12	16860	211	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	25198	0	0
T16	5556	100	0	0
T17	0	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1447349	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1447349	0	0
T1	119134	1531	0	0
T2	339255	37228	0	0
T3	62259	355	0	0
T4	46254	567	0	0
T11	3888	76	0	0
T12	16860	553	0	0
T13	660263	0	0	0
T14	57497	6	0	0
T15	240836	25656	0	0
T16	5556	112	0	0
T17	0	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3067690	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3067690	0	0
T1	119134	431	0	0
T2	339255	32583	0	0
T3	62259	364	0	0
T4	46254	567	0	0
T11	3888	76	0	0
T12	16860	553	0	0
T13	660263	0	0	0
T14	57497	1	0	0
T15	240836	20019	0	0
T16	5556	112	0	0
T17	0	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1472396	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1472396	0	0
T1	119134	401	0	0
T2	339255	34954	0	0
T3	62259	373	0	0
T4	46254	1117	0	0
T11	3888	67	0	0
T12	16860	231	0	0
T13	660263	0	0	0
T14	57497	21	0	0
T15	240836	19560	0	0
T16	5556	112	0	0
T17	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3374466	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3374466	0	0
T1	119134	464	0	0
T2	339255	27568	0	0
T3	62259	411	0	0
T4	46254	1117	0	0
T11	3888	67	0	0
T12	16860	231	0	0
T13	660263	0	0	0
T14	57497	6	0	0
T15	240836	19941	0	0
T16	5556	112	0	0
T17	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1445721	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1445721	0	0
T1	119134	1709	0	0
T2	339255	31262	0	0
T3	62259	378	0	0
T4	46254	1162	0	0
T11	3888	66	0	0
T12	16860	513	0	0
T13	660263	0	0	0
T14	57497	9	0	0
T15	240836	24967	0	0
T16	5556	99	0	0
T17	0	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3176215	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3176215	0	0
T1	119134	679	0	0
T2	339255	30350	0	0
T3	62259	270	0	0
T4	46254	1162	0	0
T11	3888	66	0	0
T12	16860	513	0	0
T13	660263	0	0	0
T14	57497	3	0	0
T15	240836	24290	0	0
T16	5556	99	0	0
T17	0	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1420261	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1420261	0	0
T1	119134	383	0	0
T2	339255	27563	0	0
T3	62259	427	0	0
T4	46254	1262	0	0
T11	3888	52	0	0
T12	16860	249	0	0
T13	660263	0	0	0
T14	57497	27	0	0
T15	240836	21422	0	0
T16	5556	90	0	0
T17	0	458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2463858	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2463858	0	0
T1	119134	178	0	0
T2	339255	29387	0	0
T3	62259	346	0	0
T4	46254	1262	0	0
T11	3888	52	0	0
T12	16860	249	0	0
T13	660263	0	0	0
T14	57497	6	0	0
T15	240836	20046	0	0
T16	5556	90	0	0
T17	0	458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1472402	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1472402	0	0
T1	119134	1828	0	0
T2	339255	40385	0	0
T3	62259	437	0	0
T4	46254	542	0	0
T11	3888	70	0	0
T12	16860	710	0	0
T13	660263	0	0	0
T14	57497	27	0	0
T15	240836	28659	0	0
T16	5556	97	0	0
T17	0	239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2691861	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2691861	0	0
T1	119134	786	0	0
T2	339255	31051	0	0
T3	62259	383	0	0
T4	46254	542	0	0
T11	3888	70	0	0
T12	16860	710	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	23508	0	0
T16	5556	97	0	0
T17	0	239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1445888	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1445888	0	0
T1	119134	137	0	0
T2	339255	37726	0	0
T3	62259	430	0	0
T4	46254	983	0	0
T11	3888	57	0	0
T12	16860	238	0	0
T13	660263	0	0	0
T14	57497	12	0	0
T15	240836	25402	0	0
T16	5556	98	0	0
T17	0	692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3246816	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3246816	0	0
T1	119134	313	0	0
T2	339255	32130	0	0
T3	62259	417	0	0
T4	46254	983	0	0
T11	3888	57	0	0
T12	16860	238	0	0
T13	660263	0	0	0
T14	57497	4	0	0
T15	240836	27122	0	0
T16	5556	98	0	0
T17	0	692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1400734	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1400734	0	0
T1	119134	715	0	0
T2	339255	30323	0	0
T3	62259	600	0	0
T4	46254	563	0	0
T11	3888	65	0	0
T12	16860	195	0	0
T13	660263	0	0	0
T14	57497	25	0	0
T15	240836	30330	0	0
T16	5556	90	0	0
T17	0	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	2889807	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	2889807	0	0
T1	119134	131	0	0
T2	339255	23837	0	0
T3	62259	449	0	0
T4	46254	562	0	0
T11	3888	65	0	0
T12	16860	195	0	0
T13	660263	0	0	0
T14	57497	5	0	0
T15	240836	29684	0	0
T16	5556	90	0	0
T17	0	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1466478	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1466478	0	0
T1	119134	1661	0	0
T2	339255	39933	0	0
T3	62259	557	0	0
T4	46254	516	0	0
T11	3888	63	0	0
T12	16860	215	0	0
T13	660263	0	0	0
T14	57497	38	0	0
T15	240836	20339	0	0
T16	5556	97	0	0
T17	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3645082	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3645082	0	0
T1	119134	354	0	0
T2	339255	34464	0	0
T3	62259	416	0	0
T4	46254	516	0	0
T11	3888	63	0	0
T12	16860	215	0	0
T13	660263	0	0	0
T14	57497	9	0	0
T15	240836	21928	0	0
T16	5556	97	0	0
T17	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1418421	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1418421	0	0
T1	119134	1222	0	0
T2	339255	35239	0	0
T3	62259	396	0	0
T4	46254	869	0	0
T11	3888	71	0	0
T12	16860	459	0	0
T13	660263	0	0	0
T14	57497	15	0	0
T15	240836	28050	0	0
T16	5556	96	0	0
T17	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3456195	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3456195	0	0
T1	119134	515	0	0
T2	339255	33215	0	0
T3	62259	364	0	0
T4	46254	869	0	0
T11	3888	71	0	0
T12	16860	459	0	0
T13	660263	0	0	0
T14	57497	3	0	0
T15	240836	31712	0	0
T16	5556	96	0	0
T17	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1439634	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1439634	0	0
T1	119134	2435	0	0
T2	339255	40969	0	0
T3	62259	467	0	0
T4	46254	1092	0	0
T11	3888	60	0	0
T12	16860	484	0	0
T13	660263	0	0	0
T14	57497	16	0	0
T15	240836	22362	0	0
T16	5556	103	0	0
T17	0	266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3149815	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3149815	0	0
T1	119134	993	0	0
T2	339255	34225	0	0
T3	62259	448	0	0
T4	46254	1091	0	0
T11	3888	60	0	0
T12	16860	484	0	0
T13	660263	0	0	0
T14	57497	6	0	0
T15	240836	19853	0	0
T16	5556	103	0	0
T17	0	266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	1419143	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	1419143	0	0
T1	119134	345	0	0
T2	339255	33948	0	0
T3	62259	532	0	0
T4	46254	1058	0	0
T11	3888	64	0	0
T12	16860	517	0	0
T13	660263	0	0	0
T14	57497	26	0	0
T15	240836	23507	0	0
T16	5556	110	0	0
T17	0	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292909807	3237163	0	0
DepthKnown_A	292909807	292792861	0	0
RvalidKnown_A	292909807	292792861	0	0
WreadyKnown_A	292909807	292792861	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	3237163	0	0
T1	119134	317	0	0
T2	339255	30262	0	0
T3	62259	478	0	0
T4	46254	1058	0	0
T11	3888	64	0	0
T12	16860	517	0	0
T13	660263	0	0	0
T14	57497	5	0	0
T15	240836	23459	0	0
T16	5556	110	0	0
T17	0	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292909807	292792861	0	0
T1	119134	119125	0	0
T2	339255	339250	0	0
T3	62259	62226	0	0
T4	46254	45239	0	0
T11	3888	3832	0	0
T12	16860	16832	0	0
T13	660263	660251	0	0
T14	57497	57481	0	0
T15	240836	240831	0	0
T16	5556	5471	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0