Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1823098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

287218

1

T1

29

T2

12

T3

468

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	713744	1			T1	63		T2	40		T3	1100
values[0x0]	683745	1			T1	55		T2	4		T3	1174
values[0x1]	712827	1			T1	55		T2	52		T3	1110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1413946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

696370

1

T1

62

T2

39

T3

1131

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7614	1			T3	13		T5	18		T8	1
valid_sources[0x01]	8364	1			T2	1		T3	20		T5	15
valid_sources[0x02]	8024	1			T3	16		T5	17		T8	1
valid_sources[0x03]	8340	1			T3	8		T5	17		T22	1
valid_sources[0x04]	7372	1			T2	1		T3	8		T5	17
valid_sources[0x05]	9210	1			T2	1		T3	17		T5	17
valid_sources[0x06]	8853	1			T3	6		T5	16		T8	2
valid_sources[0x07]	8095	1			T3	8		T5	17		T7	3
valid_sources[0x08]	7258	1			T3	2		T5	18		T7	14
valid_sources[0x09]	7993	1			T2	1		T3	16		T5	18
valid_sources[0x0a]	10103	1			T3	24		T5	17		T8	3
valid_sources[0x0b]	9048	1			T3	27		T5	16		T24	70
valid_sources[0x0c]	7690	1			T3	9		T5	19		T22	1
valid_sources[0x0d]	7397	1			T3	1		T5	16		T8	1
valid_sources[0x0e]	9503	1			T3	22		T5	15		T23	1
valid_sources[0x0f]	7842	1			T2	1		T3	1		T5	16
valid_sources[0x10]	7319	1			T2	2		T3	9		T5	17
valid_sources[0x11]	8624	1			T3	19		T5	17		T22	3
valid_sources[0x12]	8654	1			T3	23		T5	16		T24	2
valid_sources[0x13]	8530	1			T3	3		T4	15		T5	17
valid_sources[0x14]	7416	1			T2	1		T3	10		T5	18
valid_sources[0x15]	8229	1			T1	19		T3	18		T5	18
valid_sources[0x16]	7544	1			T3	18		T5	17		T24	9
valid_sources[0x17]	8362	1			T3	8		T5	15		T8	2
valid_sources[0x18]	7583	1			T3	11		T5	16		T24	11
valid_sources[0x19]	8338	1			T1	7		T3	24		T5	17
valid_sources[0x1a]	8463	1			T3	8		T4	17		T5	18
valid_sources[0x1b]	8582	1			T3	17		T5	18		T22	1
valid_sources[0x1c]	8697	1			T3	5		T5	16		T8	1
valid_sources[0x1d]	8469	1			T3	30		T5	16		T8	3
valid_sources[0x1e]	10955	1			T3	5		T5	17		T8	1
valid_sources[0x1f]	7682	1			T3	12		T5	18		T23	3
valid_sources[0x20]	7885	1			T3	19		T5	17		T19	2
valid_sources[0x21]	7578	1			T3	17		T5	15		T22	4
valid_sources[0x22]	7681	1			T3	21		T5	15		T8	1
valid_sources[0x23]	7531	1			T3	4		T5	16		T8	2
valid_sources[0x24]	8677	1			T3	8		T5	16		T23	1
valid_sources[0x25]	8630	1			T3	17		T5	17		T6	3
valid_sources[0x26]	7898	1			T3	3		T5	16		T8	5
valid_sources[0x27]	8009	1			T3	10		T5	18		T24	1
valid_sources[0x28]	8591	1			T3	11		T5	16		T24	76
valid_sources[0x29]	8023	1			T2	1		T3	8		T5	18
valid_sources[0x2a]	8498	1			T3	24		T5	17		T22	1
valid_sources[0x2b]	8705	1			T3	14		T5	17		T8	1
valid_sources[0x2c]	7399	1			T2	1		T3	5		T5	15
valid_sources[0x2d]	7848	1			T3	17		T5	16		T24	30
valid_sources[0x2e]	8742	1			T2	1		T3	5		T5	18
valid_sources[0x2f]	8103	1			T3	11		T5	17		T22	1
valid_sources[0x30]	8664	1			T2	1		T3	1		T5	16
valid_sources[0x31]	9107	1			T2	2		T3	23		T5	17
valid_sources[0x32]	8505	1			T3	14		T5	17		T23	1
valid_sources[0x33]	8558	1			T3	15		T5	15		T22	2
valid_sources[0x34]	8388	1			T3	5		T5	17		T8	1
valid_sources[0x35]	7342	1			T3	13		T5	17		T22	1
valid_sources[0x36]	7104	1			T5	16		T19	2		T20	4
valid_sources[0x37]	8129	1			T3	14		T5	17		T22	1
valid_sources[0x38]	8355	1			T3	4		T5	15		T24	33
valid_sources[0x39]	7892	1			T3	25		T5	19		T22	1
valid_sources[0x3a]	7414	1			T3	28		T5	18		T23	2
valid_sources[0x3b]	7664	1			T3	15		T5	19		T22	1
valid_sources[0x3c]	7850	1			T2	2		T3	39		T5	16
valid_sources[0x3d]	9343	1			T3	9		T5	17		T7	3
valid_sources[0x3e]	7831	1			T3	27		T5	16		T6	2
valid_sources[0x3f]	9506	1			T3	4		T5	17		T7	8
valid_sources[0x40]	9841	1			T1	7		T3	19		T5	18
valid_sources[0x41]	7939	1			T3	6		T5	17		T8	1
valid_sources[0x42]	7545	1			T3	10		T5	16		T8	1
valid_sources[0x43]	7670	1			T3	10		T5	18		T22	2
valid_sources[0x44]	8301	1			T3	10		T5	17		T22	3
valid_sources[0x45]	9087	1			T3	15		T4	19		T5	17
valid_sources[0x46]	8291	1			T3	17		T5	18		T18	60
valid_sources[0x47]	7725	1			T2	1		T3	12		T5	18
valid_sources[0x48]	8163	1			T3	14		T5	18		T8	2
valid_sources[0x49]	7633	1			T2	1		T3	27		T5	15
valid_sources[0x4a]	7903	1			T3	31		T5	17		T23	3
valid_sources[0x4b]	8079	1			T3	19		T5	17		T24	17
valid_sources[0x4c]	6868	1			T3	6		T5	17		T8	1
valid_sources[0x4d]	8621	1			T3	24		T5	18		T19	1
valid_sources[0x4e]	7742	1			T2	5		T3	5		T5	17
valid_sources[0x4f]	8724	1			T3	10		T5	18		T22	1
valid_sources[0x50]	7871	1			T3	13		T5	17		T20	2
valid_sources[0x51]	7957	1			T5	18		T7	3		T22	1
valid_sources[0x52]	8485	1			T3	20		T5	17		T22	2
valid_sources[0x53]	8897	1			T2	1		T3	7		T4	6
valid_sources[0x54]	7959	1			T3	10		T5	17		T23	3
valid_sources[0x55]	8624	1			T3	14		T5	18		T8	1
valid_sources[0x56]	8006	1			T3	3		T5	18		T22	3
valid_sources[0x57]	7853	1			T3	5		T5	19		T7	7
valid_sources[0x58]	7794	1			T1	16		T2	1		T3	13
valid_sources[0x59]	8600	1			T2	1		T5	17		T7	2
valid_sources[0x5a]	8322	1			T3	6		T5	15		T24	3
valid_sources[0x5b]	8278	1			T3	13		T5	17		T8	2
valid_sources[0x5c]	8104	1			T2	1		T3	5		T5	17
valid_sources[0x5d]	8884	1			T3	3		T5	17		T23	5
valid_sources[0x5e]	7880	1			T2	1		T3	14		T5	19
valid_sources[0x5f]	7595	1			T3	15		T5	14		T8	1
valid_sources[0x60]	8932	1			T3	14		T5	16		T6	4
valid_sources[0x61]	8520	1			T3	16		T5	17		T22	1
valid_sources[0x62]	8389	1			T3	7		T5	15		T22	1
valid_sources[0x63]	8077	1			T3	23		T5	18		T22	2
valid_sources[0x64]	9108	1			T2	1		T3	21		T5	17
valid_sources[0x65]	7752	1			T3	11		T5	18		T8	2
valid_sources[0x66]	7167	1			T3	10		T5	17		T20	2
valid_sources[0x67]	8588	1			T3	13		T5	18		T22	2
valid_sources[0x68]	8085	1			T2	2		T3	41		T5	17
valid_sources[0x69]	8720	1			T2	2		T3	40		T5	18
valid_sources[0x6a]	7431	1			T2	1		T3	14		T5	18
valid_sources[0x6b]	8101	1			T2	1		T3	14		T5	16
valid_sources[0x6c]	8084	1			T3	11		T5	17		T8	1
valid_sources[0x6d]	8823	1			T2	4		T3	16		T4	10
valid_sources[0x6e]	8286	1			T3	26		T5	18		T23	1
valid_sources[0x6f]	7745	1			T3	11		T5	15		T22	1
valid_sources[0x70]	7832	1			T1	8		T2	3		T5	16
valid_sources[0x71]	8904	1			T3	15		T5	18		T7	4
valid_sources[0x72]	8526	1			T3	21		T5	16		T23	2
valid_sources[0x73]	8222	1			T3	7		T5	17		T22	2
valid_sources[0x74]	10765	1			T2	1		T3	9		T5	17
valid_sources[0x75]	7864	1			T3	7		T5	15		T22	1
valid_sources[0x76]	7673	1			T1	15		T2	1		T3	20
valid_sources[0x77]	8474	1			T2	2		T3	18		T5	17
valid_sources[0x78]	7904	1			T3	16		T5	17		T19	1
valid_sources[0x79]	8515	1			T2	4		T3	11		T5	15
valid_sources[0x7a]	8885	1			T3	6		T5	17		T8	2
valid_sources[0x7b]	7539	1			T3	10		T5	18		T8	1
valid_sources[0x7c]	8174	1			T5	18		T23	1		T24	13
valid_sources[0x7d]	9021	1			T1	18		T3	8		T5	16
valid_sources[0x7e]	7531	1			T3	9		T5	19		T20	1
valid_sources[0x7f]	7524	1			T2	2		T3	27		T5	16
valid_sources[0x80]	8344	1			T2	1		T3	38		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30120

1

T1

4

T2

5

T3

39

values[0x0]

all_enables

biggest_size

226999

1

T1

21

T2

3

T3

395

values[0x1]

all_enables

biggest_size

30099

1

T1

4

T2

4

T3

34