Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	308422971	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	308422971	0	0
T1	390768	5368	0	0
T2	333928	9462	0	0
T3	3517584	72270	0	0
T4	7879648	183838	0	0
T5	20691216	1732834	0	0
T6	1439592	29703	0	0
T7	7888048	255279	0	0
T8	5127808	121314	0	0
T18	13521200	266723	0	0
T22	9454872	302318	0	0
T23	0	936	0	0
T24	0	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	390768	387632	0	0
T2	333928	325864	0	0
T3	3517584	3513384	0	0
T4	7879648	7877184	0	0
T5	20691216	20690824	0	0
T6	1439592	1438192	0	0
T7	7888048	7886592	0	0
T8	5127808	5122096	0	0
T18	13521200	13518512	0	0
T22	9454872	9452856	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	390768	387632	0	0
T2	333928	325864	0	0
T3	3517584	3513384	0	0
T4	7879648	7877184	0	0
T5	20691216	20690824	0	0
T6	1439592	1438192	0	0
T7	7888048	7886592	0	0
T8	5127808	5122096	0	0
T18	13521200	13518512	0	0
T22	9454872	9452856	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	390768	387632	0	0
T2	333928	325864	0	0
T3	3517584	3513384	0	0
T4	7879648	7877184	0	0
T5	20691216	20690824	0	0
T6	1439592	1438192	0	0
T7	7888048	7886592	0	0
T8	5127808	5122096	0	0
T18	13521200	13518512	0	0
T22	9454872	9452856	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T7	56	56	0	0
T8	56	56	0	0
T18	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	114940299	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	114940299	0	0
T1	6978	1322	0	0
T2	5963	2369	0	0
T3	62814	23221	0	0
T4	140708	75007	0	0
T5	369486	20141	0	0
T6	25707	13619	0	0
T7	140858	138980	0	0
T8	91568	48570	0	0
T18	241450	121083	0	0
T22	168837	166442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	78631375	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	78631375	0	0
T1	6978	1364	0	0
T2	5963	2369	0	0
T3	62814	12914	0	0
T4	140708	36046	0	0
T5	369486	153881	0	0
T6	25707	3565	0	0
T7	140858	57807	0	0
T8	91568	23873	0	0
T18	241450	41271	0	0
T22	168837	67514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1375124	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1375124	0	0
T1	6978	74	0	0
T2	5963	75	0	0
T3	62814	0	0	0
T4	140708	647	0	0
T5	369486	0	0	0
T6	25707	272	0	0
T7	140858	36	0	0
T8	91568	863	0	0
T18	241450	2573	0	0
T22	168837	1	0	0
T23	0	42	0	0
T24	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2562263	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2562263	0	0
T1	6978	74	0	0
T2	5963	75	0	0
T3	62814	0	0	0
T4	140708	2371	0	0
T5	369486	0	0	0
T6	25707	58	0	0
T7	140858	3354	0	0
T8	91568	883	0	0
T18	241450	1055	0	0
T22	168837	819	0	0
T23	0	9	0	0
T24	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1391942	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1391942	0	0
T1	6978	32	0	0
T2	5963	102	0	0
T3	62814	0	0	0
T4	140708	1625	0	0
T5	369486	1021	0	0
T6	25707	324	0	0
T7	140858	13	0	0
T8	91568	823	0	0
T18	241450	2694	0	0
T22	168837	26	0	0
T23	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2854498	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2854498	0	0
T1	6978	34	0	0
T2	5963	102	0	0
T3	62814	0	0	0
T4	140708	2514	0	0
T5	369486	87585	0	0
T6	25707	142	0	0
T7	140858	430	0	0
T8	91568	769	0	0
T18	241450	1903	0	0
T22	168837	1108	0	0
T23	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1388053	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1388053	0	0
T1	6978	97	0	0
T2	5963	99	0	0
T3	62814	0	0	0
T4	140708	1968	0	0
T5	369486	0	0	0
T6	25707	317	0	0
T7	140858	47	0	0
T8	91568	1042	0	0
T18	241450	1111	0	0
T22	168837	66	0	0
T23	0	13	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2385533	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2385533	0	0
T1	6978	72	0	0
T2	5963	99	0	0
T3	62814	0	0	0
T4	140708	2189	0	0
T5	369486	0	0	0
T6	25707	76	0	0
T7	140858	3241	0	0
T8	91568	1019	0	0
T18	241450	1198	0	0
T22	168837	3268	0	0
T23	0	4	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1345643	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1345643	0	0
T1	6978	49	0	0
T2	5963	113	0	0
T3	62814	1203	0	0
T4	140708	411	0	0
T5	369486	0	0	0
T6	25707	410	0	0
T7	140858	26	0	0
T8	91568	997	0	0
T18	241450	2294	0	0
T22	168837	5	0	0
T23	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2211864	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2211864	0	0
T1	6978	36	0	0
T2	5963	113	0	0
T3	62814	881	0	0
T4	140708	582	0	0
T5	369486	0	0	0
T6	25707	181	0	0
T7	140858	1849	0	0
T8	91568	1014	0	0
T18	241450	1031	0	0
T22	168837	1683	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1403828	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1403828	0	0
T1	6978	44	0	0
T2	5963	83	0	0
T3	62814	2277	0	0
T4	140708	611	0	0
T5	369486	1285	0	0
T6	25707	364	0	0
T7	140858	27	0	0
T8	91568	764	0	0
T18	241450	4045	0	0
T22	168837	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3399874	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3399874	0	0
T1	6978	76	0	0
T2	5963	83	0	0
T3	62814	986	0	0
T4	140708	1038	0	0
T5	369486	98104	0	0
T6	25707	93	0	0
T7	140858	2301	0	0
T8	91568	831	0	0
T18	241450	1818	0	0
T22	168837	3665	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1360591	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1360591	0	0
T1	6978	40	0	0
T2	5963	84	0	0
T3	62814	0	0	0
T4	140708	1083	0	0
T5	369486	1023	0	0
T6	25707	366	0	0
T7	140858	9	0	0
T8	91568	1160	0	0
T18	241450	2710	0	0
T22	168837	40	0	0
T23	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2436006	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2436006	0	0
T1	6978	76	0	0
T2	5963	84	0	0
T3	62814	0	0	0
T4	140708	1267	0	0
T5	369486	77198	0	0
T6	25707	141	0	0
T7	140858	837	0	0
T8	91568	1066	0	0
T18	241450	2399	0	0
T22	168837	3825	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1350614	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1350614	0	0
T1	6978	18	0	0
T2	5963	103	0	0
T3	62814	2218	0	0
T4	140708	2300	0	0
T5	369486	996	0	0
T6	25707	294	0	0
T7	140858	5	0	0
T8	91568	1030	0	0
T18	241450	1441	0	0
T22	168837	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3002095	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3002095	0	0
T1	6978	22	0	0
T2	5963	103	0	0
T3	62814	1033	0	0
T4	140708	2534	0	0
T5	369486	79579	0	0
T6	25707	151	0	0
T7	140858	584	0	0
T8	91568	920	0	0
T18	241450	239	0	0
T22	168837	1563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1357269	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1357269	0	0
T1	6978	24	0	0
T2	5963	85	0	0
T3	62814	2193	0	0
T4	140708	3183	0	0
T5	369486	2616	0	0
T6	25707	268	0	0
T7	140858	38	0	0
T8	91568	955	0	0
T18	241450	2884	0	0
T22	168837	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2549793	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2549793	0	0
T1	6978	17	0	0
T2	5963	85	0	0
T3	62814	1886	0	0
T4	140708	2067	0	0
T5	369486	189358	0	0
T6	25707	116	0	0
T7	140858	1855	0	0
T8	91568	804	0	0
T18	241450	1897	0	0
T22	168837	4619	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1397985	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1397985	0	0
T1	6978	80	0	0
T2	5963	100	0	0
T3	62814	0	0	0
T4	140708	1741	0	0
T5	369486	0	0	0
T6	25707	340	0	0
T7	140858	18	0	0
T8	91568	924	0	0
T18	241450	902	0	0
T22	168837	17	0	0
T23	0	27	0	0
T24	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2580639	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2580639	0	0
T1	6978	97	0	0
T2	5963	100	0	0
T3	62814	0	0	0
T4	140708	238	0	0
T5	369486	0	0	0
T6	25707	149	0	0
T7	140858	3035	0	0
T8	91568	921	0	0
T18	241450	1655	0	0
T22	168837	1891	0	0
T23	0	274	0	0
T24	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1454752	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1454752	0	0
T1	6978	27	0	0
T2	5963	68	0	0
T3	62814	2296	0	0
T4	140708	1116	0	0
T5	369486	0	0	0
T6	25707	354	0	0
T7	140858	17	0	0
T8	91568	915	0	0
T18	241450	2377	0	0
T22	168837	55	0	0
T23	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3465748	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3465748	0	0
T1	6978	40	0	0
T2	5963	68	0	0
T3	62814	1692	0	0
T4	140708	1234	0	0
T5	369486	0	0	0
T6	25707	137	0	0
T7	140858	1057	0	0
T8	91568	793	0	0
T18	241450	2215	0	0
T22	168837	3534	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1352536	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1352536	0	0
T1	6978	43	0	0
T2	5963	78	0	0
T3	62814	0	0	0
T4	140708	1943	0	0
T5	369486	1080	0	0
T6	25707	377	0	0
T7	140858	39	0	0
T8	91568	893	0	0
T18	241450	2005	0	0
T22	168837	40	0	0
T23	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2671892	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2671892	0	0
T1	6978	66	0	0
T2	5963	78	0	0
T3	62814	0	0	0
T4	140708	1234	0	0
T5	369486	84044	0	0
T6	25707	196	0	0
T7	140858	2467	0	0
T8	91568	921	0	0
T18	241450	2624	0	0
T22	168837	1862	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1377060	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1377060	0	0
T1	6978	107	0	0
T2	5963	93	0	0
T3	62814	0	0	0
T4	140708	1621	0	0
T5	369486	1002	0	0
T6	25707	241	0	0
T7	140858	40	0	0
T8	91568	769	0	0
T18	241450	2550	0	0
T22	168837	42	0	0
T23	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3308721	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3308721	0	0
T1	6978	102	0	0
T2	5963	93	0	0
T3	62814	0	0	0
T4	140708	384	0	0
T5	369486	76044	0	0
T6	25707	106	0	0
T7	140858	1828	0	0
T8	91568	776	0	0
T18	241450	2491	0	0
T22	168837	3898	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1378488	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1378488	0	0
T1	6978	32	0	0
T2	5963	86	0	0
T3	62814	0	0	0
T4	140708	257	0	0
T5	369486	0	0	0
T6	25707	380	0	0
T7	140858	18	0	0
T8	91568	719	0	0
T18	241450	1463	0	0
T22	168837	9	0	0
T23	0	17	0	0
T24	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2881347	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2881347	0	0
T1	6978	35	0	0
T2	5963	86	0	0
T3	62814	0	0	0
T4	140708	565	0	0
T5	369486	0	0	0
T6	25707	153	0	0
T7	140858	1434	0	0
T8	91568	798	0	0
T18	241450	930	0	0
T22	168837	618	0	0
T23	0	3	0	0
T24	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1336488	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1336488	0	0
T1	6978	43	0	0
T2	5963	78	0	0
T3	62814	2320	0	0
T4	140708	1077	0	0
T5	369486	1306	0	0
T6	25707	312	0	0
T7	140858	12	0	0
T8	91568	983	0	0
T18	241450	759	0	0
T22	168837	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2773934	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2773934	0	0
T1	6978	68	0	0
T2	5963	78	0	0
T3	62814	996	0	0
T4	140708	840	0	0
T5	369486	107275	0	0
T6	25707	140	0	0
T7	140858	2283	0	0
T8	91568	891	0	0
T18	241450	924	0	0
T22	168837	1909	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1379918	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1379918	0	0
T1	6978	76	0	0
T2	5963	77	0	0
T3	62814	6193	0	0
T4	140708	2491	0	0
T5	369486	1195	0	0
T6	25707	394	0	0
T7	140858	27	0	0
T8	91568	944	0	0
T18	241450	1480	0	0
T22	168837	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3038173	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3038173	0	0
T1	6978	52	0	0
T2	5963	77	0	0
T3	62814	2723	0	0
T4	140708	1908	0	0
T5	369486	84510	0	0
T6	25707	125	0	0
T7	140858	2639	0	0
T8	91568	784	0	0
T18	241450	1204	0	0
T22	168837	3360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1374145	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1374145	0	0
T1	6978	55	0	0
T2	5963	86	0	0
T3	62814	0	0	0
T4	140708	1694	0	0
T5	369486	989	0	0
T6	25707	407	0	0
T7	140858	38	0	0
T8	91568	1132	0	0
T18	241450	1084	0	0
T22	168837	45	0	0
T23	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3021255	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3021255	0	0
T1	6978	60	0	0
T2	5963	86	0	0
T3	62814	0	0	0
T4	140708	1398	0	0
T5	369486	74415	0	0
T6	25707	140	0	0
T7	140858	5119	0	0
T8	91568	946	0	0
T18	241450	2243	0	0
T22	168837	5086	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1403060	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1403060	0	0
T1	6978	70	0	0
T2	5963	95	0	0
T3	62814	1863	0	0
T4	140708	1479	0	0
T5	369486	0	0	0
T6	25707	308	0	0
T7	140858	27	0	0
T8	91568	886	0	0
T18	241450	3824	0	0
T22	168837	26	0	0
T23	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2981408	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2981408	0	0
T1	6978	49	0	0
T2	5963	95	0	0
T3	62814	739	0	0
T4	140708	1068	0	0
T5	369486	0	0	0
T6	25707	191	0	0
T7	140858	1786	0	0
T8	91568	785	0	0
T18	241450	1603	0	0
T22	168837	1501	0	0
T23	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1405031	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1405031	0	0
T1	6978	49	0	0
T2	5963	82	0	0
T3	62814	0	0	0
T4	140708	1543	0	0
T5	369486	1209	0	0
T6	25707	370	0	0
T7	140858	23	0	0
T8	91568	979	0	0
T18	241450	3230	0	0
T22	168837	28	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2782238	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2782238	0	0
T1	6978	43	0	0
T2	5963	82	0	0
T3	62814	0	0	0
T4	140708	1587	0	0
T5	369486	88473	0	0
T6	25707	147	0	0
T7	140858	2067	0	0
T8	91568	956	0	0
T18	241450	1295	0	0
T22	168837	2018	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1308565	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1308565	0	0
T1	6978	52	0	0
T2	5963	78	0	0
T3	62814	0	0	0
T4	140708	1316	0	0
T5	369486	0	0	0
T6	25707	258	0	0
T7	140858	22	0	0
T8	91568	836	0	0
T18	241450	1981	0	0
T22	168837	15	0	0
T23	0	16	0	0
T24	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2969146	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2969146	0	0
T1	6978	56	0	0
T2	5963	78	0	0
T3	62814	0	0	0
T4	140708	1852	0	0
T5	369486	0	0	0
T6	25707	108	0	0
T7	140858	2040	0	0
T8	91568	701	0	0
T18	241450	1063	0	0
T22	168837	1573	0	0
T23	0	4	0	0
T24	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1421063	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1421063	0	0
T1	6978	20	0	0
T2	5963	87	0	0
T3	62814	0	0	0
T4	140708	676	0	0
T5	369486	0	0	0
T6	25707	312	0	0
T7	140858	19	0	0
T8	91568	955	0	0
T18	241450	2527	0	0
T22	168837	29	0	0
T23	0	31	0	0
T24	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2470392	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2470392	0	0
T1	6978	49	0	0
T2	5963	87	0	0
T3	62814	0	0	0
T4	140708	921	0	0
T5	369486	0	0	0
T6	25707	131	0	0
T7	140858	2597	0	0
T8	91568	988	0	0
T18	241450	16	0	0
T22	168837	2905	0	0
T23	0	6	0	0
T24	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1378049	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1378049	0	0
T1	6978	52	0	0
T2	5963	67	0	0
T3	62814	0	0	0
T4	140708	1234	0	0
T5	369486	0	0	0
T6	25707	312	0	0
T7	140858	2	0	0
T8	91568	897	0	0
T18	241450	1366	0	0
T22	168837	17	0	0
T23	0	32	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2787790	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2787790	0	0
T1	6978	54	0	0
T2	5963	67	0	0
T3	62814	0	0	0
T4	140708	1584	0	0
T5	369486	0	0	0
T6	25707	124	0	0
T7	140858	8	0	0
T8	91568	911	0	0
T18	241450	1888	0	0
T22	168837	1607	0	0
T23	0	5	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1412936	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1412936	0	0
T1	6978	25	0	0
T2	5963	84	0	0
T3	62814	0	0	0
T4	140708	1630	0	0
T5	369486	0	0	0
T6	25707	319	0	0
T7	140858	20	0	0
T8	91568	984	0	0
T18	241450	3303	0	0
T22	168837	31	0	0
T23	0	65	0	0
T24	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2520007	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2520007	0	0
T1	6978	13	0	0
T2	5963	84	0	0
T3	62814	0	0	0
T4	140708	691	0	0
T5	369486	0	0	0
T6	25707	125	0	0
T7	140858	1564	0	0
T8	91568	1120	0	0
T18	241450	2046	0	0
T22	168837	1929	0	0
T23	0	12	0	0
T24	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1412416	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1412416	0	0
T1	6978	21	0	0
T2	5963	106	0	0
T3	62814	1209	0	0
T4	140708	1543	0	0
T5	369486	2466	0	0
T6	25707	299	0	0
T7	140858	31	0	0
T8	91568	744	0	0
T18	241450	1459	0	0
T22	168837	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3717669	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3717669	0	0
T1	6978	12	0	0
T2	5963	106	0	0
T3	62814	933	0	0
T4	140708	1618	0	0
T5	369486	198437	0	0
T6	25707	129	0	0
T7	140858	3074	0	0
T8	91568	635	0	0
T18	241450	445	0	0
T22	168837	2107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1422558	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1422558	0	0
T1	6978	79	0	0
T2	5963	71	0	0
T3	62814	0	0	0
T4	140708	849	0	0
T5	369486	1306	0	0
T6	25707	307	0	0
T7	140858	42	0	0
T8	91568	1003	0	0
T18	241450	2608	0	0
T22	168837	45	0	0
T23	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2869993	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2869993	0	0
T1	6978	41	0	0
T2	5963	71	0	0
T3	62814	0	0	0
T4	140708	2018	0	0
T5	369486	95683	0	0
T6	25707	102	0	0
T7	140858	2442	0	0
T8	91568	965	0	0
T18	241450	2157	0	0
T22	168837	3737	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1388371	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1388371	0	0
T1	6978	74	0	0
T2	5963	99	0	0
T3	62814	0	0	0
T4	140708	787	0	0
T5	369486	1278	0	0
T6	25707	321	0	0
T7	140858	43	0	0
T8	91568	1001	0	0
T18	241450	1985	0	0
T22	168837	41	0	0
T23	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	3675598	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	3675598	0	0
T1	6978	50	0	0
T2	5963	99	0	0
T3	62814	0	0	0
T4	140708	1338	0	0
T5	369486	98935	0	0
T6	25707	151	0	0
T7	140858	2576	0	0
T8	91568	908	0	0
T18	241450	784	0	0
T22	168837	2199	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1343494	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1343494	0	0
T1	6978	11	0	0
T2	5963	89	0	0
T3	62814	0	0	0
T4	140708	447	0	0
T5	369486	1295	0	0
T6	25707	382	0	0
T7	140858	33	0	0
T8	91568	977	0	0
T18	241450	2869	0	0
T22	168837	36	0	0
T23	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2870532	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2870532	0	0
T1	6978	20	0	0
T2	5963	89	0	0
T3	62814	0	0	0
T4	140708	339	0	0
T5	369486	99105	0	0
T6	25707	108	0	0
T7	140858	4542	0	0
T8	91568	947	0	0
T18	241450	1534	0	0
T22	168837	2768	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	1358970	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	1358970	0	0
T1	6978	26	0	0
T2	5963	94	0	0
T3	62814	1449	0	0
T4	140708	1467	0	0
T5	369486	0	0	0
T6	25707	346	0	0
T7	140858	13	0	0
T8	91568	823	0	0
T18	241450	5574	0	0
T22	168837	32	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	286828344	2783940	0	0
DepthKnown_A	286828344	286706931	0	0
RvalidKnown_A	286828344	286706931	0	0
WreadyKnown_A	286828344	286706931	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	2783940	0	0
T1	6978	48	0	0
T2	5963	94	0	0
T3	62814	1045	0	0
T4	140708	667	0	0
T5	369486	0	0	0
T6	25707	145	0	0
T7	140858	798	0	0
T8	91568	821	0	0
T18	241450	2614	0	0
T22	168837	2462	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286828344	286706931	0	0
T1	6978	6922	0	0
T2	5963	5819	0	0
T3	62814	62739	0	0
T4	140708	140664	0	0
T5	369486	369479	0	0
T6	25707	25682	0	0
T7	140858	140832	0	0
T8	91568	91466	0	0
T18	241450	241402	0	0
T22	168837	168801	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0