Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1653304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260100

1

T1

21

T2

414

T3

291

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	646647	1			T1	48		T2	1022		T3	629
values[0x0]	618752	1			T1	11		T2	999		T3	637
values[0x1]	648005	1			T1	51		T2	980		T3	605

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1281315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632089

1

T1

51

T2

994

T3

620

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6803	1			T2	1		T3	8		T13	22
valid_sources[0x01]	7763	1			T1	1		T3	6		T13	13
valid_sources[0x02]	7453	1			T3	11		T13	3		T17	1
valid_sources[0x03]	7305	1			T3	7		T16	1		T17	5
valid_sources[0x04]	7558	1			T2	13		T3	4		T13	1
valid_sources[0x05]	7798	1			T3	10		T13	13		T16	1
valid_sources[0x06]	7133	1			T1	1		T3	7		T13	14
valid_sources[0x07]	6978	1			T1	1		T2	12		T3	10
valid_sources[0x08]	6917	1			T3	8		T13	17		T14	7
valid_sources[0x09]	7178	1			T3	5		T13	12		T16	2
valid_sources[0x0a]	7615	1			T1	1		T3	10		T16	2
valid_sources[0x0b]	7438	1			T3	7		T13	4		T16	2
valid_sources[0x0c]	7063	1			T3	7		T13	10		T16	2
valid_sources[0x0d]	7356	1			T2	13		T3	13		T16	1
valid_sources[0x0e]	7311	1			T1	1		T2	8		T3	6
valid_sources[0x0f]	7994	1			T3	11		T13	14		T16	3
valid_sources[0x10]	8016	1			T2	1		T3	3		T13	5
valid_sources[0x11]	6906	1			T3	7		T13	25		T17	1
valid_sources[0x12]	8080	1			T1	1		T2	18		T3	8
valid_sources[0x13]	7240	1			T1	1		T3	5		T13	9
valid_sources[0x14]	7989	1			T1	1		T3	5		T13	11
valid_sources[0x15]	7076	1			T2	34		T3	4		T17	1
valid_sources[0x16]	7148	1			T1	1		T2	19		T3	8
valid_sources[0x17]	7507	1			T1	2		T2	13		T3	6
valid_sources[0x18]	7450	1			T3	9		T13	8		T16	1
valid_sources[0x19]	8227	1			T3	2		T16	1		T17	1
valid_sources[0x1a]	7229	1			T2	48		T3	5		T13	7
valid_sources[0x1b]	6884	1			T3	7		T13	5		T17	1
valid_sources[0x1c]	7366	1			T3	9		T13	3		T17	2
valid_sources[0x1d]	8091	1			T3	7		T13	5		T14	13
valid_sources[0x1e]	7092	1			T2	253		T3	6		T17	1
valid_sources[0x1f]	6654	1			T2	14		T3	8		T13	4
valid_sources[0x20]	7022	1			T3	4		T13	6		T17	2
valid_sources[0x21]	7229	1			T1	1		T2	23		T3	6
valid_sources[0x22]	7307	1			T2	1		T3	7		T13	12
valid_sources[0x23]	7834	1			T2	1		T3	6		T13	25
valid_sources[0x24]	7436	1			T3	9		T13	13		T16	1
valid_sources[0x25]	7077	1			T2	2		T3	5		T16	1
valid_sources[0x26]	8085	1			T1	2		T2	3		T3	5
valid_sources[0x27]	7475	1			T2	10		T3	2		T13	10
valid_sources[0x28]	7095	1			T3	6		T17	13		T14	6
valid_sources[0x29]	7195	1			T2	5		T3	7		T13	9
valid_sources[0x2a]	7441	1			T2	6		T3	5		T13	1
valid_sources[0x2b]	7148	1			T1	1		T2	1		T3	8
valid_sources[0x2c]	6846	1			T3	11		T13	7		T14	5
valid_sources[0x2d]	7031	1			T3	9		T13	4		T16	1
valid_sources[0x2e]	7511	1			T2	1		T3	3		T13	3
valid_sources[0x2f]	7442	1			T3	3		T13	25		T17	3
valid_sources[0x30]	7109	1			T3	2		T13	1		T16	1
valid_sources[0x31]	7433	1			T1	1		T3	6		T13	20
valid_sources[0x32]	7306	1			T2	32		T3	9		T13	12
valid_sources[0x33]	7725	1			T2	20		T3	6		T17	3
valid_sources[0x34]	6965	1			T3	13		T13	21		T16	1
valid_sources[0x35]	7437	1			T1	3		T3	4		T13	26
valid_sources[0x36]	7510	1			T1	1		T2	1		T3	9
valid_sources[0x37]	7710	1			T3	6		T13	9		T17	6
valid_sources[0x38]	7334	1			T3	5		T13	22		T20	12
valid_sources[0x39]	7062	1			T3	9		T13	24		T16	1
valid_sources[0x3a]	7497	1			T3	8		T13	3		T17	1
valid_sources[0x3b]	7010	1			T3	7		T13	7		T16	1
valid_sources[0x3c]	7102	1			T3	9		T13	9		T16	1
valid_sources[0x3d]	7601	1			T1	2		T3	8		T13	23
valid_sources[0x3e]	7397	1			T2	18		T3	8		T13	3
valid_sources[0x3f]	7014	1			T1	1		T3	5		T13	9
valid_sources[0x40]	7468	1			T1	1		T3	11		T13	2
valid_sources[0x41]	7112	1			T1	1		T3	13		T13	7
valid_sources[0x42]	7373	1			T3	6		T17	1		T14	8
valid_sources[0x43]	7429	1			T3	5		T13	20		T16	2
valid_sources[0x44]	7354	1			T2	1		T3	11		T13	17
valid_sources[0x45]	7557	1			T2	1		T3	7		T13	7
valid_sources[0x46]	7144	1			T1	1		T3	5		T13	5
valid_sources[0x47]	7734	1			T1	1		T3	7		T13	9
valid_sources[0x48]	7679	1			T1	1		T3	15		T13	10
valid_sources[0x49]	7313	1			T1	1		T3	6		T13	12
valid_sources[0x4a]	7523	1			T1	1		T3	12		T13	6
valid_sources[0x4b]	7205	1			T2	1		T3	5		T13	6
valid_sources[0x4c]	6693	1			T2	34		T3	3		T13	8
valid_sources[0x4d]	6764	1			T1	1		T3	7		T4	29
valid_sources[0x4e]	6926	1			T2	11		T3	9		T13	21
valid_sources[0x4f]	7226	1			T2	1		T3	14		T13	7
valid_sources[0x50]	8622	1			T1	3		T3	4		T13	1
valid_sources[0x51]	6962	1			T2	1		T3	5		T14	4
valid_sources[0x52]	7012	1			T3	8		T13	10		T14	6
valid_sources[0x53]	7948	1			T1	2		T2	1		T3	10
valid_sources[0x54]	8395	1			T1	1		T2	1		T3	4
valid_sources[0x55]	8485	1			T2	1		T3	7		T17	1
valid_sources[0x56]	8373	1			T3	9		T13	5		T16	1
valid_sources[0x57]	7222	1			T3	7		T13	12		T16	1
valid_sources[0x58]	7659	1			T1	1		T3	5		T13	8
valid_sources[0x59]	8170	1			T1	1		T3	7		T13	15
valid_sources[0x5a]	7709	1			T1	2		T3	6		T13	6
valid_sources[0x5b]	7123	1			T1	1		T3	7		T13	2
valid_sources[0x5c]	6960	1			T1	1		T2	445		T3	8
valid_sources[0x5d]	7265	1			T3	8		T13	8		T14	2
valid_sources[0x5e]	7743	1			T2	13		T3	9		T13	10
valid_sources[0x5f]	8030	1			T3	8		T13	5		T14	4
valid_sources[0x60]	6998	1			T3	6		T13	10		T17	3
valid_sources[0x61]	7219	1			T1	2		T3	11		T13	10
valid_sources[0x62]	9614	1			T3	8		T13	13		T14	9
valid_sources[0x63]	7855	1			T3	6		T13	18		T17	1
valid_sources[0x64]	6801	1			T3	6		T13	15		T16	1
valid_sources[0x65]	7507	1			T2	40		T3	3		T13	22
valid_sources[0x66]	7793	1			T2	1		T3	8		T14	5
valid_sources[0x67]	8380	1			T3	9		T13	1		T16	2
valid_sources[0x68]	8649	1			T3	9		T13	7		T16	1
valid_sources[0x69]	7429	1			T1	1		T3	12		T13	4
valid_sources[0x6a]	7069	1			T3	6		T13	1		T16	1
valid_sources[0x6b]	7455	1			T1	1		T3	11		T13	10
valid_sources[0x6c]	7187	1			T3	3		T13	8		T16	1
valid_sources[0x6d]	7538	1			T3	14		T13	12		T16	1
valid_sources[0x6e]	7714	1			T2	284		T3	13		T13	2
valid_sources[0x6f]	6904	1			T3	5		T13	9		T17	3
valid_sources[0x70]	7620	1			T1	2		T3	7		T13	5
valid_sources[0x71]	6581	1			T1	1		T3	9		T13	1
valid_sources[0x72]	7879	1			T3	9		T13	1		T14	6
valid_sources[0x73]	7945	1			T2	131		T3	7		T13	3
valid_sources[0x74]	8613	1			T2	2		T3	5		T13	14
valid_sources[0x75]	7170	1			T3	11		T13	16		T17	2
valid_sources[0x76]	8418	1			T3	1		T13	16		T14	12
valid_sources[0x77]	6958	1			T1	1		T2	1		T3	4
valid_sources[0x78]	8092	1			T3	9		T13	2		T16	1
valid_sources[0x79]	7837	1			T3	8		T13	2		T16	2
valid_sources[0x7a]	7512	1			T2	13		T3	6		T13	10
valid_sources[0x7b]	8017	1			T1	1		T2	118		T3	11
valid_sources[0x7c]	7613	1			T2	2		T3	3		T13	2
valid_sources[0x7d]	7031	1			T3	8		T13	6		T17	1
valid_sources[0x7e]	7321	1			T1	2		T3	4		T13	24
valid_sources[0x7f]	7579	1			T3	12		T13	21		T14	3
valid_sources[0x80]	6663	1			T3	8		T13	5		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27401

1

T1

4

T2

44

T3

37

values[0x0]

all_enables

biggest_size

205176

1

T1

6

T2

326

T3

227

values[0x1]

all_enables

biggest_size

27523

1

T1

11

T2

44

T3

27