Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	331805095	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	331805095	0	0
T1	3724896	80374	0	0
T2	259056	13138	0	0
T3	2195200	60276	0	0
T4	158480	2467	0	0
T13	263368	11278	0	0
T14	2285304	47298	0	0
T15	190792	6604	0	0
T16	11095504	192587	0	0
T17	75600	2203	0	0
T18	1175160	17284	0	0
T19	0	4548	0	0
T20	0	14739	0	0
T21	0	17438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3724896	3723440	0	0
T2	259056	256256	0	0
T3	2195200	2190608	0	0
T4	158480	155680	0	0
T13	263368	261632	0	0
T14	2285304	2284912	0	0
T15	190792	189952	0	0
T16	11095504	11091696	0	0
T17	75600	72240	0	0
T18	1175160	1173480	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3724896	3723440	0	0
T2	259056	256256	0	0
T3	2195200	2190608	0	0
T4	158480	155680	0	0
T13	263368	261632	0	0
T14	2285304	2284912	0	0
T15	190792	189952	0	0
T16	11095504	11091696	0	0
T17	75600	72240	0	0
T18	1175160	1173480	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3724896	3723440	0	0
T2	259056	256256	0	0
T3	2195200	2190608	0	0
T4	158480	155680	0	0
T13	263368	261632	0	0
T14	2285304	2284912	0	0
T15	190792	189952	0	0
T16	11095504	11091696	0	0
T17	75600	72240	0	0
T18	1175160	1173480	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	124758152	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	124758152	0	0
T1	66516	34713	0	0
T2	4626	4337	0	0
T3	39200	14231	0	0
T4	2830	1126	0	0
T13	4703	4395	0	0
T14	40809	17327	0	0
T15	3407	3237	0	0
T16	198134	94239	0	0
T17	1350	862	0	0
T18	20985	7940	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	84234839	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	84234839	0	0
T1	66516	14162	0	0
T2	4626	3001	0	0
T3	39200	15907	0	0
T4	2830	309	0	0
T13	4703	2295	0	0
T14	40809	15801	0	0
T15	3407	1653	0	0
T16	198134	18049	0	0
T17	1350	447	0	0
T18	20985	2596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1425586	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1425586	0	0
T1	66516	673	0	0
T2	4626	287	0	0
T3	39200	0	0	0
T4	2830	14	0	0
T13	4703	79	0	0
T14	40809	270	0	0
T15	3407	41	0	0
T16	198134	2160	0	0
T17	1350	18	0	0
T18	20985	302	0	0
T21	0	1303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3434416	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3434416	0	0
T1	66516	546	0	0
T2	4626	287	0	0
T3	39200	0	0	0
T4	2830	3	0	0
T13	4703	79	0	0
T14	40809	196	0	0
T15	3407	41	0	0
T16	198134	1330	0	0
T17	1350	18	0	0
T18	20985	100	0	0
T21	0	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1479764	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1479764	0	0
T1	66516	699	0	0
T2	4626	23	0	0
T3	39200	0	0	0
T4	2830	22	0	0
T13	4703	88	0	0
T14	40809	319	0	0
T15	3407	37	0	0
T16	198134	2597	0	0
T17	1350	16	0	0
T18	20985	142	0	0
T20	0	1394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3313754	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3313754	0	0
T1	66516	545	0	0
T2	4626	23	0	0
T3	39200	0	0	0
T4	2830	18	0	0
T13	4703	88	0	0
T14	40809	331	0	0
T15	3407	37	0	0
T16	198134	960	0	0
T17	1350	16	0	0
T18	20985	60	0	0
T20	0	956	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1517059	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1517059	0	0
T1	66516	585	0	0
T2	4626	36	0	0
T3	39200	2141	0	0
T4	2830	66	0	0
T13	4703	100	0	0
T14	40809	190	0	0
T15	3407	28	0	0
T16	198134	1907	0	0
T17	1350	22	0	0
T18	20985	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3180088	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3180088	0	0
T1	66516	533	0	0
T2	4626	36	0	0
T3	39200	2183	0	0
T4	2830	26	0	0
T13	4703	100	0	0
T14	40809	167	0	0
T15	3407	28	0	0
T16	198134	772	0	0
T17	1350	22	0	0
T18	20985	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1475452	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1475452	0	0
T1	66516	530	0	0
T2	4626	37	0	0
T3	39200	0	0	0
T4	2830	9	0	0
T13	4703	88	0	0
T14	40809	338	0	0
T15	3407	39	0	0
T16	198134	189	0	0
T17	1350	11	0	0
T18	20985	116	0	0
T20	0	2163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3388269	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3388269	0	0
T1	66516	495	0	0
T2	4626	37	0	0
T3	39200	0	0	0
T4	2830	1	0	0
T13	4703	88	0	0
T14	40809	242	0	0
T15	3407	39	0	0
T16	198134	60	0	0
T17	1350	11	0	0
T18	20985	47	0	0
T20	0	821	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1450201	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1450201	0	0
T1	66516	621	0	0
T2	4626	30	0	0
T3	39200	0	0	0
T4	2830	13	0	0
T13	4703	93	0	0
T14	40809	307	0	0
T15	3407	26	0	0
T16	198134	1467	0	0
T17	1350	18	0	0
T18	20985	136	0	0
T19	0	281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3094217	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3094217	0	0
T1	66516	574	0	0
T2	4626	30	0	0
T3	39200	0	0	0
T4	2830	3	0	0
T13	4703	93	0	0
T14	40809	191	0	0
T15	3407	26	0	0
T16	198134	339	0	0
T17	1350	18	0	0
T18	20985	75	0	0
T19	0	281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1457257	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1457257	0	0
T1	66516	688	0	0
T2	4626	297	0	0
T3	39200	1366	0	0
T4	2830	21	0	0
T13	4703	84	0	0
T14	40809	256	0	0
T15	3407	19	0	0
T16	198134	2845	0	0
T17	1350	16	0	0
T18	20985	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2671138	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2671138	0	0
T1	66516	564	0	0
T2	4626	297	0	0
T3	39200	1806	0	0
T4	2830	15	0	0
T13	4703	84	0	0
T14	40809	289	0	0
T15	3407	19	0	0
T16	198134	1415	0	0
T17	1350	16	0	0
T18	20985	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1455681	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1455681	0	0
T1	66516	611	0	0
T2	4626	551	0	0
T3	39200	0	0	0
T4	2830	11	0	0
T13	4703	101	0	0
T14	40809	256	0	0
T15	3407	33	0	0
T16	198134	933	0	0
T17	1350	13	0	0
T18	20985	132	0	0
T21	0	2265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2658168	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2658168	0	0
T1	66516	546	0	0
T2	4626	551	0	0
T3	39200	0	0	0
T4	2830	2	0	0
T13	4703	101	0	0
T14	40809	174	0	0
T15	3407	33	0	0
T16	198134	53	0	0
T17	1350	13	0	0
T18	20985	53	0	0
T21	0	1269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1458008	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1458008	0	0
T1	66516	640	0	0
T2	4626	28	0	0
T3	39200	1936	0	0
T4	2830	44	0	0
T13	4703	95	0	0
T14	40809	272	0	0
T15	3407	25	0	0
T16	198134	3009	0	0
T17	1350	15	0	0
T18	20985	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2781350	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2781350	0	0
T1	66516	547	0	0
T2	4626	28	0	0
T3	39200	1926	0	0
T4	2830	16	0	0
T13	4703	95	0	0
T14	40809	275	0	0
T15	3407	25	0	0
T16	198134	238	0	0
T17	1350	15	0	0
T18	20985	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1445223	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1445223	0	0
T1	66516	851	0	0
T2	4626	33	0	0
T3	39200	2150	0	0
T4	2830	38	0	0
T13	4703	71	0	0
T14	40809	238	0	0
T15	3407	30	0	0
T16	198134	2914	0	0
T17	1350	20	0	0
T18	20985	183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3081307	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3081307	0	0
T1	66516	732	0	0
T2	4626	33	0	0
T3	39200	2152	0	0
T4	2830	29	0	0
T13	4703	71	0	0
T14	40809	231	0	0
T15	3407	30	0	0
T16	198134	1228	0	0
T17	1350	20	0	0
T18	20985	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1455894	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1455894	0	0
T1	66516	751	0	0
T2	4626	28	0	0
T3	39200	1488	0	0
T4	2830	38	0	0
T13	4703	75	0	0
T14	40809	383	0	0
T15	3407	27	0	0
T16	198134	5001	0	0
T17	1350	20	0	0
T18	20985	200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3556152	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3556152	0	0
T1	66516	570	0	0
T2	4626	28	0	0
T3	39200	2126	0	0
T4	2830	18	0	0
T13	4703	75	0	0
T14	40809	302	0	0
T15	3407	27	0	0
T16	198134	1038	0	0
T17	1350	20	0	0
T18	20985	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1425519	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1425519	0	0
T1	66516	743	0	0
T2	4626	271	0	0
T3	39200	0	0	0
T4	2830	40	0	0
T13	4703	83	0	0
T14	40809	299	0	0
T15	3407	41	0	0
T16	198134	2410	0	0
T17	1350	16	0	0
T18	20985	133	0	0
T21	0	676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2714498	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2714498	0	0
T1	66516	595	0	0
T2	4626	271	0	0
T3	39200	0	0	0
T4	2830	6	0	0
T13	4703	83	0	0
T14	40809	304	0	0
T15	3407	41	0	0
T16	198134	2043	0	0
T17	1350	16	0	0
T18	20985	76	0	0
T21	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1539461	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1539461	0	0
T1	66516	552	0	0
T2	4626	306	0	0
T3	39200	0	0	0
T4	2830	36	0	0
T13	4703	87	0	0
T14	40809	321	0	0
T15	3407	31	0	0
T16	198134	1583	0	0
T17	1350	9	0	0
T18	20985	185	0	0
T21	0	2285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2994428	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2994428	0	0
T1	66516	411	0	0
T2	4626	306	0	0
T3	39200	0	0	0
T4	2830	28	0	0
T13	4703	87	0	0
T14	40809	365	0	0
T15	3407	31	0	0
T16	198134	679	0	0
T17	1350	9	0	0
T18	20985	108	0	0
T21	0	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1478411	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1478411	0	0
T1	66516	662	0	0
T2	4626	24	0	0
T3	39200	1483	0	0
T4	2830	22	0	0
T13	4703	75	0	0
T14	40809	281	0	0
T15	3407	26	0	0
T16	198134	3479	0	0
T17	1350	17	0	0
T18	20985	201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3472485	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3472485	0	0
T1	66516	490	0	0
T2	4626	24	0	0
T3	39200	1743	0	0
T4	2830	6	0	0
T13	4703	75	0	0
T14	40809	303	0	0
T15	3407	26	0	0
T16	198134	775	0	0
T17	1350	17	0	0
T18	20985	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1464079	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1464079	0	0
T1	66516	717	0	0
T2	4626	22	0	0
T3	39200	0	0	0
T4	2830	65	0	0
T13	4703	76	0	0
T14	40809	328	0	0
T15	3407	34	0	0
T16	198134	773	0	0
T17	1350	20	0	0
T18	20985	180	0	0
T21	0	1543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2811093	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2811093	0	0
T1	66516	589	0	0
T2	4626	22	0	0
T3	39200	0	0	0
T4	2830	13	0	0
T13	4703	76	0	0
T14	40809	262	0	0
T15	3407	34	0	0
T16	198134	2	0	0
T17	1350	20	0	0
T18	20985	42	0	0
T21	0	483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1490440	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1490440	0	0
T1	66516	667	0	0
T2	4626	29	0	0
T3	39200	0	0	0
T4	2830	17	0	0
T13	4703	94	0	0
T14	40809	353	0	0
T15	3407	34	0	0
T16	198134	1302	0	0
T17	1350	19	0	0
T18	20985	182	0	0
T21	0	2764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2716265	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2716265	0	0
T1	66516	592	0	0
T2	4626	29	0	0
T3	39200	0	0	0
T4	2830	9	0	0
T13	4703	94	0	0
T14	40809	312	0	0
T15	3407	34	0	0
T16	198134	434	0	0
T17	1350	19	0	0
T18	20985	83	0	0
T21	0	1139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1484286	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1484286	0	0
T1	66516	599	0	0
T2	4626	33	0	0
T3	39200	0	0	0
T4	2830	27	0	0
T13	4703	66	0	0
T14	40809	317	0	0
T15	3407	28	0	0
T16	198134	1879	0	0
T17	1350	15	0	0
T18	20985	160	0	0
T19	0	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2980755	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2980755	0	0
T1	66516	371	0	0
T2	4626	33	0	0
T3	39200	0	0	0
T4	2830	20	0	0
T13	4703	66	0	0
T14	40809	227	0	0
T15	3407	28	0	0
T16	198134	735	0	0
T17	1350	15	0	0
T18	20985	50	0	0
T19	0	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1459866	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1459866	0	0
T1	66516	504	0	0
T2	4626	26	0	0
T3	39200	0	0	0
T4	2830	11	0	0
T13	4703	81	0	0
T14	40809	235	0	0
T15	3407	44	0	0
T16	198134	3324	0	0
T17	1350	17	0	0
T18	20985	157	0	0
T19	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3110761	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3110761	0	0
T1	66516	416	0	0
T2	4626	26	0	0
T3	39200	0	0	0
T4	2830	5	0	0
T13	4703	81	0	0
T14	40809	247	0	0
T15	3407	44	0	0
T16	198134	376	0	0
T17	1350	17	0	0
T18	20985	74	0	0
T19	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1444032	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1444032	0	0
T1	66516	616	0	0
T2	4626	325	0	0
T3	39200	0	0	0
T4	2830	44	0	0
T13	4703	84	0	0
T14	40809	209	0	0
T15	3407	32	0	0
T16	198134	2932	0	0
T17	1350	15	0	0
T18	20985	146	0	0
T21	0	1383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2798282	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2798282	0	0
T1	66516	544	0	0
T2	4626	325	0	0
T3	39200	0	0	0
T4	2830	5	0	0
T13	4703	84	0	0
T14	40809	251	0	0
T15	3407	32	0	0
T16	198134	431	0	0
T17	1350	15	0	0
T18	20985	62	0	0
T21	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1475372	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1475372	0	0
T1	66516	565	0	0
T2	4626	24	0	0
T3	39200	0	0	0
T4	2830	17	0	0
T13	4703	80	0	0
T14	40809	186	0	0
T15	3407	30	0	0
T16	198134	2696	0	0
T17	1350	16	0	0
T18	20985	206	0	0
T19	0	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3010969	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3010969	0	0
T1	66516	399	0	0
T2	4626	24	0	0
T3	39200	0	0	0
T4	2830	5	0	0
T13	4703	80	0	0
T14	40809	197	0	0
T15	3407	30	0	0
T16	198134	633	0	0
T17	1350	16	0	0
T18	20985	83	0	0
T19	0	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1499111	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1499111	0	0
T1	66516	669	0	0
T2	4626	28	0	0
T3	39200	1937	0	0
T4	2830	41	0	0
T13	4703	82	0	0
T14	40809	273	0	0
T15	3407	41	0	0
T16	198134	2237	0	0
T17	1350	11	0	0
T18	20985	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3449823	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3449823	0	0
T1	66516	506	0	0
T2	4626	28	0	0
T3	39200	2204	0	0
T4	2830	29	0	0
T13	4703	82	0	0
T14	40809	297	0	0
T15	3407	41	0	0
T16	198134	514	0	0
T17	1350	11	0	0
T18	20985	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1500216	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1500216	0	0
T1	66516	624	0	0
T2	4626	23	0	0
T3	39200	1730	0	0
T4	2830	20	0	0
T13	4703	87	0	0
T14	40809	247	0	0
T15	3407	37	0	0
T16	198134	1630	0	0
T17	1350	16	0	0
T18	20985	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	3788737	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	3788737	0	0
T1	66516	541	0	0
T2	4626	23	0	0
T3	39200	1767	0	0
T4	2830	3	0	0
T13	4703	87	0	0
T14	40809	219	0	0
T15	3407	37	0	0
T16	198134	639	0	0
T17	1350	16	0	0
T18	20985	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1470000	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1470000	0	0
T1	66516	600	0	0
T2	4626	35	0	0
T3	39200	0	0	0
T4	2830	10	0	0
T13	4703	85	0	0
T14	40809	263	0	0
T15	3407	30	0	0
T16	198134	1115	0	0
T17	1350	19	0	0
T18	20985	255	0	0
T19	0	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2939956	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2939956	0	0
T1	66516	535	0	0
T2	4626	35	0	0
T3	39200	0	0	0
T4	2830	4	0	0
T13	4703	85	0	0
T14	40809	224	0	0
T15	3407	30	0	0
T16	198134	654	0	0
T17	1350	19	0	0
T18	20985	110	0	0
T19	0	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1436824	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1436824	0	0
T1	66516	694	0	0
T2	4626	28	0	0
T3	39200	0	0	0
T4	2830	12	0	0
T13	4703	87	0	0
T14	40809	252	0	0
T15	3407	21	0	0
T16	198134	1775	0	0
T17	1350	12	0	0
T18	20985	197	0	0
T20	0	4282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2829810	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2829810	0	0
T1	66516	558	0	0
T2	4626	28	0	0
T3	39200	0	0	0
T4	2830	5	0	0
T13	4703	87	0	0
T14	40809	213	0	0
T15	3407	21	0	0
T16	198134	242	0	0
T17	1350	12	0	0
T18	20985	84	0	0
T20	0	1949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1450404	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1450404	0	0
T1	66516	496	0	0
T2	4626	36	0	0
T3	39200	0	0	0
T4	2830	16	0	0
T13	4703	95	0	0
T14	40809	404	0	0
T15	3407	30	0	0
T16	198134	2793	0	0
T17	1350	22	0	0
T18	20985	185	0	0
T19	0	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2768627	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2768627	0	0
T1	66516	392	0	0
T2	4626	36	0	0
T3	39200	0	0	0
T4	2830	1	0	0
T13	4703	95	0	0
T14	40809	298	0	0
T15	3407	30	0	0
T16	198134	467	0	0
T17	1350	22	0	0
T18	20985	57	0	0
T19	0	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1491936	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1491936	0	0
T1	66516	547	0	0
T2	4626	286	0	0
T3	39200	0	0	0
T4	2830	18	0	0
T13	4703	84	0	0
T14	40809	165	0	0
T15	3407	32	0	0
T16	198134	3116	0	0
T17	1350	19	0	0
T18	20985	136	0	0
T21	0	785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	4215636	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	4215636	0	0
T1	66516	485	0	0
T2	4626	286	0	0
T3	39200	0	0	0
T4	2830	29	0	0
T13	4703	84	0	0
T14	40809	121	0	0
T15	3407	32	0	0
T16	198134	1254	0	0
T17	1350	19	0	0
T18	20985	62	0	0
T21	0	663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1431176	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1431176	0	0
T1	66516	668	0	0
T2	4626	32	0	0
T3	39200	0	0	0
T4	2830	38	0	0
T13	4703	92	0	0
T14	40809	215	0	0
T15	3407	29	0	0
T16	198134	3445	0	0
T17	1350	22	0	0
T18	20985	159	0	0
T19	0	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2811992	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2811992	0	0
T1	66516	511	0	0
T2	4626	32	0	0
T3	39200	0	0	0
T4	2830	7	0	0
T13	4703	92	0	0
T14	40809	210	0	0
T15	3407	29	0	0
T16	198134	410	0	0
T17	1350	22	0	0
T18	20985	67	0	0
T19	0	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	1455552	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	1455552	0	0
T1	66516	781	0	0
T2	4626	22	0	0
T3	39200	0	0	0
T4	2830	13	0	0
T13	4703	82	0	0
T14	40809	273	0	0
T15	3407	32	0	0
T16	198134	2740	0	0
T17	1350	13	0	0
T18	20985	165	0	0
T20	0	2287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297319886	2622318	0	0
DepthKnown_A	297319886	297202165	0	0
RvalidKnown_A	297319886	297202165	0	0
WreadyKnown_A	297319886	297202165	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	2622318	0	0
T1	66516	559	0	0
T2	4626	22	0	0
T3	39200	0	0	0
T4	2830	3	0	0
T13	4703	82	0	0
T14	40809	272	0	0
T15	3407	32	0	0
T16	198134	327	0	0
T17	1350	13	0	0
T18	20985	54	0	0
T20	0	887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297319886	297202165	0	0
T1	66516	66490	0	0
T2	4626	4576	0	0
T3	39200	39118	0	0
T4	2830	2780	0	0
T13	4703	4672	0	0
T14	40809	40802	0	0
T15	3407	3392	0	0
T16	198134	198066	0	0
T17	1350	1290	0	0
T18	20985	20955	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0